gt_pci.c revision 178173
1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */ 2 3/*- 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * PCI configuration support for gt I/O Processor chip. 40 */ 41 42#include <sys/cdefs.h> 43__FBSDID("$FreeBSD: head/sys/mips/mips32/malta/gt_pci.c 178173 2008-04-13 07:44:55Z imp $"); 44 45#include <sys/param.h> 46#include <sys/systm.h> 47 48#include <sys/bus.h> 49#include <sys/interrupt.h> 50#include <sys/malloc.h> 51#include <sys/kernel.h> 52#include <sys/module.h> 53#include <sys/rman.h> 54 55#include <vm/vm.h> 56#include <vm/pmap.h> 57#include <vm/vm_extern.h> 58 59#include <machine/bus.h> 60#include <machine/cpu.h> 61#include <machine/pmap.h> 62 63#include <mips/mips32/malta/maltareg.h> 64 65#include <mips/mips32/malta/gtreg.h> 66#include <mips/mips32/malta/gtvar.h> 67 68#include <isa/isareg.h> 69#include <dev/ic/i8259.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <dev/pci/pcib_private.h> 75#include "pcib_if.h" 76 77 78#define ICU_LEN 16 /* number of ISA IRQs */ 79 80/* 81 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file 82 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions. 83 */ 84#define PIC_OCW1 1 85#define PIC_OCW2 0 86#define PIC_OCW3 0 87 88#define OCW2_SELECT 0 89#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */ 90 91#define OCW3_POLL_IRQ(x) ((x) & 0x7f) 92#define OCW3_POLL_PENDING (1U << 7) 93 94struct gt_pci_softc { 95 device_t sc_dev; 96 bus_space_tag_t sc_st; 97 bus_space_tag_t sc_pciio; 98 bus_space_tag_t sc_pcimem; 99 bus_space_handle_t sc_ioh_icu1; 100 bus_space_handle_t sc_ioh_icu2; 101 bus_space_handle_t sc_ioh_elcr; 102 103 int sc_busno; 104 struct rman sc_mem_rman; 105 struct rman sc_io_rman; 106 struct rman sc_irq_rman; 107 uint32_t sc_mem; 108 uint32_t sc_io; 109 110 struct resource *sc_irq; 111 struct intr_event *sc_eventstab[ICU_LEN]; 112 uint16_t sc_imask; 113 uint16_t sc_elcr; 114 115 uint16_t sc_reserved; 116 117 void *sc_ih; 118}; 119 120static void 121gt_pci_set_icus(struct gt_pci_softc *sc) 122{ 123 /* Enable the cascade IRQ (2) if 8-15 is enabled. */ 124 if ((sc->sc_imask & 0xff00) != 0xff00) 125 sc->sc_imask &= ~(1U << 2); 126 else 127 sc->sc_imask |= (1U << 2); 128 129 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1, 130 sc->sc_imask & 0xff); 131 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1, 132 (sc->sc_imask >> 8) & 0xff); 133 134 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0, 135 sc->sc_elcr & 0xff); 136 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1, 137 (sc->sc_elcr >> 8) & 0xff); 138} 139 140static int 141gt_pci_intr(void *v) 142{ 143 struct gt_pci_softc *sc = v; 144 struct intr_event *event; 145 struct intr_handler *ih; 146 int irq, thread; 147 148 for (;;) { 149 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3, 150 OCW3_SEL | OCW3_P); 151 irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3); 152 if ((irq & OCW3_POLL_PENDING) == 0) 153 { 154 return FILTER_HANDLED; 155 } 156 157 irq = OCW3_POLL_IRQ(irq); 158 159 if (irq == 2) { 160 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 161 PIC_OCW3, OCW3_SEL | OCW3_P); 162 irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2, 163 PIC_OCW3); 164 if (irq & OCW3_POLL_PENDING) 165 irq = OCW3_POLL_IRQ(irq) + 8; 166 else 167 irq = 2; 168 } 169 170 event = sc->sc_eventstab[irq]; 171 thread = 0; 172 173 if (event && !TAILQ_EMPTY(&event->ie_handlers)) 174 { 175 /* Execute fast handlers. */ 176 TAILQ_FOREACH(ih, &event->ie_handlers, ih_next) { 177 if (ih->ih_filter == NULL) 178 thread = 1; 179 else 180 ih->ih_filter(ih->ih_argument); 181 } 182 } 183 184 /* Schedule thread if needed. */ 185 if (thread) 186 intr_event_schedule_thread(event); 187 188 /* Send a specific EOI to the 8259. */ 189 if (irq > 7) { 190 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 191 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL | 192 OCW2_ILS(irq & 7)); 193 irq = 2; 194 } 195 196 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2, 197 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq)); 198 } 199 200 return FILTER_HANDLED; 201} 202 203static int 204gt_pci_probe(device_t dev) 205{ 206 device_set_desc(dev, "GT64120 PCI bridge"); 207 return (0); 208} 209 210static int 211gt_pci_attach(device_t dev) 212{ 213 214 uint32_t busno; 215 struct gt_pci_softc *sc = device_get_softc(dev); 216 int rid; 217 218 busno = 0; 219 sc->sc_dev = dev; 220 sc->sc_busno = busno; 221 sc->sc_pciio = MIPS_BUS_SPACE_IO; 222 sc->sc_pcimem = MIPS_BUS_SPACE_MEM; 223 224 /* Use KSEG1 to access IO ports for it is uncached */ 225 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE); 226 sc->sc_io_rman.rm_type = RMAN_ARRAY; 227 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports"; 228 if (rman_init(&sc->sc_io_rman) != 0 || 229 rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) { 230 panic("gt_pci_attach: failed to set up I/O rman"); 231 } 232 233 /* Use KSEG1 to access PCI memory for it is uncached */ 234 sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE); 235 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 236 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory"; 237 if (rman_init(&sc->sc_mem_rman) != 0 || 238 rman_manage_region(&sc->sc_mem_rman, 239 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) { 240 panic("gt_pci_attach: failed to set up memory rman"); 241 } 242 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 243 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs"; 244 if (rman_init(&sc->sc_irq_rman) != 0 || 245 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) 246 panic("gt_pci_attach: failed to set up IRQ rman"); 247 248 /* 249 * Map the PIC/ELCR registers. 250 */ 251#if 0 252 if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0) 253 device_printf(dev, "unable to map ELCR registers\n"); 254 if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0) 255 device_printf(dev, "unable to map ICU1 registers\n"); 256 if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) 257 device_printf(dev, "unable to map ICU2 registers\n"); 258#else 259 sc->sc_ioh_elcr = sc->sc_io + 0x4d0; 260 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1; 261 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2; 262#endif 263 264 265 /* All interrupts default to "masked off". */ 266 sc->sc_imask = 0xffff; 267 268 /* All interrupts default to edge-triggered. */ 269 sc->sc_elcr = 0; 270 271 /* 272 * Initialize the 8259s. 273 */ 274 /* reset, program device, 4 bytes */ 275 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0, 276 ICW1_RESET | ICW1_IC4); 277 /* 278 * XXX: values from NetBSD's <dev/ic/i8259reg.h> 279 */ 280 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, 281 0/*XXX*/); 282 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, 283 1 << 2); 284 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, 285 ICW4_8086); 286 287 /* mask all interrupts */ 288 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0, 289 sc->sc_imask & 0xff); 290 291 /* enable special mask mode */ 292 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, 293 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 294 295 /* read IRR by default */ 296 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1, 297 OCW3_SEL | OCW3_RR); 298 299 /* reset, program device, 4 bytes */ 300 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0, 301 ICW1_RESET | ICW1_IC4); 302 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, 303 0/*XXX*/); 304 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, 305 1 << 2); 306 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, 307 ICW4_8086); 308 309 /* mask all interrupts */ 310 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0, 311 sc->sc_imask & 0xff); 312 313 /* enable special mask mode */ 314 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, 315 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 316 317 /* read IRR by default */ 318 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1, 319 OCW3_SEL | OCW3_RR); 320 321 /* 322 * Default all interrupts to edge-triggered. 323 */ 324 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0, 325 sc->sc_elcr & 0xff); 326 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1, 327 (sc->sc_elcr >> 8) & 0xff); 328 329 /* 330 * Some ISA interrupts are reserved for devices that 331 * we know are hard-wired to certain IRQs. 332 */ 333 sc->sc_reserved = 334 (1U << 0) | /* timer */ 335 (1U << 1) | /* keyboard controller (keyboard) */ 336 (1U << 2) | /* PIC cascade */ 337 (1U << 3) | /* COM 2 */ 338 (1U << 4) | /* COM 1 */ 339 (1U << 6) | /* floppy */ 340 (1U << 7) | /* centronics */ 341 (1U << 8) | /* RTC */ 342 (1U << 9) | /* I2C */ 343 (1U << 12) | /* keyboard controller (mouse) */ 344 (1U << 14) | /* IDE primary */ 345 (1U << 15); /* IDE secondary */ 346 347 /* Hook up our interrupt handler. */ 348 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 349 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1, 350 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 351 device_printf(dev, "unable to allocate IRQ resource\n"); 352 return ENXIO; 353 } 354 355 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 356 gt_pci_intr, NULL, sc, &sc->sc_ih))) { 357 device_printf(dev, 358 "WARNING: unable to register interrupt handler\n"); 359 return ENXIO; 360 } 361 362 /* Initialize memory and i/o rmans. */ 363 device_add_child(dev, "pci", busno); 364 return (bus_generic_attach(dev)); 365} 366 367static int 368gt_pci_maxslots(device_t dev) 369{ 370 return (PCI_SLOTMAX); 371} 372 373static int 374gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func, 375 int reg, uint32_t *addr) 376{ 377 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg; 378 379 return (0); 380} 381 382static uint32_t 383gt_pci_read_config(device_t dev, int bus, int slot, int func, int reg, 384 int bytes) 385{ 386 struct gt_pci_softc *sc = device_get_softc(dev); 387 uint32_t data; 388 uint32_t addr; 389 uint32_t shift, mask; 390 391 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 392 return (uint32_t)(-1); 393 394 /* Clear cause register bits. */ 395 GT_REGVAL(GT_INTR_CAUSE) = 0; 396 397 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr; 398 data = GT_REGVAL(GT_PCI0_CFG_DATA); 399 400 /* Check for master abort. */ 401 if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0)) 402 data = (uint32_t) -1; 403 404 /* 405 * XXX: We assume that words readed from GT chip are BE. 406 * Should we set the mode explicitly during chip 407 * Initialization? 408 */ 409 switch(reg % 4) 410 { 411 case 3: 412 shift = 24; 413 break; 414 case 2: 415 shift = 16; 416 break; 417 case 1: 418 shift = 8; 419 break; 420 default: 421 shift = 0; 422 break; 423 } 424 425 switch(bytes) 426 { 427 case 1: 428 mask = 0xff; 429 data = (data >> shift) & mask; 430 break; 431 case 2: 432 mask = 0xffff; 433 if(reg % 4 == 0) 434 data = data & mask; 435 else 436 data = (data >> 16) & mask; 437 break; 438 case 4: 439 break; 440 default: 441 panic("gt_pci_readconfig: wrong bytes count"); 442 break; 443 } 444#if 0 445 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 446 bus, slot, func, reg, data, bytes); 447#endif 448 449 return (data); 450} 451 452static void 453gt_pci_write_config(device_t dev, int bus, int slot, int func, int reg, 454 uint32_t data, int bytes) 455{ 456 struct gt_pci_softc *sc = device_get_softc(dev); 457 uint32_t addr; 458 uint32_t reg_data; 459 uint32_t shift, mask; 460 461 if(bytes != 4) 462 { 463 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4); 464 465 /* 466 * XXX: We assume that words readed from GT chip are BE. 467 * Should we set the mode explicitly during chip 468 * Initialization? 469 */ 470 switch(reg % 4) 471 { 472 case 3: 473 shift = 24; 474 break; 475 case 2: 476 shift = 16; 477 break; 478 case 1: 479 shift = 8; 480 break; 481 default: 482 shift = 0; 483 break; 484 } 485 486 switch(bytes) 487 { 488 case 1: 489 mask = 0xff; 490 data = (reg_data & ~ (mask << shift)) | (data << shift); 491 break; 492 case 2: 493 mask = 0xffff; 494 if(reg % 4 == 0) 495 data = (reg_data & ~mask) | data; 496 else 497 data = (reg_data & ~ (mask << shift)) | 498 (data << shift); 499 break; 500 case 4: 501 break; 502 default: 503 panic("gt_pci_readconfig: wrong bytes count"); 504 break; 505 } 506 } 507 508 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 509 return; 510 511 /* The galileo has problems accessing device 31. */ 512 if (bus == 0 && slot == 31) 513 return; 514 515 /* XXX: no support for bus > 0 yet */ 516 if (bus > 0) 517 return; 518 519 /* Clear cause register bits. */ 520 GT_REGVAL(GT_INTR_CAUSE) = 0; 521 522 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | addr; 523 GT_REGVAL(GT_PCI0_CFG_DATA) = data; 524} 525 526static int 527gt_pci_route_interrupt(device_t pcib, device_t dev, int pin) 528{ 529 int bus; 530 int device; 531 int func; 532 /* struct gt_pci_softc *sc = device_get_softc(pcib); */ 533 bus = pci_get_bus(dev); 534 device = pci_get_slot(dev); 535 func = pci_get_function(dev); 536 /* 537 * XXXMIPS: We need routing logic. This is just a stub . 538 */ 539 switch (device) { 540 case 9: /* 541 * PIIX4 IDE adapter. HW IRQ0 542 */ 543 return 0; 544 default: 545 printf("No mapping for %d/%d/%d/%d\n", bus, device, func, pin); 546 547 } 548 return (0); 549 550} 551 552static int 553gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 554{ 555 struct gt_pci_softc *sc = device_get_softc(dev); 556 switch (which) { 557 case PCIB_IVAR_DOMAIN: 558 *result = 0; 559 return (0); 560 case PCIB_IVAR_BUS: 561 *result = sc->sc_busno; 562 return (0); 563 564 } 565 return (ENOENT); 566} 567 568static int 569gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 570{ 571 struct gt_pci_softc * sc = device_get_softc(dev); 572 573 switch (which) { 574 case PCIB_IVAR_BUS: 575 sc->sc_busno = result; 576 return (0); 577 } 578 return (ENOENT); 579} 580 581static struct resource * 582gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 583 u_long start, u_long end, u_long count, u_int flags) 584{ 585 struct gt_pci_softc *sc = device_get_softc(bus); 586 struct resource *rv = NULL; 587 struct rman *rm; 588 bus_space_tag_t bt = 0; 589 bus_space_handle_t bh = 0; 590 591 switch (type) { 592 case SYS_RES_IRQ: 593 rm = &sc->sc_irq_rman; 594 break; 595 case SYS_RES_MEMORY: 596 rm = &sc->sc_mem_rman; 597 bt = sc->sc_pcimem; 598 bh = sc->sc_mem; 599 break; 600 case SYS_RES_IOPORT: 601 rm = &sc->sc_io_rman; 602 bt = sc->sc_pciio; 603 bh = sc->sc_io; 604 break; 605 default: 606 return (NULL); 607 } 608 609 rv = rman_reserve_resource(rm, start, end, count, flags, child); 610 if (rv == NULL) 611 return (NULL); 612 rman_set_rid(rv, *rid); 613 if (type != SYS_RES_IRQ) { 614 bh += (rman_get_start(rv)); 615 616 rman_set_bustag(rv, bt); 617 rman_set_bushandle(rv, bh); 618 if (flags & RF_ACTIVE) { 619 if (bus_activate_resource(child, type, *rid, rv)) { 620 rman_release_resource(rv); 621 return (NULL); 622 } 623 } 624 } 625 return (rv); 626} 627 628static int 629gt_pci_activate_resource(device_t bus, device_t child, int type, int rid, 630 struct resource *r) 631{ 632 bus_space_handle_t p; 633 int error; 634 635 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 636 error = bus_space_map(rman_get_bustag(r), 637 rman_get_bushandle(r), rman_get_size(r), 0, &p); 638 if (error) 639 return (error); 640 rman_set_bushandle(r, p); 641 } 642 return (rman_activate_resource(r)); 643} 644 645static int 646gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 647 int flags, driver_filter_t *filt, driver_intr_t *handler, 648 void *arg, void **cookiep) 649{ 650 struct gt_pci_softc *sc = device_get_softc(dev); 651 struct intr_event *event; 652 int irq, error; 653 654 irq = rman_get_start(ires); 655 if (irq >= ICU_LEN || irq == 2) 656 panic("%s: bad irq or type", __func__); 657 658 event = sc->sc_eventstab[irq]; 659 if (event == NULL) { 660 error = intr_event_create(&event, (void *)irq, 0, 661 (mask_fn)mips_mask_irq, (mask_fn)mips_unmask_irq, 662 (mask_fn)mips_unmask_irq, NULL, "gt_pci intr%d:", irq); 663 if (error) 664 return 0; 665 sc->sc_eventstab[irq] = event; 666 } 667 668 intr_event_add_handler(event, device_get_nameunit(child), filt, 669 handler, arg, intr_priority(flags), flags, cookiep); 670 671 /* Enable it, set trigger mode. */ 672 sc->sc_imask &= ~(1 << irq); 673 sc->sc_elcr &= ~(1 << irq); 674 675 gt_pci_set_icus(sc); 676 677 return 0; 678} 679 680static int 681gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res, 682 void *cookie) 683{ 684 return (intr_event_remove_handler(cookie)); 685} 686 687static device_method_t gt_pci_methods[] = { 688 /* Device interface */ 689 DEVMETHOD(device_probe, gt_pci_probe), 690 DEVMETHOD(device_attach, gt_pci_attach), 691 DEVMETHOD(device_shutdown, bus_generic_shutdown), 692 DEVMETHOD(device_suspend, bus_generic_suspend), 693 DEVMETHOD(device_resume, bus_generic_resume), 694 695 /* Bus interface */ 696 DEVMETHOD(bus_print_child, bus_generic_print_child), 697 DEVMETHOD(bus_read_ivar, gt_read_ivar), 698 DEVMETHOD(bus_write_ivar, gt_write_ivar), 699 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource), 700 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 701 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource), 702 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 703 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr), 704 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr), 705 706 /* pcib interface */ 707 DEVMETHOD(pcib_maxslots, gt_pci_maxslots), 708 DEVMETHOD(pcib_read_config, gt_pci_read_config), 709 DEVMETHOD(pcib_write_config, gt_pci_write_config), 710 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt), 711 712 {0, 0} 713}; 714 715static driver_t gt_pci_driver = { 716 "pcib", 717 gt_pci_methods, 718 sizeof(struct gt_pci_softc), 719}; 720 721static devclass_t gt_pci_devclass; 722 723DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0); 724