pte.h revision 209482 
1/*-
2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/include/pte.h 209482 2010-06-23 19:42:01Z jchandra $
27 */
28
29#ifndef	_MACHINE_PTE_H_
30#define	_MACHINE_PTE_H_
31
32/*
33 * TLB and PTE management.  Most things operate within the context of
34 * EntryLo0,1, and begin with TLBLO_.  Things which work with EntryHi
35 * start with TLBHI_.  PTE bits begin with PTE_.
36 *
37 * Note that we use the same size VM and TLB pages.
38 */
39#define	TLB_PAGE_SHIFT	(PAGE_SHIFT)
40#define	TLB_PAGE_SIZE	(1 << TLB_PAGE_SHIFT)
41#define	TLB_PAGE_MASK	(TLB_PAGE_SIZE - 1)
42
43/*
44 * TLB PageMask register.  Has mask bits set above the default, 4K, page mask.
45 */
46#define	TLBMASK_SHIFT	(13)
47#define	TLBMASK_MASK	((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
48
49/*
50 * PFN for EntryLo register.  Upper bits are 0, which is to say that
51 * bit 29 is the last hardware bit;  Bits 30 and upwards (EntryLo is
52 * 64 bit though it can be referred to in 32-bits providing 2 software
53 * bits safely.  We use it as 64 bits to get many software bits, and
54 * god knows what else.) are unacknowledged by hardware.  They may be
55 * written as anything, but otherwise they have as much meaning as
56 * other 0 fields.
57 */
58#define	TLBLO_SWBITS_SHIFT	(30)
59#define	TLBLO_SWBITS_MASK	(0x3U << TLBLO_SWBITS_SHIFT)
60#define	TLBLO_PFN_SHIFT		(6)
61#define	TLBLO_PFN_MASK		(0x3FFFFFC0)
62#define	TLBLO_PA_TO_PFN(pa)	((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
63#define	TLBLO_PFN_TO_PA(pfn)	((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
64#define	TLBLO_PTE_TO_PFN(pte)	((pte) & TLBLO_PFN_MASK)
65#define	TLBLO_PTE_TO_PA(pte)	(TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
66
67/*
68 * VPN for EntryHi register.  Upper two bits select user, supervisor,
69 * or kernel.  Bits 61 to 40 copy bit 63.  VPN2 is bits 39 and down to
70 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*.  From bit 12
71 * to bit 8 there is a 5-bit 0 field.  Low byte is ASID.
72 *
73 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
74 */
75#define	TLBHI_ASID_MASK		(0xff)
76#define	TLBHI_ENTRY(va, asid)	(((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
77
78#ifndef _LOCORE
79typedef	uint32_t pt_entry_t;
80typedef	pt_entry_t *pd_entry_t;
81#endif
82
83#define	PDESIZE		sizeof(pd_entry_t)	/* for assembly files */
84#define	PTESIZE		sizeof(pt_entry_t)	/* for assembly files */
85
86/*
87 * TLB flags managed in hardware:
88 * 	C:	Cache attribute.
89 * 	D:	Dirty bit.  This means a page is writable.  It is not
90 * 		set at first, and a write is trapped, and the dirty
91 * 		bit is set.  See also PTE_RO.
92 * 	V:	Valid bit.  Obvious, isn't it?
93 * 	G:	Global bit.  This means that this mapping is present
94 * 		in EVERY address space, and to ignore the ASID when
95 * 		it is matched.
96 */
97#define	PTE_C(attr)	((attr & 0x07) << 3)
98#define	PTE_C_UNCACHED	(PTE_C(0x02))
99/*
100 * The preferred cache attribute for cacheable pages, this can be
101 * implementation dependent. We will use the standard value 0x3 as
102 * default.
103 */
104#if defined(CPU_SB1)
105#define	PTE_C_CACHE	(PTE_C(0x05))
106#else
107#define	PTE_C_CACHE	(PTE_C(0x03))
108#endif
109#define	PTE_D		0x04
110#define	PTE_V		0x02
111#define	PTE_G		0x01
112
113/*
114 * VM flags managed in software:
115 * 	RO:	Read only.  Never set PTE_D on this page, and don't
116 * 		listen to requests to write to it.
117 * 	W:	Wired.  ???
118 */
119#define	PTE_RO	(0x01 << TLBLO_SWBITS_SHIFT)
120#define	PTE_W	(0x02 << TLBLO_SWBITS_SHIFT)
121
122/*
123 * PTE management functions for bits defined above.
124 *
125 * XXX Can make these atomics, but some users of them are using PTEs in local
126 * registers and such and don't need the overhead.
127 */
128#define	pte_clear(pte, bit)	(*(pte) &= ~(bit))
129#define	pte_set(pte, bit)	(*(pte) |= (bit))
130#define	pte_test(pte, bit)	((*(pte) & (bit)) == (bit))
131
132#endif /* !_MACHINE_PTE_H_ */
133