pte.h revision 209243 
1/*-
2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/include/pte.h 209243 2010-06-17 05:03:01Z jchandra $
27 */
28
29#ifndef	_MACHINE_PTE_H_
30#define	_MACHINE_PTE_H_
31
32/*
33 * TLB and PTE management.  Most things operate within the context of
34 * EntryLo0,1, and begin with TLBLO_.  Things which work with EntryHi
35 * start with TLBHI_.  PTE bits begin with PG_.
36 *
37 * Note that we use the same size VM and TLB pages.
38 */
39#define	TLB_PAGE_SHIFT	(PAGE_SHIFT)
40#define	TLB_PAGE_SIZE	(1 << TLB_PAGE_SHIFT)
41#define	TLB_PAGE_MASK	(TLB_PAGE_SIZE - 1)
42
43/*
44 * TLB PageMask register.  Has mask bits set above the default, 4K, page mask.
45 */
46#define	TLBMASK_SHIFT	(13)
47#define	TLBMASK_MASK	((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
48
49/*
50 * PFN for EntryLo register.  Upper bits are 0, which is to say that
51 * bit 29 is the last hardware bit;  Bits 30 and upwards (EntryLo is
52 * 64 bit though it can be referred to in 32-bits providing 2 software
53 * bits safely.  We use it as 64 bits to get many software bits, and
54 * god knows what else.) are unacknowledged by hardware.  They may be
55 * written as anything, but otherwise they have as much meaning as
56 * other 0 fields.
57 */
58#define	TLBLO_SWBITS_SHIFT	(30)
59#define	TLBLO_SWBITS_MASK	(0x3U << TLBLO_SWBITS_SHIFT)
60#define	TLBLO_PFN_SHIFT		(6)
61#define	TLBLO_PFN_MASK		(0x3FFFFFC0)
62#define	TLBLO_PA_TO_PFN(pa)	((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
63#define	TLBLO_PFN_TO_PA(pfn)	((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
64#define	TLBLO_PTE_TO_PFN(pte)	((pte) & TLBLO_PFN_MASK)
65#define	TLBLO_PTE_TO_PA(pte)	(TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
66
67/*
68 * VPN for EntryHi register.  Upper two bits select user, supervisor,
69 * or kernel.  Bits 61 to 40 copy bit 63.  VPN2 is bits 39 and down to
70 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*.  From bit 12
71 * to bit 8 there is a 5-bit 0 field.  Low byte is ASID.
72 *
73 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
74 */
75#define	TLBHI_ASID_MASK		(0xff)
76#define	TLBHI_ENTRY(va, asid)	(((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
77
78#ifndef _LOCORE
79typedef unsigned int pt_entry_t;
80typedef pt_entry_t *pd_entry_t;
81#endif
82
83#define	PDESIZE		sizeof(pd_entry_t)	/* for assembly files */
84#define	PTESIZE		sizeof(pt_entry_t)	/* for assembly files */
85
86#define	PT_ENTRY_NULL	((pt_entry_t *) 0)
87
88#define	PTE_WIRED	0x80000000	/* SW */
89#define	PTE_W		PTE_WIRED
90#define	PTE_RO		0x40000000	/* SW */
91
92#define	PTE_G		0x00000001	/* HW */
93#define	PTE_V		0x00000002
94/*#define	PTE_NV		0x00000000       Not Used */
95#define	PTE_M		0x00000004
96#define	PTE_RW		PTE_M
97#define PTE_ODDPG       0x00001000
98/*#define	PG_ATTR		0x0000003f  Not Used */
99#define	PTE_UNCACHED	0x00000010
100#ifdef CPU_SB1
101#define	PTE_CACHE	0x00000028	/* cacheable coherent */
102#else
103#define	PTE_CACHE	0x00000018
104#endif
105/*#define	PG_CACHEMODE	0x00000038 Not Used*/
106#define	PTE_ROPAGE	(PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
107#define	PTE_RWPAGE	(PTE_V | PTE_M | PTE_CACHE)  /* Not wr-prot not clean */
108#define	PTE_CWPAGE	(PTE_V | PTE_CACHE)	   /* Not wr-prot but clean */
109#define	PTE_IOPAGE	(PTE_G | PTE_V | PTE_M | PTE_UNCACHED)
110#define	PTE_FRAME	0x3fffffc0
111#define PTE_HVPN        0xffffe000      /* Hardware page no mask */
112#define PTE_ASID        0x000000ff      /* Address space ID */
113
114
115/* User virtual to pte offset in page table */
116#define	vad_to_pte_offset(adr)	(((adr) >> PAGE_SHIFT) & (NPTEPG -1))
117
118#define	mips_pg_v(entry)	((entry) & PTE_V)
119#define	mips_pg_wired(entry)	((entry) & PTE_WIRED)
120#define	mips_pg_m_bit()		(PTE_M)
121#define	mips_pg_rw_bit()	(PTE_M)
122#define	mips_pg_ro_bit()	(PTE_RO)
123#define	mips_pg_ropage_bit()	(PTE_ROPAGE)
124#define	mips_pg_rwpage_bit()	(PTE_RWPAGE)
125#define	mips_pg_cwpage_bit()	(PTE_CWPAGE)
126#define	mips_pg_global_bit()	(PTE_G)
127#define	mips_pg_wired_bit()	(PTE_WIRED)
128
129#endif /* !_MACHINE_PTE_H_ */
130