pte.h revision 178172
1/* $OpenBSD: pte.h,v 1.4 1998/01/28 13:46:25 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department and Ralph Campbell. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah Hdr: pte.h 1.11 89/09/03 41 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93 42 * JNPR: pte.h,v 1.1.4.1 2007/09/10 06:20:19 girish 43 * $FreeBSD: head/sys/mips/include/pte.h 178172 2008-04-13 07:27:37Z imp $ 44 */ 45 46#ifndef _MACHINE_PTE_H_ 47#define _MACHINE_PTE_H_ 48 49#include <machine/endian.h> 50 51/* 52 * MIPS hardware page table entry 53 */ 54 55#ifndef _LOCORE 56struct pte { 57#if BYTE_ORDER == BIG_ENDIAN 58unsigned int pg_prot:2, /* SW: access control */ 59 pg_pfnum:24, /* HW: core page frame number or 0 */ 60 pg_attr:3, /* HW: cache attribute */ 61 pg_m:1, /* HW: modified (dirty) bit */ 62 pg_v:1, /* HW: valid bit */ 63 pg_g:1; /* HW: ignore pid bit */ 64#endif 65#if BYTE_ORDER == LITTLE_ENDIAN 66unsigned int pg_g:1, /* HW: ignore pid bit */ 67 pg_v:1, /* HW: valid bit */ 68 pg_m:1, /* HW: modified (dirty) bit */ 69 pg_attr:3, /* HW: cache attribute */ 70 pg_pfnum:24, /* HW: core page frame number or 0 */ 71 pg_prot:2; /* SW: access control */ 72#endif 73}; 74 75/* 76 * Structure defining an tlb entry data set. 77 */ 78 79struct tlb { 80 int tlb_mask; 81 int tlb_hi; 82 int tlb_lo0; 83 int tlb_lo1; 84}; 85 86typedef unsigned long pt_entry_t; 87typedef pt_entry_t *pd_entry_t; 88 89#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 90#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 91 92#endif /* _LOCORE */ 93 94#define PT_ENTRY_NULL ((pt_entry_t *) 0) 95 96#define PTE_WIRED 0x80000000 /* SW */ 97#define PTE_W PTE_WIRED 98#define PTE_RO 0x40000000 /* SW */ 99 100#define PTE_G 0x00000001 /* HW */ 101#define PTE_V 0x00000002 102/*#define PTE_NV 0x00000000 Not Used */ 103#define PTE_M 0x00000004 104#define PTE_RW PTE_M 105#define PTE_ODDPG 0x00001000 106/*#define PG_ATTR 0x0000003f Not Used */ 107#define PTE_UNCACHED 0x00000010 108#define PTE_CACHE 0x00000018 109/*#define PG_CACHEMODE 0x00000038 Not Used*/ 110#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */ 111#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */ 112#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */ 113#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED) 114#define PTE_FRAME 0x3fffffc0 115#define PTE_HVPN 0xffffe000 /* Hardware page no mask */ 116#define PTE_ASID 0x000000ff /* Address space ID */ 117 118#define PTE_SHIFT 6 119#define pfn_is_ext(x) ((x) & 0x3c000000) 120#define vad_to_pfn(x) (((unsigned)(x) >> PTE_SHIFT) & PTE_FRAME) 121#define vad_to_pfn64(x) ((quad_t)(x) >> PTE_SHIFT) & PTE_FRAME) 122#define pfn_to_vad(x) (((x) & PTE_FRAME) << PTE_SHIFT) 123 124/* User viritual to pte offset in page table */ 125#define vad_to_pte_offset(adr) (((adr) >> PGSHIFT) & (NPTEPG -1)) 126 127#define mips_pg_v(entry) ((entry) & PTE_V) 128#define mips_pg_wired(entry) ((entry) & PTE_WIRED) 129#define mips_pg_m_bit() (PTE_M) 130#define mips_pg_rw_bit() (PTE_M) 131#define mips_pg_ro_bit() (PTE_RO) 132#define mips_pg_ropage_bit() (PTE_ROPAGE) 133#define mips_pg_rwpage_bit() (PTE_RWPAGE) 134#define mips_pg_cwpage_bit() (PTE_CWPAGE) 135#define mips_pg_global_bit() (PTE_G) 136#define mips_pg_wired_bit() (PTE_WIRED) 137#define mips_tlbpfn_to_paddr(x) pfn_to_vad((x)) 138#define mips_paddr_to_tlbpfn(x) vad_to_pfn((x)) 139 140/* These are not used */ 141#define PTE_SIZE_4K 0x00000000 142#define PTE_SIZE_16K 0x00006000 143#define PTE_SIZE_64K 0x0001e000 144#define PTE_SIZE_256K 0x0007e000 145#define PTE_SIZE_1M 0x001fe000 146#define PTE_SIZE_4M 0x007fe000 147#define PTE_SIZE_16M 0x01ffe000 148 149#endif /* !_MACHINE_PTE_H_ */ 150