1178172Simp/*- 2209243Sjchandra * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3209243Sjchandra * All rights reserved. 4178172Simp * 5178172Simp * Redistribution and use in source and binary forms, with or without 6178172Simp * modification, are permitted provided that the following conditions 7178172Simp * are met: 8178172Simp * 1. Redistributions of source code must retain the above copyright 9178172Simp * notice, this list of conditions and the following disclaimer. 10178172Simp * 2. Redistributions in binary form must reproduce the above copyright 11178172Simp * notice, this list of conditions and the following disclaimer in the 12178172Simp * documentation and/or other materials provided with the distribution. 13178172Simp * 14209243Sjchandra * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17209243Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24178172Simp * SUCH DAMAGE. 25178172Simp * 26178172Simp * $FreeBSD$ 27178172Simp */ 28178172Simp 29209243Sjchandra#ifndef _MACHINE_PTE_H_ 30178172Simp#define _MACHINE_PTE_H_ 31178172Simp 32209805Sjchandra#ifndef _LOCORE 33217354Sjchandra#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 34217354Sjchandratypedef uint64_t pt_entry_t; 35217354Sjchandra#else 36209805Sjchandratypedef uint32_t pt_entry_t; 37217354Sjchandra#endif 38209805Sjchandratypedef pt_entry_t *pd_entry_t; 39209805Sjchandra#endif 40209805Sjchandra 41209243Sjchandra/* 42209243Sjchandra * TLB and PTE management. Most things operate within the context of 43209243Sjchandra * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 44209482Sjchandra * start with TLBHI_. PTE bits begin with PTE_. 45209243Sjchandra * 46209243Sjchandra * Note that we use the same size VM and TLB pages. 47209243Sjchandra */ 48209243Sjchandra#define TLB_PAGE_SHIFT (PAGE_SHIFT) 49209243Sjchandra#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT) 50209243Sjchandra#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1) 51178172Simp 52178172Simp/* 53209243Sjchandra * TLB PageMask register. Has mask bits set above the default, 4K, page mask. 54178172Simp */ 55209243Sjchandra#define TLBMASK_SHIFT (13) 56209243Sjchandra#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT) 57178172Simp 58178172Simp/* 59257017Sbrooks * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB 60257017Sbrooks * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and 61257017Sbrooks * "EntryLo"). MIPS4k and MIPS64 both define certain bits in TLB entries as 62257017Sbrooks * reserved, and these must be zero-filled by software. We overload these 63257017Sbrooks * bits in PTE entries to hold PTE_ flags such as RO, W, and MANAGED. 64257017Sbrooks * However, we must mask these out when writing to TLB entries to ensure that 65257017Sbrooks * they do not become visible to hardware -- especially on MIPS64r2 which has 66257017Sbrooks * an extended physical memory space. 67257017Sbrooks * 68257017Sbrooks * When using n64 and n32, shift software-defined bits into the MIPS64r2 69257017Sbrooks * reserved range, which runs from bit 55 ... 63. In other configurations 70257017Sbrooks * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31. 71257017Sbrooks * 72257017Sbrooks * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top 73257017Sbrooks * bit of PFN to a non-zero value, as software is using it! This physical 74257017Sbrooks * memory size limit may not be sufficiently enforced elsewhere. 75178172Simp */ 76217354Sjchandra#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 77257017Sbrooks#define TLBLO_SWBITS_SHIFT (55) 78257017Sbrooks#define TLBLO_SWBITS_CLEAR_SHIFT (9) 79217354Sjchandra#define TLBLO_PFN_MASK 0x3FFFFFFC0ULL 80217354Sjchandra#else 81239964Salc#define TLBLO_SWBITS_SHIFT (29) 82257017Sbrooks#define TLBLO_SWBITS_CLEAR_SHIFT (3) 83239964Salc#define TLBLO_PFN_MASK (0x1FFFFFC0) 84217354Sjchandra#endif 85209243Sjchandra#define TLBLO_PFN_SHIFT (6) 86239964Salc#define TLBLO_SWBITS_MASK ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT) 87209243Sjchandra#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 88209243Sjchandra#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 89209243Sjchandra#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 90209243Sjchandra#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 91209482Sjchandra 92209243Sjchandra/* 93209805Sjchandra * XXX This comment is not correct for anything more modern than R4K. 94209805Sjchandra * 95209243Sjchandra * VPN for EntryHi register. Upper two bits select user, supervisor, 96209243Sjchandra * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 97209243Sjchandra * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 98209243Sjchandra * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 99209243Sjchandra * 100209805Sjchandra * XXX This comment is not correct for FreeBSD. 101209243Sjchandra * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 102209243Sjchandra */ 103209243Sjchandra#define TLBHI_ASID_MASK (0xff) 104209929Sjchandra#if defined(__mips_n64) 105209929Sjchandra#define TLBHI_R_SHIFT 62 106209929Sjchandra#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT) 107209929Sjchandra#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT) 108209929Sjchandra#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT) 109209929Sjchandra#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT) 110209929Sjchandra#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK) 111209929Sjchandra#define TLBHI_FILL_SHIFT 40 112209929Sjchandra#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1) 113209929Sjchandra#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT)) 114209929Sjchandra#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK) 115209929Sjchandra#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \ 116209929Sjchandra (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \ 117209929Sjchandra ((asid) & TLBHI_ASID_MASK)) 118217354Sjchandra#else /* !defined(__mips_n64) */ 119209645Sjchandra#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 120209645Sjchandra#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 121217354Sjchandra#endif /* defined(__mips_n64) */ 122178172Simp 123209482Sjchandra/* 124209482Sjchandra * TLB flags managed in hardware: 125209482Sjchandra * C: Cache attribute. 126209482Sjchandra * D: Dirty bit. This means a page is writable. It is not 127209482Sjchandra * set at first, and a write is trapped, and the dirty 128209482Sjchandra * bit is set. See also PTE_RO. 129209482Sjchandra * V: Valid bit. Obvious, isn't it? 130209482Sjchandra * G: Global bit. This means that this mapping is present 131209482Sjchandra * in EVERY address space, and to ignore the ASID when 132209482Sjchandra * it is matched. 133209482Sjchandra */ 134217354Sjchandra#define PTE_C(attr) ((attr & 0x07) << 3) 135217354Sjchandra#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED)) 136217354Sjchandra#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED)) 137217354Sjchandra#define PTE_D 0x04 138217354Sjchandra#define PTE_V 0x02 139217354Sjchandra#define PTE_G 0x01 140178172Simp 141209482Sjchandra/* 142209482Sjchandra * VM flags managed in software: 143209482Sjchandra * RO: Read only. Never set PTE_D on this page, and don't 144209482Sjchandra * listen to requests to write to it. 145209482Sjchandra * W: Wired. ??? 146239964Salc * MANAGED:Managed. This PTE maps a managed page. 147257017Sbrooks * 148257017Sbrooks * These bits should not be written into the TLB, so must first be masked out 149257017Sbrooks * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly. 150209482Sjchandra */ 151217354Sjchandra#define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT) 152217354Sjchandra#define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT) 153239964Salc#define PTE_MANAGED ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT) 154178172Simp 155209482Sjchandra/* 156209482Sjchandra * PTE management functions for bits defined above. 157209482Sjchandra */ 158209482Sjchandra#define pte_clear(pte, bit) (*(pte) &= ~(bit)) 159209482Sjchandra#define pte_set(pte, bit) (*(pte) |= (bit)) 160209482Sjchandra#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit)) 161178172Simp 162217354Sjchandra/* Assembly support for PTE access*/ 163217354Sjchandra#ifdef LOCORE 164217354Sjchandra#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */ 165217354Sjchandra#define PTESHIFT 3 166217354Sjchandra#define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */ 167217354Sjchandra#define PTEMASK 0xff8 168217354Sjchandra#define PTESIZE 8 169217354Sjchandra#define PTE_L ld 170217354Sjchandra#define PTE_MTC0 dmtc0 171217354Sjchandra#define CLEAR_PTE_SWBITS(pr) 172217354Sjchandra#else 173217354Sjchandra#define PTESHIFT 2 174217354Sjchandra#define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */ 175217354Sjchandra#define PTEMASK 0xffc 176217354Sjchandra#define PTESIZE 4 177217354Sjchandra#define PTE_L lw 178217354Sjchandra#define PTE_MTC0 mtc0 179257017Sbrooks#define CLEAR_PTE_SWBITS(r) LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */ 180217354Sjchandra#endif /* defined(__mips_n64) || defined(__mips_n32) */ 181217354Sjchandra 182217354Sjchandra#if defined(__mips_n64) 183217354Sjchandra#define PTRSHIFT 3 184217354Sjchandra#define PDEPTRMASK 0xff8 185217354Sjchandra#else 186217354Sjchandra#define PTRSHIFT 2 187217354Sjchandra#define PDEPTRMASK 0xffc 188217354Sjchandra#endif 189217354Sjchandra 190217354Sjchandra#endif /* LOCORE */ 191292609Sadrian 192292609Sadrian/* PageMask Register (CP0 Register 5, Select 0) Values */ 193292609Sadrian#define MIPS3_PGMASK_MASKX 0x00001800 194292609Sadrian#define MIPS3_PGMASK_4K 0x00000000 195292609Sadrian#define MIPS3_PGMASK_16K 0x00006000 196292609Sadrian#define MIPS3_PGMASK_64K 0x0001e000 197292609Sadrian#define MIPS3_PGMASK_256K 0x0007e000 198292609Sadrian#define MIPS3_PGMASK_1M 0x001fe000 199292609Sadrian#define MIPS3_PGMASK_4M 0x007fe000 200292609Sadrian#define MIPS3_PGMASK_16M 0x01ffe000 201292609Sadrian#define MIPS3_PGMASK_64M 0x07ffe000 202292609Sadrian#define MIPS3_PGMASK_256M 0x1fffe000 203292609Sadrian 204209243Sjchandra#endif /* !_MACHINE_PTE_H_ */ 205