1178172Simp/* $NetBSD: locore.h,v 1.78 2007/10/17 19:55:36 garbled Exp $ */ 2178172Simp 3178172Simp/* 4178172Simp * Copyright 1996 The Board of Trustees of The Leland Stanford 5178172Simp * Junior University. All Rights Reserved. 6178172Simp * 7178172Simp * Permission to use, copy, modify, and distribute this 8178172Simp * software and its documentation for any purpose and without 9178172Simp * fee is hereby granted, provided that the above copyright 10178172Simp * notice appear in all copies. Stanford University 11178172Simp * makes no representations about the suitability of this 12178172Simp * software for any purpose. It is provided "as is" without 13178172Simp * express or implied warranty. 14178172Simp * 15178172Simp * $FreeBSD$ 16178172Simp */ 17178172Simp 18178172Simp/* 19178172Simp * Jump table for MIPS cpu locore functions that are implemented 20178172Simp * differently on different generations, or instruction-level 21178172Simp * archtecture (ISA) level, the Mips family. 22178172Simp * 23178172Simp * We currently provide support for MIPS I and MIPS III. 24178172Simp */ 25178172Simp 26178172Simp#ifndef _MIPS_LOCORE_H 27211862Sjchandra#define _MIPS_LOCORE_H 28178172Simp 29178172Simp#include <machine/cpufunc.h> 30178172Simp#include <machine/cpuregs.h> 31178172Simp#include <machine/frame.h> 32178172Simp#include <machine/md_var.h> 33178172Simp 34178172Simp/* 35178172Simp * CPU identification, from PRID register. 36178172Simp */ 37178172Simp 38178172Simp#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff) 39178172Simp#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff) 40178172Simp 41178172Simp/* pre-MIPS32/64 */ 42178172Simp#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff) 43178172Simp#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f) 44178172Simp#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f) 45178172Simp 46178172Simp/* MIPS32/64 */ 47211862Sjchandra#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */ 48211862Sjchandra#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */ 49211862Sjchandra#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */ 50211862Sjchandra#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */ 51211862Sjchandra#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */ 52211862Sjchandra#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */ 53211862Sjchandra#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */ 54211862Sjchandra#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */ 55211862Sjchandra#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */ 56211862Sjchandra#define MIPS_PRID_CID_LSI 0x08 /* LSI */ 57178172Simp /* 0x09 unannounced */ 58178172Simp /* 0x0a unannounced */ 59211862Sjchandra#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */ 60211862Sjchandra#define MIPS_PRID_CID_RMI 0x0c /* RMI */ 61211862Sjchandra#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */ 62211862Sjchandra#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */ 63178172Simp 64178172Simp#endif /* _MIPS_LOCORE_H */ 65