cpuinfo.h revision 202031
1178172Simp/* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */ 2178172Simp 3178172Simp/*- 4178172Simp * Copyright (c) 1992, 1993 5178172Simp * The Regents of the University of California. All rights reserved. 6178172Simp * 7178172Simp * This code is derived from software contributed to Berkeley by 8178172Simp * Ralph Campbell and Rick Macklem. 9178172Simp * 10178172Simp * Redistribution and use in source and binary forms, with or without 11178172Simp * modification, are permitted provided that the following conditions 12178172Simp * are met: 13178172Simp * 1. Redistributions of source code must retain the above copyright 14178172Simp * notice, this list of conditions and the following disclaimer. 15178172Simp * 2. Redistributions in binary form must reproduce the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer in the 17178172Simp * documentation and/or other materials provided with the distribution. 18178172Simp * 3. All advertising materials mentioning features or use of this software 19178172Simp * must display the following acknowledgement: 20178172Simp * This product includes software developed by the University of 21178172Simp * California, Berkeley and its contributors. 22178172Simp * 4. Neither the name of the University nor the names of its contributors 23178172Simp * may be used to endorse or promote products derived from this software 24178172Simp * without specific prior written permission. 25178172Simp * 26178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36178172Simp * SUCH DAMAGE. 37178172Simp * 38178172Simp * $FreeBSD: head/sys/mips/include/cpuinfo.h 202031 2010-01-10 19:50:24Z imp $ 39178172Simp * @(#)cpu.h 8.4 (Berkeley) 1/4/94 40178172Simp */ 41178172Simp 42178172Simp#ifndef _CPUINFO_H_ 43178172Simp#define _CPUINFO_H_ 44178172Simp 45178172Simp/* 46178172Simp * Exported definitions unique to NetBSD/mips cpu support. 47178172Simp */ 48178172Simp 49178172Simp#ifdef _KERNEL 50178172Simp#ifndef LOCORE 51178172Simp 52178172Simpstruct mips_cpuinfo { 53178172Simp u_int8_t cpu_vendor; 54178172Simp u_int8_t cpu_rev; 55178172Simp u_int8_t cpu_impl; 56178172Simp u_int8_t tlb_type; 57178172Simp u_int16_t tlb_nentries; 58178172Simp u_int8_t icache_virtual; 59178172Simp struct { 60202031Simp u_int32_t ic_size; 61178172Simp u_int8_t ic_linesize; 62178172Simp u_int8_t ic_nways; 63178172Simp u_int16_t ic_nsets; 64202031Simp u_int32_t dc_size; 65178172Simp u_int8_t dc_linesize; 66178172Simp u_int8_t dc_nways; 67178172Simp u_int16_t dc_nsets; 68178172Simp } l1; 69178172Simp}; 70178172Simp 71178172Simp/* TODO: Merge above structure with NetBSD's below. */ 72178172Simp 73178172Simpstruct cpu_info { 74178172Simp#ifdef notyet 75178172Simp struct schedstate_percpu ci_schedstate; /* scheduler state */ 76178172Simp#endif 77178172Simp u_long ci_cpu_freq; /* CPU frequency */ 78178172Simp u_long ci_cycles_per_hz; /* CPU freq / hz */ 79178172Simp u_long ci_divisor_delay; /* for delay/DELAY */ 80178172Simp u_long ci_divisor_recip; /* scaled reciprocal of previous; 81178172Simp see below */ 82178172Simp#if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 83178172Simp u_long ci_spin_locks; /* # of spin locks held */ 84178172Simp u_long ci_simple_locks; /* # of simple locks held */ 85178172Simp#endif 86178172Simp}; 87178172Simp 88178172Simp/* 89178172Simp * To implement a more accurate microtime using the CP0 COUNT register 90178172Simp * we need to divide that register by the number of cycles per MHz. 91178172Simp * But... 92178172Simp * 93178172Simp * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 94178172Simp * and MULTU are only 12 clocks on the same CPU. 95178172Simp * 96178172Simp * The strategy we use is to calculate the reciprical of cycles per MHz, 97178172Simp * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 98178172Simp * HI register and have the results of the division. 99178172Simp */ 100178172Simp#define MIPS_SET_CI_RECIPRICAL(cpu) \ 101178172Simpdo { \ 102178172Simp KASSERT((cpu)->ci_divisor_delay != 0, ("divisor delay")); \ 103178172Simp (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 104178172Simp} while (0) 105178172Simp 106178172Simp#define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 107178172Simp __asm __volatile ("multu %1,%2 ; mfhi %0" \ 108178172Simp : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 109178172Simp 110178172Simp 111178172Simpextern struct cpu_info cpu_info_store; 112178172Simp 113178172Simp#if 0 114178172Simp#define curcpu() (&cpu_info_store) 115178172Simp#define cpu_number() (0) 116178172Simp#endif 117178172Simp 118178172Simp#endif /* !LOCORE */ 119178172Simp#endif /* _KERNEL */ 120178172Simp#endif /* _CPUINFO_H_ */ 121