cpufunc.h revision 210311
1/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27/* 28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 1. Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * 2. Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in the 37 * documentation and/or other materials provided with the distribution. 38 * 3. All advertising materials mentioning features or use of this software 39 * must display the following acknowledgement: 40 * This product includes software developed by Per Fogelstrom. 41 * 4. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta 56 * $FreeBSD: head/sys/mips/include/cpufunc.h 210311 2010-07-20 19:25:11Z jmallett $ 57 */ 58 59#ifndef _MACHINE_CPUFUNC_H_ 60#define _MACHINE_CPUFUNC_H_ 61 62#include <sys/types.h> 63#include <machine/cpuregs.h> 64 65/* 66 * These functions are required by user-land atomi ops 67 */ 68 69static __inline void 70mips_barrier(void) 71{ 72 __asm __volatile (".set noreorder\n\t" 73 "nop\n\t" 74 "nop\n\t" 75 "nop\n\t" 76 "nop\n\t" 77 "nop\n\t" 78 "nop\n\t" 79 "nop\n\t" 80 "nop\n\t" 81 ".set reorder\n\t" 82 : : : "memory"); 83} 84 85static __inline void 86mips_cp0_sync(void) 87{ 88 __asm __volatile (__XSTRING(COP0_SYNC)); 89} 90 91static __inline void 92mips_wbflush(void) 93{ 94 __asm __volatile ("sync" : : : "memory"); 95 mips_barrier(); 96} 97 98static __inline void 99mips_read_membar(void) 100{ 101 /* Nil */ 102} 103 104static __inline void 105mips_write_membar(void) 106{ 107 mips_wbflush(); 108} 109 110#ifdef _KERNEL 111#if defined(__mips_n32) || defined(__mips_n64) 112#define MIPS_RDRW64_COP0(n,r) \ 113static __inline uint64_t \ 114mips_rd_ ## n (void) \ 115{ \ 116 int v0; \ 117 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \ 118 : [v0] "=&r"(v0)); \ 119 mips_barrier(); \ 120 return (v0); \ 121} \ 122static __inline void \ 123mips_wr_ ## n (uint64_t a0) \ 124{ \ 125 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \ 126 __XSTRING(COP0_SYNC)";" \ 127 "nop;" \ 128 "nop;" \ 129 : \ 130 : [a0] "r"(a0)); \ 131 mips_barrier(); \ 132} struct __hack 133 134#if defined(__mips_n64) 135MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 136MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 137MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI); 138MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 139#endif 140MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); 141 142#undef MIPS_RDRW64_COP0 143#endif 144 145#define MIPS_RDRW32_COP0(n,r) \ 146static __inline uint32_t \ 147mips_rd_ ## n (void) \ 148{ \ 149 int v0; \ 150 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \ 151 : [v0] "=&r"(v0)); \ 152 mips_barrier(); \ 153 return (v0); \ 154} \ 155static __inline void \ 156mips_wr_ ## n (uint32_t a0) \ 157{ \ 158 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \ 159 __XSTRING(COP0_SYNC)";" \ 160 "nop;" \ 161 "nop;" \ 162 : \ 163 : [a0] "r"(a0)); \ 164 mips_barrier(); \ 165} struct __hack 166 167#define MIPS_RDRW32_COP0_SEL(n,r,s) \ 168static __inline uint32_t \ 169mips_rd_ ## n(void) \ 170{ \ 171 int v0; \ 172 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \ 173 : [v0] "=&r"(v0)); \ 174 mips_barrier(); \ 175 return (v0); \ 176} \ 177static __inline void \ 178mips_wr_ ## n(uint32_t a0) \ 179{ \ 180 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \ 181 __XSTRING(COP0_SYNC)";" \ 182 "nop;" \ 183 "nop;" \ 184 : \ 185 : [a0] "r"(a0)); \ 186 mips_barrier(); \ 187} struct __hack 188 189#ifdef CPU_CNMIPS 190static __inline void mips_sync_icache (void) 191{ 192 __asm __volatile ( 193 ".set push\n" 194 ".set mips64\n" 195 ".word 0x041f0000\n" /* xxx ICACHE */ 196 "nop\n" 197 ".set pop\n" 198 : : ); 199} 200#endif 201 202MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); 203MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); 204MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); 205MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); 206MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); 207MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); 208MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); 209MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); 210MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); 211MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); 212 213/* XXX: Some of these registers are specific to MIPS32. */ 214#if !defined(__mips_n64) 215MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); 216MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); 217MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); 218MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); 219#endif 220MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); 221/* XXX 64-bit? */ 222MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); 223MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); 224MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); 225MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); 226MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); 227MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); 228MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); 229MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); 230MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); 231 232MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); 233MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); 234MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); 235MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); 236 237#undef MIPS_RDRW32_COP0 238 239static __inline register_t 240intr_disable(void) 241{ 242 register_t s; 243 244 s = mips_rd_status(); 245 mips_wr_status(s & ~MIPS_SR_INT_IE); 246 247 return (s & MIPS_SR_INT_IE); 248} 249 250static __inline register_t 251intr_enable(void) 252{ 253 register_t s; 254 255 s = mips_rd_status(); 256 mips_wr_status(s | MIPS_SR_INT_IE); 257 258 return (s); 259} 260 261static __inline void 262intr_restore(register_t ie) 263{ 264 if (ie == MIPS_SR_INT_IE) { 265 intr_enable(); 266 } 267} 268 269static __inline void 270breakpoint(void) 271{ 272 __asm __volatile ("break"); 273} 274 275#if defined(__GNUC__) && !defined(__mips_o32) 276static inline uint64_t 277mips3_ld(const volatile uint64_t *va) 278{ 279 uint64_t rv; 280 281#if defined(_LP64) 282 rv = *va; 283#else 284 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va)); 285#endif 286 287 return (rv); 288} 289 290static inline void 291mips3_sd(volatile uint64_t *va, uint64_t v) 292{ 293#if defined(_LP64) 294 *va = v; 295#else 296 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va)); 297#endif 298} 299#else 300uint64_t mips3_ld(volatile uint64_t *va); 301void mips3_sd(volatile uint64_t *, uint64_t); 302#endif /* __GNUC__ */ 303 304#endif /* _KERNEL */ 305 306#define readb(va) (*(volatile uint8_t *) (va)) 307#define readw(va) (*(volatile uint16_t *) (va)) 308#define readl(va) (*(volatile uint32_t *) (va)) 309 310#define writeb(va, d) (*(volatile uint8_t *) (va) = (d)) 311#define writew(va, d) (*(volatile uint16_t *) (va) = (d)) 312#define writel(va, d) (*(volatile uint32_t *) (va) = (d)) 313 314/* 315 * I/O macros. 316 */ 317 318#define outb(a,v) (*(volatile unsigned char*)(a) = (v)) 319#define out8(a,v) (*(volatile unsigned char*)(a) = (v)) 320#define outw(a,v) (*(volatile unsigned short*)(a) = (v)) 321#define out16(a,v) outw(a,v) 322#define outl(a,v) (*(volatile unsigned int*)(a) = (v)) 323#define out32(a,v) outl(a,v) 324#define inb(a) (*(volatile unsigned char*)(a)) 325#define in8(a) (*(volatile unsigned char*)(a)) 326#define inw(a) (*(volatile unsigned short*)(a)) 327#define in16(a) inw(a) 328#define inl(a) (*(volatile unsigned int*)(a)) 329#define in32(a) inl(a) 330 331#define out8rb(a,v) (*(volatile unsigned char*)(a) = (v)) 332#define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v)) 333#define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v)) 334#define in8rb(a) (*(volatile unsigned char*)(a)) 335#define in16rb(a) (__in16rb((volatile uint16_t *)(a))) 336#define in32rb(a) (__in32rb((volatile uint32_t *)(a))) 337 338#define _swap_(x) (((x) >> 24) | ((x) << 24) | \ 339 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8)) 340 341static __inline void __out32rb(volatile uint32_t *, uint32_t); 342static __inline void __out16rb(volatile uint16_t *, uint16_t); 343static __inline uint32_t __in32rb(volatile uint32_t *); 344static __inline uint16_t __in16rb(volatile uint16_t *); 345 346static __inline void 347__out32rb(volatile uint32_t *a, uint32_t v) 348{ 349 uint32_t _v_ = v; 350 351 _v_ = _swap_(_v_); 352 out32(a, _v_); 353} 354 355static __inline void 356__out16rb(volatile uint16_t *a, uint16_t v) 357{ 358 uint16_t _v_; 359 360 _v_ = ((v >> 8) & 0xff) | (v << 8); 361 out16(a, _v_); 362} 363 364static __inline uint32_t 365__in32rb(volatile uint32_t *a) 366{ 367 uint32_t _v_; 368 369 _v_ = in32(a); 370 _v_ = _swap_(_v_); 371 return _v_; 372} 373 374static __inline uint16_t 375__in16rb(volatile uint16_t *a) 376{ 377 uint16_t _v_; 378 379 _v_ = in16(a); 380 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8); 381 return _v_; 382} 383 384void insb(uint8_t *, uint8_t *,int); 385void insw(uint16_t *, uint16_t *,int); 386void insl(uint32_t *, uint32_t *,int); 387void outsb(uint8_t *, const uint8_t *,int); 388void outsw(uint16_t *, const uint16_t *,int); 389void outsl(uint32_t *, const uint32_t *,int); 390u_int loadandclear(volatile u_int *addr); 391 392#endif /* !_MACHINE_CPUFUNC_H_ */ 393