cpu.h revision 203697
1/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish 44 * $FreeBSD: head/sys/mips/include/cpu.h 203697 2010-02-09 06:24:43Z neel $ 45 */ 46 47#ifndef _MACHINE_CPU_H_ 48#define _MACHINE_CPU_H_ 49 50#include <machine/psl.h> 51#include <machine/endian.h> 52 53#define MIPS_CACHED_MEMORY_ADDR 0x80000000 54#define MIPS_UNCACHED_MEMORY_ADDR 0xa0000000 55#define MIPS_MAX_MEM_ADDR 0xbe000000 56#define MIPS_RESERVED_ADDR 0xbfc80000 57 58#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 59#define MIPS_CACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 60#define MIPS_PHYS_TO_CACHED(x) ((uintptr_t)(x) | MIPS_CACHED_MEMORY_ADDR) 61#define MIPS_UNCACHED_TO_PHYS(x) ((uintptr_t)(x) & 0x1fffffff) 62#define MIPS_PHYS_TO_UNCACHED(x) ((uintptr_t)(x) | MIPS_UNCACHED_MEMORY_ADDR) 63 64#define MIPS_PHYS_MASK (0x1fffffff) 65#define MIPS_PA_2_K1VA(x) (MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK)) 66 67#define MIPS_VA_TO_CINDEX(x) ((uintptr_t)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR) 68#define MIPS_CACHED_TO_UNCACHED(x) (MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x))) 69 70#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 71#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 72#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 73#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 74 75#define MIPS_IS_KSEG0_ADDR(x) \ 76 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 77 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 78#define MIPS_IS_KSEG1_ADDR(x) \ 79 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 80 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 81#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 82 MIPS_IS_KSEG1_ADDR(x)) 83 84/* 85 * Status register. 86 */ 87#define SR_COP_USABILITY 0xf0000000 88#define SR_COP_0_BIT 0x10000000 89#define SR_COP_1_BIT 0x20000000 90#define SR_COP_2_BIT 0x40000000 91#define SR_RP 0x08000000 92#define SR_FR_32 0x04000000 93#define SR_RE 0x02000000 94#define SR_PX 0x00800000 95#define SR_BOOT_EXC_VEC 0x00400000 96#define SR_TLB_SHUTDOWN 0x00200000 97#define SR_SOFT_RESET 0x00100000 98#define SR_DIAG_CH 0x00040000 99#define SR_DIAG_CE 0x00020000 100#define SR_DIAG_DE 0x00010000 101#define SR_KX 0x00000080 102#define SR_SX 0x00000040 103#define SR_UX 0x00000020 104#define SR_KSU_MASK 0x00000018 105#define SR_KSU_USER 0x00000010 106#define SR_KSU_SUPER 0x00000008 107#define SR_KSU_KERNEL 0x00000000 108#define SR_ERL 0x00000004 109#define SR_EXL 0x00000002 110#define SR_INT_ENAB 0x00000001 111 112#define SR_INT_MASK 0x0000ff00 113#define SOFT_INT_MASK_0 0x00000100 114#define SOFT_INT_MASK_1 0x00000200 115#define SR_INT_MASK_0 0x00000400 116#define SR_INT_MASK_1 0x00000800 117#define SR_INT_MASK_2 0x00001000 118#define SR_INT_MASK_3 0x00002000 119#define SR_INT_MASK_4 0x00004000 120#define SR_INT_MASK_5 0x00008000 121#define ALL_INT_MASK SR_INT_MASK 122#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 123#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 124 125#define soft_int_mask(softintr) (1 << ((softintr) + 8)) 126#define hard_int_mask(hardintr) (1 << ((hardintr) + 10)) 127 128/* 129 * The bits in the cause register. 130 * 131 * CR_BR_DELAY Exception happened in branch delay slot. 132 * CR_COP_ERR Coprocessor error. 133 * CR_IP Interrupt pending bits defined below. 134 * CR_EXC_CODE The exception type (see exception codes below). 135 */ 136#define CR_BR_DELAY 0x80000000 137#define CR_COP_ERR 0x30000000 138#define CR_EXC_CODE 0x0000007c 139#define CR_EXC_CODE_SHIFT 2 140#define CR_IPEND 0x0000ff00 141 142/* 143 * Cause Register Format: 144 * 145 * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0 146 * ---------------------------------------------------------------------- 147 * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0| 148 * |______________________________________________________________________ 149 */ 150 151#define CR_INT_SOFT0 0x00000100 152#define CR_INT_SOFT1 0x00000200 153#define CR_INT_0 0x00000400 154#define CR_INT_1 0x00000800 155#define CR_INT_2 0x00001000 156#define CR_INT_3 0x00002000 157#define CR_INT_4 0x00004000 158#define CR_INT_5 0x00008000 159 160#define CR_INT_UART CR_INT_1 161#define CR_INT_IPI CR_INT_2 162#define CR_INT_CLOCK CR_INT_5 163 164/* 165 * The bits in the CONFIG register 166 */ 167#define CFG_K0_UNCACHED 2 168#define CFG_K0_CACHED 3 169#define CFG_K0_MASK 0x7 170 171/* 172 * The bits in the context register. 173 */ 174#define CNTXT_PTE_BASE 0xff800000 175#define CNTXT_BAD_VPN2 0x007ffff0 176 177/* 178 * Location of exception vectors. 179 */ 180#define RESET_EXC_VEC 0xbfc00000 181#define TLB_MISS_EXC_VEC 0x80000000 182#define XTLB_MISS_EXC_VEC 0x80000080 183#define CACHE_ERR_EXC_VEC 0x80000100 184#define GEN_EXC_VEC 0x80000180 185 186/* 187 * Coprocessor 0 registers: 188 */ 189#define COP_0_TLB_INDEX $0 190#define COP_0_TLB_RANDOM $1 191#define COP_0_TLB_LO0 $2 192#define COP_0_TLB_LO1 $3 193#define COP_0_TLB_CONTEXT $4 194#define COP_0_TLB_PG_MASK $5 195#define COP_0_TLB_WIRED $6 196#define COP_0_INFO $7 197#define COP_0_BAD_VADDR $8 198#define COP_0_COUNT $9 199#define COP_0_TLB_HI $10 200#define COP_0_COMPARE $11 201#define COP_0_STATUS_REG $12 202#define COP_0_CAUSE_REG $13 203#define COP_0_EXC_PC $14 204#define COP_0_PRID $15 205#define COP_0_CONFIG $16 206#define COP_0_LLADDR $17 207#define COP_0_WATCH_LO $18 208#define COP_0_WATCH_HI $19 209#define COP_0_TLB_XCONTEXT $20 210#define COP_0_ECC $26 211#define COP_0_CACHE_ERR $27 212#define COP_0_TAG_LO $28 213#define COP_0_TAG_HI $29 214#define COP_0_ERROR_PC $30 215 216/* 217 * Coprocessor 0 Set 1 218 */ 219#define C0P_1_IPLLO $18 220#define C0P_1_IPLHI $19 221#define C0P_1_INTCTL $20 222#define C0P_1_DERRADDR0 $26 223#define C0P_1_DERRADDR1 $27 224 225/* 226 * Values for the code field in a break instruction. 227 */ 228#define BREAK_INSTR 0x0000000d 229#define BREAK_VAL_MASK 0x03ffffc0 230#define BREAK_VAL_SHIFT 16 231#define BREAK_KDB_VAL 512 232#define BREAK_SSTEP_VAL 513 233#define BREAK_BRKPT_VAL 514 234#define BREAK_SOVER_VAL 515 235#define BREAK_DDB_VAL 516 236#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 237#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 238#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 239#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 240#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 241 242/* 243 * Mininum and maximum cache sizes. 244 */ 245#define MIN_CACHE_SIZE (16 * 1024) 246#define MAX_CACHE_SIZE (256 * 1024) 247 248/* 249 * The floating point version and status registers. 250 */ 251#define FPC_ID $0 252#define FPC_CSR $31 253 254/* 255 * The floating point coprocessor status register bits. 256 */ 257#define FPC_ROUNDING_BITS 0x00000003 258#define FPC_ROUND_RN 0x00000000 259#define FPC_ROUND_RZ 0x00000001 260#define FPC_ROUND_RP 0x00000002 261#define FPC_ROUND_RM 0x00000003 262#define FPC_STICKY_BITS 0x0000007c 263#define FPC_STICKY_INEXACT 0x00000004 264#define FPC_STICKY_UNDERFLOW 0x00000008 265#define FPC_STICKY_OVERFLOW 0x00000010 266#define FPC_STICKY_DIV0 0x00000020 267#define FPC_STICKY_INVALID 0x00000040 268#define FPC_ENABLE_BITS 0x00000f80 269#define FPC_ENABLE_INEXACT 0x00000080 270#define FPC_ENABLE_UNDERFLOW 0x00000100 271#define FPC_ENABLE_OVERFLOW 0x00000200 272#define FPC_ENABLE_DIV0 0x00000400 273#define FPC_ENABLE_INVALID 0x00000800 274#define FPC_EXCEPTION_BITS 0x0003f000 275#define FPC_EXCEPTION_INEXACT 0x00001000 276#define FPC_EXCEPTION_UNDERFLOW 0x00002000 277#define FPC_EXCEPTION_OVERFLOW 0x00004000 278#define FPC_EXCEPTION_DIV0 0x00008000 279#define FPC_EXCEPTION_INVALID 0x00010000 280#define FPC_EXCEPTION_UNIMPL 0x00020000 281#define FPC_COND_BIT 0x00800000 282#define FPC_FLUSH_BIT 0x01000000 283#define FPC_MBZ_BITS 0xfe7c0000 284 285/* 286 * Constants to determine if have a floating point instruction. 287 */ 288#define OPCODE_SHIFT 26 289#define OPCODE_C1 0x11 290 291/* 292 * The low part of the TLB entry. 293 */ 294#define VMTLB_PF_NUM 0x3fffffc0 295#define VMTLB_ATTR_MASK 0x00000038 296#define VMTLB_MOD_BIT 0x00000004 297#define VMTLB_VALID_BIT 0x00000002 298#define VMTLB_GLOBAL_BIT 0x00000001 299 300#define VMTLB_PHYS_PAGE_SHIFT 6 301 302/* 303 * The high part of the TLB entry. 304 */ 305#define VMTLB_VIRT_PAGE_NUM 0xffffe000 306#define VMTLB_PID 0x000000ff 307#define VMTLB_PID_R9K 0x00000fff 308#define VMTLB_PID_SHIFT 0 309#define VMTLB_VIRT_PAGE_SHIFT 12 310#define VMTLB_VIRT_PAGE_SHIFT_R9K 13 311 312/* 313 * The first TLB entry that write random hits. 314 * TLB entry 0 maps the kernel stack of the currently running thread 315 * TLB entry 1 maps the pcpu area of processor (only for SMP builds) 316 */ 317#define KSTACK_TLB_ENTRY 0 318#ifdef SMP 319#define PCPU_TLB_ENTRY 1 320#define VMWIRED_ENTRIES 2 321#else 322#define VMWIRED_ENTRIES 1 323#endif /* SMP */ 324 325/* 326 * The number of process id entries. 327 */ 328#define VMNUM_PIDS 256 329 330/* 331 * TLB probe return codes. 332 */ 333#define VMTLB_NOT_FOUND 0 334#define VMTLB_FOUND 1 335#define VMTLB_FOUND_WITH_PATCH 2 336#define VMTLB_PROBE_ERROR 3 337 338/* 339 * Exported definitions unique to mips cpu support. 340 */ 341 342/* 343 * definitions of cpu-dependent requirements 344 * referenced in generic code 345 */ 346#define COPY_SIGCODE /* copy sigcode above user stack in exec */ 347 348#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 349 350#ifndef _LOCORE 351#include <machine/frame.h> 352/* 353 * Arguments to hardclock and gatherstats encapsulate the previous 354 * machine state in an opaque clockframe. 355 */ 356#define clockframe trapframe /* Use normal trap frame */ 357 358#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 359#define CLKF_BASEPRI(framep) ((framep)->cpl == 0) 360#define CLKF_PC(framep) ((framep)->pc) 361#define CLKF_INTR(framep) (0) 362#define MIPS_CLKF_INTR() (intr_nesting_level >= 1) 363#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0) 364#define TRAPF_PC(framep) ((framep)->pc) 365#define cpu_getstack(td) ((td)->td_frame->sp) 366 367/* 368 * CPU identification, from PRID register. 369 */ 370union cpuprid { 371 int cpuprid; 372 struct { 373#if BYTE_ORDER == BIG_ENDIAN 374 u_int pad1:8; /* reserved */ 375 u_int cp_vendor:8; /* company identifier */ 376 u_int cp_imp:8; /* implementation identifier */ 377 u_int cp_majrev:4; /* major revision identifier */ 378 u_int cp_minrev:4; /* minor revision identifier */ 379#else 380 u_int cp_minrev:4; /* minor revision identifier */ 381 u_int cp_majrev:4; /* major revision identifier */ 382 u_int cp_imp:8; /* implementation identifier */ 383 u_int cp_vendor:8; /* company identifier */ 384 u_int pad1:8; /* reserved */ 385#endif 386 } cpu; 387}; 388 389#endif /* !_LOCORE */ 390 391/* 392 * CTL_MACHDEP definitions. 393 */ 394#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 395#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */ 396#define CPU_DISRTCSET 3 /* int: disable resettodr() call */ 397#define CPU_BOOTINFO 4 /* struct: bootinfo */ 398#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */ 399#define CPU_MAXID 6 /* number of valid machdep ids */ 400 401#define CTL_MACHDEP_NAMES { \ 402 { 0, 0 }, \ 403 { "console_device", CTLTYPE_STRUCT }, \ 404 { "adjkerntz", CTLTYPE_INT }, \ 405 { "disable_rtc_set", CTLTYPE_INT }, \ 406 { "bootinfo", CTLTYPE_STRUCT }, \ 407 { "wall_cmos_clock", CTLTYPE_INT }, \ 408} 409 410/* 411 * MIPS CPU types (cp_imp). 412 */ 413#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 414#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 415#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 416#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 417#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 418#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 419#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 420#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 421#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 422#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 423#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 424#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 425#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 426#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 427#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 428#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 429#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ 430#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ 431#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 432#define MIPS_RM9000 0x34 /* E9000 CPU */ 433 434/* 435 * MIPS FPU types 436 */ 437#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 438#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 439#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 440#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 441#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 442#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 443#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 444#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 445#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 446#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 447#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 448#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 449#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 450#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 451#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 452#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ 453#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ 454#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ 455#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 456 457#ifndef _LOCORE 458extern union cpuprid cpu_id; 459 460#define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) 461#define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ 462 cpu_id.cpu.cp_imp = ((type) & 0x00ff)) 463#endif /* !_LOCORE */ 464 465#if defined(_KERNEL) && !defined(_LOCORE) 466extern union cpuprid fpu_id; 467 468struct tlb; 469struct user; 470 471u_int32_t mips_cp0_config1_read(void); 472int Mips_ConfigCache(void); 473void Mips_SetWIRED(int); 474void Mips_SetPID(int); 475u_int Mips_GetCOUNT(void); 476void Mips_SetCOMPARE(u_int); 477u_int Mips_GetCOMPARE(void); 478 479void Mips_SyncCache(void); 480void Mips_SyncDCache(vm_offset_t, int); 481void Mips_HitSyncDCache(vm_offset_t, int); 482void Mips_HitSyncSCache(vm_offset_t, int); 483void Mips_IOSyncDCache(vm_offset_t, int, int); 484void Mips_HitInvalidateDCache(vm_offset_t, int); 485void Mips_SyncICache(vm_offset_t, int); 486void Mips_InvalidateICache(vm_offset_t, int); 487 488void Mips_TLBFlush(int); 489void Mips_TLBFlushAddr(vm_offset_t); 490void Mips_TLBWriteIndexed(int, struct tlb *); 491void Mips_TLBUpdate(vm_offset_t, unsigned); 492void Mips_TLBRead(int, struct tlb *); 493void mips_TBIAP(int); 494void wbflush(void); 495 496extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 497extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 498extern int num_tlbentries; 499extern char btext[]; 500extern char etext[]; 501extern int intr_nesting_level; 502 503#define func_0args_asmmacro(func, in) \ 504 __asm __volatile ( "jalr %0" \ 505 : "=r" (in) /* outputs */ \ 506 : "r" (func) /* inputs */ \ 507 : "$31", "$4"); 508 509#define func_1args_asmmacro(func, arg0) \ 510 __asm __volatile ("move $4, %1;" \ 511 "jalr %0" \ 512 : /* outputs */ \ 513 : "r" (func), "r" (arg0) /* inputs */ \ 514 : "$31", "$4"); 515 516#define func_2args_asmmacro(func, arg0, arg1) \ 517 __asm __volatile ("move $4, %1;" \ 518 "move $5, %2;" \ 519 "jalr %0" \ 520 : /* outputs */ \ 521 : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \ 522 : "$31", "$4", "$5"); 523 524#define func_3args_asmmacro(func, arg0, arg1, arg2) \ 525 __asm __volatile ( "move $4, %1;" \ 526 "move $5, %2;" \ 527 "move $6, %3;" \ 528 "jalr %0" \ 529 : /* outputs */ \ 530 : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \ 531 : "$31", "$4", "$5", "$6"); 532 533#define MachSetPID Mips_SetPID 534#define MachTLBUpdate Mips_TLBUpdate 535#define mips_TBIS Mips_TLBFlushAddr 536#define MIPS_TBIAP() mips_TBIAP(num_tlbentries) 537#define MachSetWIRED(index) Mips_SetWIRED(index) 538#define MachTLBFlush(count) Mips_TLBFlush(count) 539#define MachTLBGetPID(pid) (pid = Mips_TLBGetPID()) 540#define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp) 541#define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc) 542 543/* 544 * Enable realtime clock (always enabled). 545 */ 546#define enablertclock() 547 548/* 549 * Are we in an interrupt handler? required by JunOS 550 */ 551#define IN_INT_HANDLER() \ 552 (curthread->td_intr_nesting_level != 0 || \ 553 (curthread->td_pflags & TDP_ITHREAD)) 554 555/* 556 * Low level access routines to CPU registers 557 */ 558 559void setsoftintr0(void); 560void clearsoftintr0(void); 561void setsoftintr1(void); 562void clearsoftintr1(void); 563 564 565u_int32_t mips_cp0_status_read(void); 566void mips_cp0_status_write(u_int32_t); 567 568int disableintr(void); 569void restoreintr(int); 570int enableintr(void); 571int Mips_TLBGetPID(void); 572 573void swi_vm(void *); 574void cpu_halt(void); 575void cpu_reset(void); 576 577u_int32_t set_intr_mask(u_int32_t); 578u_int32_t get_intr_mask(void); 579u_int32_t get_cyclecount(void); 580 581#define cpu_spinwait() /* nothing */ 582 583#endif /* _KERNEL */ 584#endif /* !_MACHINE_CPU_H_ */ 585