octeon_mp.c revision 226018 
1/*-
2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/cavium/octeon_mp.c 226018 2011-10-04 17:49:19Z marcel $
27 */
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_mp.c 226018 2011-10-04 17:49:19Z marcel $");
30
31#include <sys/param.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/smp.h>
35#include <sys/systm.h>
36
37#include <machine/hwfunc.h>
38#include <machine/md_var.h>
39#include <machine/smp.h>
40
41#include <mips/cavium/octeon_pcmap_regs.h>
42
43#include <contrib/octeon-sdk/cvmx.h>
44#include <contrib/octeon-sdk/cvmx-interrupt.h>
45
46/* XXX */
47extern cvmx_bootinfo_t *octeon_bootinfo;
48
49unsigned octeon_ap_boot = ~0;
50
51void
52platform_ipi_send(int cpuid)
53{
54	cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
55	mips_wbflush();
56}
57
58void
59platform_ipi_clear(void)
60{
61	uint64_t action;
62
63	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
64	KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
65	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
66}
67
68int
69platform_ipi_intrnum(void)
70{
71	return (1);
72}
73
74void
75platform_init_ap(int cpuid)
76{
77	unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
78
79	/*
80	 * Set the exception base.
81	 */
82	mips_wr_ebase(0x80000000);
83
84	/*
85	 * Clear any pending IPIs.
86	 */
87	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
88
89	/*
90	 * Set up interrupts.
91	 */
92	octeon_ciu_reset();
93
94	/*
95	 * Unmask the clock, ipi and ciu interrupts.
96	 */
97	ciu_int_mask = hard_int_mask(0);
98	clock_int_mask = hard_int_mask(5);
99	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
100	set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
101
102	mips_wbflush();
103}
104
105void
106platform_cpu_mask(cpuset_t *mask)
107{
108	uint64_t core_mask = octeon_bootinfo->core_mask;
109	uint64_t i, m;
110
111	CPU_ZERO(mask);
112	for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
113		if (core_mask & m)
114			CPU_SET(i, mask);
115}
116
117struct cpu_group *
118platform_smp_topo(void)
119{
120	return (smp_topo_none());
121}
122
123int
124platform_start_ap(int cpuid)
125{
126	uint64_t cores_in_reset;
127
128	/*
129	 * Release the core if it is in reset, and let it rev up a bit.
130	 * The real synchronization happens below via octeon_ap_boot.
131	 */
132	cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
133	if (cores_in_reset & (1ULL << cpuid)) {
134	    if (bootverbose)
135		printf ("AP #%d still in reset\n", cpuid);
136	    cores_in_reset &= ~(1ULL << cpuid);
137	    cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
138	    DELAY(2000);    /* Give it a moment to start */
139	}
140
141	if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
142		return (-1);
143	for (;;) {
144		DELAY(1000);
145		if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
146			return (0);
147		printf("Waiting for cpu%d to start\n", cpuid);
148	}
149}
150