1206721Sjmallett/*- 2206721Sjmallett * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3206721Sjmallett * All rights reserved. 4206721Sjmallett * 5206721Sjmallett * Redistribution and use in source and binary forms, with or without 6206721Sjmallett * modification, are permitted provided that the following conditions 7206721Sjmallett * are met: 8206721Sjmallett * 1. Redistributions of source code must retain the above copyright 9206721Sjmallett * notice, this list of conditions and the following disclaimer. 10206721Sjmallett * 2. Redistributions in binary form must reproduce the above copyright 11206721Sjmallett * notice, this list of conditions and the following disclaimer in the 12206721Sjmallett * documentation and/or other materials provided with the distribution. 13206721Sjmallett * 14206721Sjmallett * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15206721Sjmallett * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16206721Sjmallett * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17206721Sjmallett * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18206721Sjmallett * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19206721Sjmallett * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20206721Sjmallett * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21206721Sjmallett * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22206721Sjmallett * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23206721Sjmallett * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24206721Sjmallett * SUCH DAMAGE. 25206721Sjmallett * 26206721Sjmallett * $FreeBSD$ 27206721Sjmallett */ 28206721Sjmallett#include <sys/cdefs.h> 29206721Sjmallett__FBSDID("$FreeBSD$"); 30206721Sjmallett 31206721Sjmallett#include <sys/param.h> 32206721Sjmallett#include <sys/conf.h> 33206721Sjmallett#include <sys/kernel.h> 34210311Sjmallett#include <sys/smp.h> 35206721Sjmallett#include <sys/systm.h> 36206721Sjmallett 37206721Sjmallett#include <machine/hwfunc.h> 38210311Sjmallett#include <machine/md_var.h> 39206721Sjmallett#include <machine/smp.h> 40206721Sjmallett 41206721Sjmallett#include <mips/cavium/octeon_pcmap_regs.h> 42206721Sjmallett 43210311Sjmallett#include <contrib/octeon-sdk/cvmx.h> 44232812Sjmallett#include <mips/cavium/octeon_irq.h> 45210311Sjmallett 46226018Smarcelunsigned octeon_ap_boot = ~0; 47206721Sjmallett 48206721Sjmallettvoid 49206721Sjmallettplatform_ipi_send(int cpuid) 50206721Sjmallett{ 51210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1); 52206721Sjmallett mips_wbflush(); 53206721Sjmallett} 54206721Sjmallett 55206721Sjmallettvoid 56206721Sjmallettplatform_ipi_clear(void) 57206721Sjmallett{ 58206721Sjmallett uint64_t action; 59206721Sjmallett 60210311Sjmallett action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid))); 61206721Sjmallett KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action)); 62210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action); 63206721Sjmallett} 64206721Sjmallett 65206721Sjmallettint 66206721Sjmallettplatform_ipi_intrnum(void) 67206721Sjmallett{ 68206721Sjmallett return (1); 69206721Sjmallett} 70206721Sjmallett 71206721Sjmallettvoid 72206721Sjmallettplatform_init_ap(int cpuid) 73206721Sjmallett{ 74216946Sjmallett unsigned ciu_int_mask, clock_int_mask, ipi_int_mask; 75210311Sjmallett 76206721Sjmallett /* 77206721Sjmallett * Set the exception base. 78206721Sjmallett */ 79216946Sjmallett mips_wr_ebase(0x80000000); 80206721Sjmallett 81206721Sjmallett /* 82210311Sjmallett * Clear any pending IPIs. 83206721Sjmallett */ 84210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff); 85210311Sjmallett 86210311Sjmallett /* 87210311Sjmallett * Set up interrupts. 88210311Sjmallett */ 89206721Sjmallett octeon_ciu_reset(); 90206721Sjmallett 91210311Sjmallett /* 92216946Sjmallett * Unmask the clock, ipi and ciu interrupts. 93210311Sjmallett */ 94216946Sjmallett ciu_int_mask = hard_int_mask(0); 95210311Sjmallett clock_int_mask = hard_int_mask(5); 96210311Sjmallett ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); 97216946Sjmallett set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask); 98206721Sjmallett 99206721Sjmallett mips_wbflush(); 100206721Sjmallett} 101206721Sjmallett 102222813Sattiliovoid 103222813Sattilioplatform_cpu_mask(cpuset_t *mask) 104206721Sjmallett{ 105226024Smarcel uint64_t core_mask = cvmx_sysinfo_get()->core_mask; 106224661Smarcel uint64_t i, m; 107222813Sattilio 108222813Sattilio CPU_ZERO(mask); 109224661Smarcel for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1) 110224661Smarcel if (core_mask & m) 111224661Smarcel CPU_SET(i, mask); 112206721Sjmallett} 113206721Sjmallett 114210311Sjmallettstruct cpu_group * 115210311Sjmallettplatform_smp_topo(void) 116210311Sjmallett{ 117210311Sjmallett return (smp_topo_none()); 118210311Sjmallett} 119210311Sjmallett 120206721Sjmallettint 121206721Sjmallettplatform_start_ap(int cpuid) 122206721Sjmallett{ 123224661Smarcel uint64_t cores_in_reset; 124224661Smarcel 125224661Smarcel /* 126224661Smarcel * Release the core if it is in reset, and let it rev up a bit. 127224661Smarcel * The real synchronization happens below via octeon_ap_boot. 128224661Smarcel */ 129224661Smarcel cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST); 130224661Smarcel if (cores_in_reset & (1ULL << cpuid)) { 131224661Smarcel if (bootverbose) 132224661Smarcel printf ("AP #%d still in reset\n", cpuid); 133224661Smarcel cores_in_reset &= ~(1ULL << cpuid); 134224661Smarcel cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset)); 135224661Smarcel DELAY(2000); /* Give it a moment to start */ 136224661Smarcel } 137224661Smarcel 138226018Smarcel if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0) 139206721Sjmallett return (-1); 140206721Sjmallett for (;;) { 141206721Sjmallett DELAY(1000); 142226018Smarcel if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0) 143206721Sjmallett return (0); 144206721Sjmallett printf("Waiting for cpu%d to start\n", cpuid); 145206721Sjmallett } 146206721Sjmallett} 147