octeon_machdep.c revision 243469
1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 243469 2012-11-24 02:00:29Z jmallett $ 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 243469 2012-11-24 02:00:29Z jmallett $"); 30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/cons.h> 41#include <sys/exec.h> 42#include <sys/ucontext.h> 43#include <sys/proc.h> 44#include <sys/kdb.h> 45#include <sys/ptrace.h> 46#include <sys/reboot.h> 47#include <sys/signalvar.h> 48#include <sys/sysctl.h> 49#include <sys/sysent.h> 50#include <sys/sysproto.h> 51#include <sys/time.h> 52#include <sys/timetc.h> 53#include <sys/user.h> 54 55#include <vm/vm.h> 56#include <vm/vm_object.h> 57#include <vm/vm_page.h> 58#include <vm/vm_pager.h> 59 60#include <machine/atomic.h> 61#include <machine/cache.h> 62#include <machine/clock.h> 63#include <machine/cpu.h> 64#include <machine/cpuregs.h> 65#include <machine/cpufunc.h> 66#include <mips/cavium/octeon_pcmap_regs.h> 67#include <machine/hwfunc.h> 68#include <machine/intr_machdep.h> 69#include <machine/locore.h> 70#include <machine/md_var.h> 71#include <machine/pcpu.h> 72#include <machine/pte.h> 73#include <machine/trap.h> 74#include <machine/vmparam.h> 75 76#include <contrib/octeon-sdk/cvmx.h> 77#include <contrib/octeon-sdk/cvmx-bootmem.h> 78#include <contrib/octeon-sdk/cvmx-ebt3000.h> 79#include <contrib/octeon-sdk/cvmx-helper-cfg.h> 80#include <contrib/octeon-sdk/cvmx-interrupt.h> 81#include <contrib/octeon-sdk/cvmx-version.h> 82 83#include <mips/cavium/octeon_irq.h> 84 85#if defined(__mips_n64) 86#define MAX_APP_DESC_ADDR 0xffffffffafffffff 87#else 88#define MAX_APP_DESC_ADDR 0xafffffff 89#endif 90 91struct octeon_feature_description { 92 octeon_feature_t ofd_feature; 93 const char *ofd_string; 94}; 95 96extern int *end; 97extern char cpu_model[]; 98extern char cpu_board[]; 99 100static const struct octeon_feature_description octeon_feature_descriptions[] = { 101 { OCTEON_FEATURE_SAAD, "SAAD" }, 102 { OCTEON_FEATURE_ZIP, "ZIP" }, 103 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 104 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 105 { OCTEON_FEATURE_PCIE, "PCIE" }, 106 { OCTEON_FEATURE_SRIO, "SRIO" }, 107 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 108 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 109 { OCTEON_FEATURE_TRA, "TRA" }, 110 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 111 { OCTEON_FEATURE_RAID, "RAID" }, 112 { OCTEON_FEATURE_USB, "USB" }, 113 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 114 { OCTEON_FEATURE_DFA, "DFA" }, 115 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 116 { OCTEON_FEATURE_NPEI, "NPEI" }, 117 { OCTEON_FEATURE_ILK, "ILK" }, 118 { OCTEON_FEATURE_HFA, "HFA" }, 119 { OCTEON_FEATURE_DFM, "DFM" }, 120 { OCTEON_FEATURE_CIU2, "CIU2" }, 121 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 122 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 123 { OCTEON_FEATURE_NAND, "NAND" }, 124 { OCTEON_FEATURE_MMC, "MMC" }, 125 { OCTEON_FEATURE_PKND, "PKND" }, 126 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 127 { 0, NULL } 128}; 129 130static uint64_t octeon_get_ticks(void); 131static unsigned octeon_get_timecount(struct timecounter *tc); 132 133static void octeon_boot_params_init(register_t ptr); 134 135static struct timecounter octeon_timecounter = { 136 octeon_get_timecount, /* get_timecount */ 137 0, /* no poll_pps */ 138 0xffffffffu, /* octeon_mask */ 139 0, /* frequency */ 140 "Octeon", /* name */ 141 900, /* quality (adjusted in code) */ 142}; 143 144void 145platform_cpu_init() 146{ 147 /* Nothing special yet */ 148} 149 150/* 151 * Perform a board-level soft-reset. 152 */ 153void 154platform_reset(void) 155{ 156 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 157} 158 159/* 160 * octeon_debug_symbol 161 * 162 * Does nothing. 163 * Used to mark the point for simulator to begin tracing 164 */ 165void 166octeon_debug_symbol(void) 167{ 168} 169 170/* 171 * octeon_ciu_reset 172 * 173 * Shutdown all CIU to IP2, IP3 mappings 174 */ 175void 176octeon_ciu_reset(void) 177{ 178 uint64_t cvmctl; 179 180 /* Disable all CIU interrupts by default */ 181 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 182 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 183 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 184 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 185 186#ifdef SMP 187 /* Enable the MBOX interrupts. */ 188 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 189 (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 190 (1ull << (OCTEON_IRQ_MBOX1 - 8))); 191#endif 192 193 /* 194 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ 195 */ 196 cvmctl = mips_rd_cvmctl(); 197 cvmctl &= ~(7 << 7); 198 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7; 199 mips_wr_cvmctl(cvmctl); 200} 201 202static void 203octeon_memory_init(void) 204{ 205 vm_paddr_t phys_end; 206 int64_t addr; 207 unsigned i, j; 208 209 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 210 211 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { 212 /* Simulator we limit to 96 meg */ 213 phys_avail[0] = phys_end; 214 phys_avail[1] = 96 << 20; 215 216 dump_avail[0] = phys_avail[0]; 217 dump_avail[1] = phys_avail[1]; 218 219 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 220 return; 221 } 222 223 /* 224 * Allocate memory from bootmem 1MB at a time and merge 225 * adjacent entries. 226 */ 227 i = 0; 228 while (i < PHYS_AVAIL_ENTRIES) { 229 /* 230 * If there is less than 2MB of memory available in 128-byte 231 * blocks, do not steal any more memory. We need to leave some 232 * memory for the command queues to be allocated out of. 233 */ 234 if (cvmx_bootmem_available_mem(128) < 2 << 20) 235 break; 236 237 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 238 ~(vm_paddr_t)0, PAGE_SIZE, 0); 239 if (addr == -1) 240 break; 241 242 /* 243 * The SDK needs to be able to easily map any memory that might 244 * come to it e.g. in the form of an mbuf. Because on !n64 we 245 * can't direct-map some addresses and we don't want to manage 246 * temporary mappings within the SDK, don't feed memory that 247 * can't be direct-mapped to the kernel. 248 */ 249#if !defined(__mips_n64) 250 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 251 continue; 252#endif 253 254 physmem += btoc(1 << 20); 255 256 if (i > 0 && phys_avail[i - 1] == addr) { 257 phys_avail[i - 1] += 1 << 20; 258 continue; 259 } 260 261 phys_avail[i + 0] = addr; 262 phys_avail[i + 1] = addr + (1 << 20); 263 264 i += 2; 265 } 266 267 for (j = 0; j < i; j++) 268 dump_avail[j] = phys_avail[j]; 269 270 realmem = physmem; 271} 272 273void 274platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 275 __register_t a3) 276{ 277 const struct octeon_feature_description *ofd; 278 uint64_t platform_counter_freq; 279 int rv; 280 281 mips_postboot_fixup(); 282 283 /* 284 * Initialize boot parameters so that we can determine things like 285 * which console we shoud use, etc. 286 */ 287 octeon_boot_params_init(a3); 288 289 /* Initialize pcpu stuff */ 290 mips_pcpu0_init(); 291 mips_timer_early_init(cvmx_sysinfo_get()->cpu_clock_hz); 292 293 /* Initialize console. */ 294 cninit(); 295 296 /* 297 * Display information about the CPU. 298 */ 299#if !defined(OCTEON_MODEL) 300 printf("Using runtime CPU model checks.\n"); 301#else 302 printf("Compiled for CPU model: " __XSTRING(OCTEON_MODEL) "\n"); 303#endif 304 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 305 printf("CPU Model: %s\n", cpu_model); 306 printf("CPU clock: %uMHz Core Mask: %#x\n", 307 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 308 cvmx_sysinfo_get()->core_mask); 309 rv = octeon_model_version_check(cvmx_get_proc_id()); 310 if (rv == -1) 311 panic("%s: kernel not compatible with this processor.", __func__); 312 313 /* 314 * Display information about the board. 315 */ 316#if defined(OCTEON_BOARD_CAPK_0100ND) 317 strcpy(cpu_board, "CAPK-0100ND"); 318 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 319 panic("Compiled for %s, but board type is %s.", cpu_board, 320 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 321 } 322#else 323 strcpy(cpu_board, 324 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 325#endif 326 printf("Board: %s\n", cpu_board); 327 printf("Board Type: %u Revision: %u/%u\n", 328 cvmx_sysinfo_get()->board_type, 329 cvmx_sysinfo_get()->board_rev_major, 330 cvmx_sysinfo_get()->board_rev_minor); 331 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number); 332 333 /* 334 * Additional on-chip hardware/settings. 335 * 336 * XXX Display PCI host/target? What else? 337 */ 338 printf("MAC address base: %6D (%u configured)\n", 339 cvmx_sysinfo_get()->mac_addr_base, ":", 340 cvmx_sysinfo_get()->mac_addr_count); 341 342 343 octeon_ciu_reset(); 344 /* 345 * XXX 346 * We can certainly parse command line arguments or U-Boot environment 347 * to determine whether to bootverbose / single user / ... I think 348 * stass has patches to add support for loader things to U-Boot even. 349 */ 350 bootverbose = 1; 351 352 /* 353 * For some reason on the cn38xx simulator ebase register is set to 354 * 0x80001000 at bootup time. Move it back to the default, but 355 * when we move to having support for multiple executives, we need 356 * to rethink this. 357 */ 358 mips_wr_ebase(0x80000000); 359 360 octeon_memory_init(); 361 init_param1(); 362 init_param2(physmem); 363 mips_cpu_init(); 364 pmap_bootstrap(); 365 mips_proc0_init(); 366 mutex_init(); 367 kdb_init(); 368#ifdef KDB 369 if (boothowto & RB_KDB) 370 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 371#endif 372 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 373 platform_counter_freq = cpu_clock; 374 octeon_timecounter.tc_frequency = cpu_clock; 375 platform_timecounter = &octeon_timecounter; 376 mips_timer_init_params(platform_counter_freq, 0); 377 set_cputicker(octeon_get_ticks, cpu_clock, 0); 378 379#ifdef SMP 380 /* 381 * Clear any pending IPIs. 382 */ 383 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 384#endif 385 386 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 387 printf("Available Octeon features:"); 388 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 389 if (octeon_has_feature(ofd->ofd_feature)) 390 printf(" %s", ofd->ofd_string); 391 printf("\n"); 392} 393 394static uint64_t 395octeon_get_ticks(void) 396{ 397 uint64_t cvmcount; 398 399 CVMX_MF_CYCLE(cvmcount); 400 return (cvmcount); 401} 402 403static unsigned 404octeon_get_timecount(struct timecounter *tc) 405{ 406 return ((unsigned)octeon_get_ticks()); 407} 408 409static int 410sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS) 411{ 412 size_t buflen; 413 char buf[9]; 414 int error; 415 416 if (req->newptr == NULL) 417 return (EINVAL); 418 419 if (cvmx_sysinfo_get()->led_display_base_addr == 0) 420 return (ENODEV); 421 422 /* 423 * Revision 1.x of the EBT3000 only supports 4 characters, but 424 * other devices support 8. 425 */ 426 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 427 cvmx_sysinfo_get()->board_rev_major == 1) 428 buflen = 4; 429 else 430 buflen = 8; 431 432 if (req->newlen > buflen) 433 return (E2BIG); 434 435 error = SYSCTL_IN(req, buf, req->newlen); 436 if (error != 0) 437 return (error); 438 439 buf[req->newlen] = '\0'; 440 ebt3000_str_write(buf); 441 442 return (0); 443} 444 445SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR, 446 NULL, 0, sysctl_machdep_led_display, "A", 447 "String to display on LED display"); 448 449/** 450 * version of printf that works better in exception context. 451 * 452 * @param format 453 * 454 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 455 */ 456void cvmx_safe_printf(const char *format, ...) 457{ 458 char buffer[256]; 459 char *ptr = buffer; 460 int count; 461 va_list args; 462 463 va_start(args, format); 464#ifndef __U_BOOT__ 465 count = vsnprintf(buffer, sizeof(buffer), format, args); 466#else 467 count = vsprintf(buffer, format, args); 468#endif 469 va_end(args); 470 471 while (count-- > 0) 472 { 473 cvmx_uart_lsr_t lsrval; 474 475 /* Spin until there is room */ 476 do 477 { 478 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 479#if !defined(CONFIG_OCTEON_SIM_SPEED) 480 if (lsrval.s.temt == 0) 481 cvmx_wait(10000); /* Just to reduce the load on the system */ 482#endif 483 } 484 while (lsrval.s.temt == 0); 485 486 if (*ptr == '\n') 487 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 488 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 489 } 490} 491 492/* impSTART: This stuff should move back into the Cavium SDK */ 493/* 494 **************************************************************************************** 495 * 496 * APP/BOOT DESCRIPTOR STUFF 497 * 498 **************************************************************************************** 499 */ 500 501/* Define the struct that is initialized by the bootloader used by the 502 * startup code. 503 * 504 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 505 * 506 * The authors hereby grant permission to use, copy, modify, distribute, 507 * and license this software and its documentation for any purpose, provided 508 * that existing copyright notices are retained in all copies and that this 509 * notice is included verbatim in any distributions. No written agreement, 510 * license, or royalty fee is required for any of the authorized uses. 511 * Modifications to this software may be copyrighted by their authors 512 * and need not follow the licensing terms described here, provided that 513 * the new terms are clearly indicated on the first page of each file where 514 * they apply. 515 */ 516 517#define OCTEON_CURRENT_DESC_VERSION 6 518#define OCTEON_ARGV_MAX_ARGS (64) 519#define OCTOEN_SERIAL_LEN 20 520 521typedef struct { 522 /* Start of block referenced by assembly code - do not change! */ 523 uint32_t desc_version; 524 uint32_t desc_size; 525 526 uint64_t stack_top; 527 uint64_t heap_base; 528 uint64_t heap_end; 529 uint64_t entry_point; /* Only used by bootloader */ 530 uint64_t desc_vaddr; 531 /* End of This block referenced by assembly code - do not change! */ 532 533 uint32_t exception_base_addr; 534 uint32_t stack_size; 535 uint32_t heap_size; 536 uint32_t argc; /* Argc count for application */ 537 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 538 uint32_t flags; 539 uint32_t core_mask; 540 uint32_t dram_size; /**< DRAM size in megabyes */ 541 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 542 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 543 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 544 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 545 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 546 uint16_t board_type; 547 uint8_t board_rev_major; 548 uint8_t board_rev_minor; 549 uint16_t chip_type; 550 uint8_t chip_rev_major; 551 uint8_t chip_rev_minor; 552 char board_serial_number[OCTOEN_SERIAL_LEN]; 553 uint8_t mac_addr_base[6]; 554 uint8_t mac_addr_count; 555 uint64_t cvmx_desc_vaddr; 556} octeon_boot_descriptor_t; 557 558static cvmx_bootinfo_t * 559octeon_process_app_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr) 560{ 561 cvmx_bootinfo_t *octeon_bootinfo; 562 563 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 564 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 565 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) { 566 cvmx_safe_printf("Bad octeon_bootinfo %#jx\n", 567 (uintmax_t)app_desc_ptr->cvmx_desc_vaddr); 568 return (NULL); 569 } 570 571 octeon_bootinfo = cvmx_phys_to_ptr(app_desc_ptr->cvmx_desc_vaddr); 572 if (octeon_bootinfo->major_version != 1) { 573 cvmx_safe_printf("Incompatible CVMX descriptor from bootloader: %d.%d %p\n", 574 (int) octeon_bootinfo->major_version, 575 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 576 return (NULL); 577 } 578 579 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 580 octeon_bootinfo->board_type, 581 octeon_bootinfo->board_rev_major, 582 octeon_bootinfo->board_rev_minor, 583 octeon_bootinfo->eclock_hz); 584 memcpy(cvmx_sysinfo_get()->mac_addr_base, 585 octeon_bootinfo->mac_addr_base, 6); 586 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 587 cvmx_sysinfo_get()->compact_flash_common_base_addr = 588 octeon_bootinfo->compact_flash_common_base_addr; 589 cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 590 octeon_bootinfo->compact_flash_attribute_base_addr; 591 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 592 cvmx_sysinfo_get()->led_display_base_addr = 593 octeon_bootinfo->led_display_base_addr; 594 memcpy(cvmx_sysinfo_get()->board_serial_number, 595 octeon_bootinfo->board_serial_number, 596 sizeof cvmx_sysinfo_get()->board_serial_number); 597 return (octeon_bootinfo); 598} 599 600static void 601octeon_boot_params_init(register_t ptr) 602{ 603 octeon_boot_descriptor_t *app_desc_ptr; 604 cvmx_bootinfo_t *octeon_bootinfo; 605 606 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) { 607 cvmx_safe_printf("app descriptor passed at invalid address %#jx\n", 608 (uintmax_t)ptr); 609 platform_reset(); 610 } 611 612 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 613 if (app_desc_ptr->desc_version < 6) { 614 cvmx_safe_printf("Your boot code is too old to be supported.\n"); 615 platform_reset(); 616 } 617 octeon_bootinfo = octeon_process_app_desc_ver_6(app_desc_ptr); 618 if (octeon_bootinfo == NULL) { 619 cvmx_safe_printf("Could not parse boot descriptor.\n"); 620 platform_reset(); 621 } 622 623 if (cvmx_sysinfo_get()->led_display_base_addr != 0) { 624 /* 625 * Revision 1.x of the EBT3000 only supports 4 characters, but 626 * other devices support 8. 627 */ 628 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 629 cvmx_sysinfo_get()->board_rev_major == 1) 630 ebt3000_str_write("FBSD"); 631 else 632 ebt3000_str_write("FreeBSD!"); 633 } 634 635 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) { 636 cvmx_safe_printf("Your boot loader did not supply a memory descriptor.\n"); 637 platform_reset(); 638 } 639 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 640 641 octeon_feature_init(); 642 643 __cvmx_helper_cfg_init(); 644} 645/* impEND: This stuff should move back into the Cavium SDK */ 646