octeon_machdep.c revision 242344
1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 242344 2012-10-30 06:19:46Z jmallett $ 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 242344 2012-10-30 06:19:46Z jmallett $"); 30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/cons.h> 41#include <sys/exec.h> 42#include <sys/ucontext.h> 43#include <sys/proc.h> 44#include <sys/kdb.h> 45#include <sys/ptrace.h> 46#include <sys/reboot.h> 47#include <sys/signalvar.h> 48#include <sys/sysctl.h> 49#include <sys/sysent.h> 50#include <sys/sysproto.h> 51#include <sys/time.h> 52#include <sys/timetc.h> 53#include <sys/user.h> 54 55#include <vm/vm.h> 56#include <vm/vm_object.h> 57#include <vm/vm_page.h> 58#include <vm/vm_pager.h> 59 60#include <machine/atomic.h> 61#include <machine/cache.h> 62#include <machine/clock.h> 63#include <machine/cpu.h> 64#include <machine/cpuregs.h> 65#include <machine/cpufunc.h> 66#include <mips/cavium/octeon_pcmap_regs.h> 67#include <machine/hwfunc.h> 68#include <machine/intr_machdep.h> 69#include <machine/locore.h> 70#include <machine/md_var.h> 71#include <machine/pcpu.h> 72#include <machine/pte.h> 73#include <machine/trap.h> 74#include <machine/vmparam.h> 75 76#include <contrib/octeon-sdk/cvmx.h> 77#include <contrib/octeon-sdk/cvmx-bootmem.h> 78#include <contrib/octeon-sdk/cvmx-ebt3000.h> 79#include <contrib/octeon-sdk/cvmx-helper-cfg.h> 80#include <contrib/octeon-sdk/cvmx-interrupt.h> 81#include <contrib/octeon-sdk/cvmx-version.h> 82 83#include <mips/cavium/octeon_irq.h> 84 85#if defined(__mips_n64) 86#define MAX_APP_DESC_ADDR 0xffffffffafffffff 87#else 88#define MAX_APP_DESC_ADDR 0xafffffff 89#endif 90 91#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 92 93struct octeon_feature_description { 94 octeon_feature_t ofd_feature; 95 const char *ofd_string; 96}; 97 98extern int *edata; 99extern int *end; 100extern char cpu_model[]; 101extern char cpu_board[]; 102 103static const struct octeon_feature_description octeon_feature_descriptions[] = { 104 { OCTEON_FEATURE_SAAD, "SAAD" }, 105 { OCTEON_FEATURE_ZIP, "ZIP" }, 106 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 107 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 108 { OCTEON_FEATURE_PCIE, "PCIE" }, 109 { OCTEON_FEATURE_SRIO, "SRIO" }, 110 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 111 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 112 { OCTEON_FEATURE_TRA, "TRA" }, 113 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 114 { OCTEON_FEATURE_RAID, "RAID" }, 115 { OCTEON_FEATURE_USB, "USB" }, 116 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 117 { OCTEON_FEATURE_DFA, "DFA" }, 118 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 119 { OCTEON_FEATURE_NPEI, "NPEI" }, 120 { OCTEON_FEATURE_ILK, "ILK" }, 121 { OCTEON_FEATURE_HFA, "HFA" }, 122 { OCTEON_FEATURE_DFM, "DFM" }, 123 { OCTEON_FEATURE_CIU2, "CIU2" }, 124 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 125 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 126 { OCTEON_FEATURE_NAND, "NAND" }, 127 { OCTEON_FEATURE_MMC, "MMC" }, 128 { OCTEON_FEATURE_PKND, "PKND" }, 129 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 130 { 0, NULL } 131}; 132 133static uint64_t octeon_get_ticks(void); 134static unsigned octeon_get_timecount(struct timecounter *tc); 135 136static void octeon_boot_params_init(register_t ptr); 137 138static struct timecounter octeon_timecounter = { 139 octeon_get_timecount, /* get_timecount */ 140 0, /* no poll_pps */ 141 0xffffffffu, /* octeon_mask */ 142 0, /* frequency */ 143 "Octeon", /* name */ 144 900, /* quality (adjusted in code) */ 145}; 146 147void 148platform_cpu_init() 149{ 150 /* Nothing special yet */ 151} 152 153/* 154 * Perform a board-level soft-reset. 155 */ 156void 157platform_reset(void) 158{ 159 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 160} 161 162/* 163 * octeon_debug_symbol 164 * 165 * Does nothing. 166 * Used to mark the point for simulator to begin tracing 167 */ 168void 169octeon_debug_symbol(void) 170{ 171} 172 173/* 174 * octeon_ciu_reset 175 * 176 * Shutdown all CIU to IP2, IP3 mappings 177 */ 178void 179octeon_ciu_reset(void) 180{ 181 uint64_t cvmctl; 182 183 /* Disable all CIU interrupts by default */ 184 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 185 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 186 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 187 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 188 189#ifdef SMP 190 /* Enable the MBOX interrupts. */ 191 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 192 (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 193 (1ull << (OCTEON_IRQ_MBOX1 - 8))); 194#endif 195 196 /* 197 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ 198 */ 199 cvmctl = mips_rd_cvmctl(); 200 cvmctl &= ~(7 << 7); 201 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7; 202 mips_wr_cvmctl(cvmctl); 203} 204 205static void 206octeon_memory_init(void) 207{ 208 vm_paddr_t phys_end; 209 int64_t addr; 210 unsigned i, j; 211 212 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 213 214 if (octeon_is_simulation()) { 215 /* Simulator we limit to 96 meg */ 216 phys_avail[0] = phys_end; 217 phys_avail[1] = 96 << 20; 218 219 dump_avail[0] = phys_avail[0]; 220 dump_avail[1] = phys_avail[1]; 221 222 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 223 return; 224 } 225 226 /* 227 * Allocate memory from bootmem 1MB at a time and merge 228 * adjacent entries. 229 */ 230 i = 0; 231 while (i < PHYS_AVAIL_ENTRIES) { 232 /* 233 * If there is less than 2MB of memory available in 128-byte 234 * blocks, do not steal any more memory. We need to leave some 235 * memory for the command queues to be allocated out of. 236 */ 237 if (cvmx_bootmem_available_mem(128) < 2 << 20) 238 break; 239 240 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 241 ~(vm_paddr_t)0, PAGE_SIZE, 0); 242 if (addr == -1) 243 break; 244 245 /* 246 * The SDK needs to be able to easily map any memory that might 247 * come to it e.g. in the form of an mbuf. Because on !n64 we 248 * can't direct-map some addresses and we don't want to manage 249 * temporary mappings within the SDK, don't feed memory that 250 * can't be direct-mapped to the kernel. 251 */ 252#if !defined(__mips_n64) 253 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 254 continue; 255#endif 256 257 physmem += btoc(1 << 20); 258 259 if (i > 0 && phys_avail[i - 1] == addr) { 260 phys_avail[i - 1] += 1 << 20; 261 continue; 262 } 263 264 phys_avail[i + 0] = addr; 265 phys_avail[i + 1] = addr + (1 << 20); 266 267 i += 2; 268 } 269 270 for (j = 0; j < i; j++) 271 dump_avail[j] = phys_avail[j]; 272 273 realmem = physmem; 274} 275 276void 277platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 278 __register_t a3) 279{ 280 const struct octeon_feature_description *ofd; 281 uint64_t platform_counter_freq; 282 283 /* 284 * XXX 285 * octeon_boot_params_init() should be called before anything else, 286 * certainly before any output; we may find out from the boot 287 * descriptor's flags that we're supposed to use the PCI or UART1 288 * consoles rather than UART0. No point doing that reorganization 289 * until we actually intercept UART_DEV_CONSOLE for the UART1 case 290 * and somehow handle the PCI console, which we lack code for 291 * entirely. 292 */ 293 294 mips_postboot_fixup(); 295 296 /* Initialize pcpu stuff */ 297 mips_pcpu0_init(); 298 mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 299 cninit(); 300 301 octeon_ciu_reset(); 302 octeon_boot_params_init(a3); 303 /* 304 * XXX 305 * We can certainly parse command line arguments or U-Boot environment 306 * to determine whether to bootverbose / single user / ... I think 307 * stass has patches to add support for loader things to U-Boot even. 308 */ 309 bootverbose = 1; 310 311 /* 312 * For some reason on the cn38xx simulator ebase register is set to 313 * 0x80001000 at bootup time. Move it back to the default, but 314 * when we move to having support for multiple executives, we need 315 * to rethink this. 316 */ 317 mips_wr_ebase(0x80000000); 318 319 octeon_memory_init(); 320 init_param1(); 321 init_param2(physmem); 322 mips_cpu_init(); 323 pmap_bootstrap(); 324 mips_proc0_init(); 325 mutex_init(); 326 kdb_init(); 327#ifdef KDB 328 if (boothowto & RB_KDB) 329 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 330#endif 331 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 332 platform_counter_freq = cpu_clock; 333 octeon_timecounter.tc_frequency = cpu_clock; 334 platform_timecounter = &octeon_timecounter; 335 mips_timer_init_params(platform_counter_freq, 0); 336 set_cputicker(octeon_get_ticks, cpu_clock, 0); 337 338#ifdef SMP 339 /* 340 * Clear any pending IPIs. 341 */ 342 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 343#endif 344 345 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 346 printf("Available Octeon features:"); 347 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 348 if (octeon_has_feature(ofd->ofd_feature)) 349 printf(" %s", ofd->ofd_string); 350 printf("\n"); 351} 352 353static uint64_t 354octeon_get_ticks(void) 355{ 356 uint64_t cvmcount; 357 358 CVMX_MF_CYCLE(cvmcount); 359 return (cvmcount); 360} 361 362static unsigned 363octeon_get_timecount(struct timecounter *tc) 364{ 365 return ((unsigned)octeon_get_ticks()); 366} 367 368static int 369sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS) 370{ 371 size_t buflen; 372 char buf[9]; 373 int error; 374 375 if (req->newptr == NULL) 376 return (EINVAL); 377 378 if (cvmx_sysinfo_get()->led_display_base_addr == 0) 379 return (ENODEV); 380 381 /* 382 * Revision 1.x of the EBT3000 only supports 4 characters, but 383 * other devices support 8. 384 */ 385 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 386 cvmx_sysinfo_get()->board_rev_major == 1) 387 buflen = 4; 388 else 389 buflen = 8; 390 391 if (req->newlen > buflen) 392 return (E2BIG); 393 394 error = SYSCTL_IN(req, buf, req->newlen); 395 if (error != 0) 396 return (error); 397 398 buf[req->newlen] = '\0'; 399 ebt3000_str_write(buf); 400 401 return (0); 402} 403 404SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR, 405 NULL, 0, sysctl_machdep_led_display, "A", 406 "String to display on LED display"); 407 408/** 409 * version of printf that works better in exception context. 410 * 411 * @param format 412 * 413 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 414 */ 415void cvmx_safe_printf(const char *format, ...) 416{ 417 char buffer[256]; 418 char *ptr = buffer; 419 int count; 420 va_list args; 421 422 va_start(args, format); 423#ifndef __U_BOOT__ 424 count = vsnprintf(buffer, sizeof(buffer), format, args); 425#else 426 count = vsprintf(buffer, format, args); 427#endif 428 va_end(args); 429 430 while (count-- > 0) 431 { 432 cvmx_uart_lsr_t lsrval; 433 434 /* Spin until there is room */ 435 do 436 { 437 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 438#if !defined(CONFIG_OCTEON_SIM_SPEED) 439 if (lsrval.s.temt == 0) 440 cvmx_wait(10000); /* Just to reduce the load on the system */ 441#endif 442 } 443 while (lsrval.s.temt == 0); 444 445 if (*ptr == '\n') 446 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 447 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 448 } 449} 450 451/* impSTART: This stuff should move back into the Cavium SDK */ 452/* 453 **************************************************************************************** 454 * 455 * APP/BOOT DESCRIPTOR STUFF 456 * 457 **************************************************************************************** 458 */ 459 460/* Define the struct that is initialized by the bootloader used by the 461 * startup code. 462 * 463 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 464 * 465 * The authors hereby grant permission to use, copy, modify, distribute, 466 * and license this software and its documentation for any purpose, provided 467 * that existing copyright notices are retained in all copies and that this 468 * notice is included verbatim in any distributions. No written agreement, 469 * license, or royalty fee is required for any of the authorized uses. 470 * Modifications to this software may be copyrighted by their authors 471 * and need not follow the licensing terms described here, provided that 472 * the new terms are clearly indicated on the first page of each file where 473 * they apply. 474 */ 475 476#define OCTEON_CURRENT_DESC_VERSION 6 477#define OCTEON_ARGV_MAX_ARGS (64) 478#define OCTOEN_SERIAL_LEN 20 479 480typedef struct { 481 /* Start of block referenced by assembly code - do not change! */ 482 uint32_t desc_version; 483 uint32_t desc_size; 484 485 uint64_t stack_top; 486 uint64_t heap_base; 487 uint64_t heap_end; 488 uint64_t entry_point; /* Only used by bootloader */ 489 uint64_t desc_vaddr; 490 /* End of This block referenced by assembly code - do not change! */ 491 492 uint32_t exception_base_addr; 493 uint32_t stack_size; 494 uint32_t heap_size; 495 uint32_t argc; /* Argc count for application */ 496 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 497 uint32_t flags; 498 uint32_t core_mask; 499 uint32_t dram_size; /**< DRAM size in megabyes */ 500 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 501 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 502 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 503 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 504 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 505 uint16_t board_type; 506 uint8_t board_rev_major; 507 uint8_t board_rev_minor; 508 uint16_t chip_type; 509 uint8_t chip_rev_major; 510 uint8_t chip_rev_minor; 511 char board_serial_number[OCTOEN_SERIAL_LEN]; 512 uint8_t mac_addr_base[6]; 513 uint8_t mac_addr_count; 514 uint64_t cvmx_desc_vaddr; 515} octeon_boot_descriptor_t; 516 517cvmx_bootinfo_t *octeon_bootinfo; 518 519static octeon_boot_descriptor_t *app_desc_ptr; 520 521int 522octeon_is_simulation(void) 523{ 524 switch (cvmx_sysinfo_get()->board_type) { 525 case CVMX_BOARD_TYPE_SIM: 526 return 1; 527 default: 528 return 0; 529 } 530} 531 532static void 533octeon_process_app_desc_ver_6(void) 534{ 535 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 536 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 537 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 538 panic("Bad octeon_bootinfo %p", octeon_bootinfo); 539 540 octeon_bootinfo = 541 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 542 octeon_bootinfo = 543 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 544 if (octeon_bootinfo->major_version != 1) 545 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 546 (int) octeon_bootinfo->major_version, 547 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 548 549 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 550 octeon_bootinfo->board_type, 551 octeon_bootinfo->board_rev_major, 552 octeon_bootinfo->board_rev_minor, 553 octeon_bootinfo->eclock_hz); 554 memcpy(cvmx_sysinfo_get()->mac_addr_base, 555 octeon_bootinfo->mac_addr_base, 6); 556 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 557 cvmx_sysinfo_get()->compact_flash_common_base_addr = 558 octeon_bootinfo->compact_flash_common_base_addr; 559 cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 560 octeon_bootinfo->compact_flash_attribute_base_addr; 561 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 562 cvmx_sysinfo_get()->led_display_base_addr = 563 octeon_bootinfo->led_display_base_addr; 564 memcpy(cvmx_sysinfo_get()->board_serial_number, 565 octeon_bootinfo->board_serial_number, 566 sizeof cvmx_sysinfo_get()->board_serial_number); 567} 568 569static void 570octeon_boot_params_init(register_t ptr) 571{ 572 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 573 panic("app descriptor passed at invalid address %#jx", 574 (uintmax_t)ptr); 575 576 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 577 if (app_desc_ptr->desc_version < 6) 578 panic("Your boot code is too old to be supported."); 579 octeon_process_app_desc_ver_6(); 580 581 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 582 583 if (cvmx_sysinfo_get()->led_display_base_addr != 0) { 584 /* 585 * Revision 1.x of the EBT3000 only supports 4 characters, but 586 * other devices support 8. 587 */ 588 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 589 cvmx_sysinfo_get()->board_rev_major == 1) 590 ebt3000_str_write("FBSD"); 591 else 592 ebt3000_str_write("FreeBSD!"); 593 } 594 595 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 596 panic("Your boot loader did not supply a memory descriptor."); 597 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 598 599 octeon_feature_init(); 600 601 __cvmx_helper_cfg_init(); 602 603 printf("Boot Descriptor Ver: %u -> %u/%u", 604 app_desc_ptr->desc_version, octeon_bootinfo->major_version, 605 octeon_bootinfo->minor_version); 606 printf(" CPU clock: %uMHz Core Mask: %#x\n", 607 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 608 cvmx_sysinfo_get()->core_mask); 609 printf(" Board Type: %u Revision: %u/%u\n", 610 cvmx_sysinfo_get()->board_type, 611 cvmx_sysinfo_get()->board_rev_major, 612 cvmx_sysinfo_get()->board_rev_minor); 613 614 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 615 octeon_bootinfo->mac_addr_base[0], 616 octeon_bootinfo->mac_addr_base[1], 617 octeon_bootinfo->mac_addr_base[2], 618 octeon_bootinfo->mac_addr_base[3], 619 octeon_bootinfo->mac_addr_base[4], 620 octeon_bootinfo->mac_addr_base[5], 621 octeon_bootinfo->mac_addr_count); 622 623#if defined(OCTEON_BOARD_CAPK_0100ND) 624 strcpy(cpu_board, "CAPK-0100ND"); 625 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 626 printf("Compiled for CAPK-0100ND, but board type is %s\n", 627 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 628 strcat(cpu_board, " hardwired, but type is "); 629 strcat(cpu_board, 630 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 631 } 632#else 633 strcpy(cpu_board, 634 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 635 printf("Board: %s\n", cpu_board); 636#endif 637 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 638 printf("Model: %s\n", cpu_model); 639 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number); 640} 641/* impEND: This stuff should move back into the Cavium SDK */ 642