octeon_machdep.c revision 232812
1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 232812 2012-03-11 06:17:49Z jmallett $ 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 232812 2012-03-11 06:17:49Z jmallett $"); 30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/cons.h> 41#include <sys/exec.h> 42#include <sys/ucontext.h> 43#include <sys/proc.h> 44#include <sys/kdb.h> 45#include <sys/ptrace.h> 46#include <sys/reboot.h> 47#include <sys/signalvar.h> 48#include <sys/sysent.h> 49#include <sys/sysproto.h> 50#include <sys/time.h> 51#include <sys/timetc.h> 52#include <sys/user.h> 53 54#include <vm/vm.h> 55#include <vm/vm_object.h> 56#include <vm/vm_page.h> 57#include <vm/vm_pager.h> 58 59#include <machine/atomic.h> 60#include <machine/cache.h> 61#include <machine/clock.h> 62#include <machine/cpu.h> 63#include <machine/cpuregs.h> 64#include <machine/cpufunc.h> 65#include <mips/cavium/octeon_pcmap_regs.h> 66#include <machine/hwfunc.h> 67#include <machine/intr_machdep.h> 68#include <machine/locore.h> 69#include <machine/md_var.h> 70#include <machine/pcpu.h> 71#include <machine/pte.h> 72#include <machine/trap.h> 73#include <machine/vmparam.h> 74 75#include <contrib/octeon-sdk/cvmx.h> 76#include <contrib/octeon-sdk/cvmx-bootmem.h> 77#include <contrib/octeon-sdk/cvmx-interrupt.h> 78#include <contrib/octeon-sdk/cvmx-version.h> 79 80#include <mips/cavium/octeon_irq.h> 81 82#if defined(__mips_n64) 83#define MAX_APP_DESC_ADDR 0xffffffffafffffff 84#else 85#define MAX_APP_DESC_ADDR 0xafffffff 86#endif 87 88#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 89 90struct octeon_feature_description { 91 octeon_feature_t ofd_feature; 92 const char *ofd_string; 93}; 94 95extern int *edata; 96extern int *end; 97extern char cpu_model[]; 98extern char cpu_board[]; 99 100static const struct octeon_feature_description octeon_feature_descriptions[] = { 101 { OCTEON_FEATURE_SAAD, "SAAD" }, 102 { OCTEON_FEATURE_ZIP, "ZIP" }, 103 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 104 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 105 { OCTEON_FEATURE_PCIE, "PCIE" }, 106 { OCTEON_FEATURE_SRIO, "SRIO" }, 107 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 108 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 109 { OCTEON_FEATURE_TRA, "TRA" }, 110 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 111 { OCTEON_FEATURE_RAID, "RAID" }, 112 { OCTEON_FEATURE_USB, "USB" }, 113 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 114 { OCTEON_FEATURE_DFA, "DFA" }, 115 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 116 { OCTEON_FEATURE_NPEI, "NPEI" }, 117 { OCTEON_FEATURE_ILK, "ILK" }, 118 { OCTEON_FEATURE_HFA, "HFA" }, 119 { OCTEON_FEATURE_DFM, "DFM" }, 120 { OCTEON_FEATURE_CIU2, "CIU2" }, 121 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 122 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 123 { OCTEON_FEATURE_NAND, "NAND" }, 124 { OCTEON_FEATURE_MMC, "MMC" }, 125 { OCTEON_FEATURE_PKND, "PKND" }, 126 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 127 { 0, NULL } 128}; 129 130uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 131void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 132 133static uint64_t octeon_get_ticks(void); 134static unsigned octeon_get_timecount(struct timecounter *tc); 135 136static void octeon_boot_params_init(register_t ptr); 137 138static struct timecounter octeon_timecounter = { 139 octeon_get_timecount, /* get_timecount */ 140 0, /* no poll_pps */ 141 0xffffffffu, /* octeon_mask */ 142 0, /* frequency */ 143 "Octeon", /* name */ 144 900, /* quality (adjusted in code) */ 145}; 146 147void 148platform_cpu_init() 149{ 150 /* Nothing special yet */ 151} 152 153/* 154 * Perform a board-level soft-reset. 155 */ 156void 157platform_reset(void) 158{ 159 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 160} 161 162void 163octeon_led_write_char(int char_position, char val) 164{ 165 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 166 167 if (octeon_is_simulation()) 168 return; 169 170 char_position &= 0x7; /* only 8 chars */ 171 ptr += char_position; 172 oct_write8_x8(ptr, val); 173} 174 175void 176octeon_led_write_char0(char val) 177{ 178 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 179 180 if (octeon_is_simulation()) 181 return; 182 oct_write8_x8(ptr, val); 183} 184 185void 186octeon_led_write_hexchar(int char_position, char hexval) 187{ 188 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 189 char char1, char2; 190 191 if (octeon_is_simulation()) 192 return; 193 194 char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7'; 195 char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7'; 196 char_position &= 0x7; /* only 8 chars */ 197 if (char_position > 6) 198 char_position = 6; 199 ptr += char_position; 200 oct_write8_x8(ptr, char1); 201 ptr++; 202 oct_write8_x8(ptr, char2); 203} 204 205void 206octeon_led_write_string(const char *str) 207{ 208 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 209 int i; 210 211 if (octeon_is_simulation()) 212 return; 213 214 for (i=0; i<8; i++, ptr++) { 215 if (str && *str) 216 oct_write8_x8(ptr, *str++); 217 else 218 oct_write8_x8(ptr, ' '); 219 (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT); 220 } 221} 222 223static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'}; 224 225void 226octeon_led_run_wheel(int *prog_count, int led_position) 227{ 228 if (octeon_is_simulation()) 229 return; 230 octeon_led_write_char(led_position, progress[*prog_count]); 231 *prog_count += 1; 232 *prog_count &= 0x7; 233} 234 235void 236octeon_led_write_hex(uint32_t wl) 237{ 238 char nbuf[80]; 239 240 sprintf(nbuf, "%X", wl); 241 octeon_led_write_string(nbuf); 242} 243 244/* 245 * octeon_debug_symbol 246 * 247 * Does nothing. 248 * Used to mark the point for simulator to begin tracing 249 */ 250void 251octeon_debug_symbol(void) 252{ 253} 254 255/* 256 * octeon_ciu_reset 257 * 258 * Shutdown all CIU to IP2, IP3 mappings 259 */ 260void 261octeon_ciu_reset(void) 262{ 263 /* Disable all CIU interrupts by default */ 264 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 265 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 266 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 267 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 268 269#ifdef SMP 270 /* Enable the MBOX interrupts. */ 271 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 272 (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 273 (1ull << (OCTEON_IRQ_MBOX1 - 8))); 274#endif 275} 276 277static void 278octeon_memory_init(void) 279{ 280 vm_paddr_t phys_end; 281 int64_t addr; 282 unsigned i, j; 283 284 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 285 286 if (octeon_is_simulation()) { 287 /* Simulator we limit to 96 meg */ 288 phys_avail[0] = phys_end; 289 phys_avail[1] = 96 << 20; 290 291 dump_avail[0] = phys_avail[0]; 292 dump_avail[1] = phys_avail[1]; 293 294 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 295 return; 296 } 297 298 /* 299 * Allocate memory from bootmem 1MB at a time and merge 300 * adjacent entries. 301 */ 302 i = 0; 303 while (i < PHYS_AVAIL_ENTRIES) { 304 /* 305 * If there is less than 2MB of memory available in 128-byte 306 * blocks, do not steal any more memory. We need to leave some 307 * memory for the command queues to be allocated out of. 308 */ 309 if (cvmx_bootmem_available_mem(128) < 2 << 20) 310 break; 311 312 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 313 ~(vm_paddr_t)0, PAGE_SIZE, 0); 314 if (addr == -1) 315 break; 316 317 /* 318 * The SDK needs to be able to easily map any memory that might 319 * come to it e.g. in the form of an mbuf. Because on !n64 we 320 * can't direct-map some addresses and we don't want to manage 321 * temporary mappings within the SDK, don't feed memory that 322 * can't be direct-mapped to the kernel. 323 */ 324#if !defined(__mips_n64) 325 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 326 continue; 327#endif 328 329 physmem += btoc(1 << 20); 330 331 if (i > 0 && phys_avail[i - 1] == addr) { 332 phys_avail[i - 1] += 1 << 20; 333 continue; 334 } 335 336 phys_avail[i + 0] = addr; 337 phys_avail[i + 1] = addr + (1 << 20); 338 339 i += 2; 340 } 341 342 for (j = 0; j < i; j++) 343 dump_avail[j] = phys_avail[j]; 344 345 realmem = physmem; 346} 347 348void 349platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 350 __register_t a3) 351{ 352 const struct octeon_feature_description *ofd; 353 uint64_t platform_counter_freq; 354 355 /* 356 * XXX 357 * octeon_boot_params_init() should be called before anything else, 358 * certainly before any output; we may find out from the boot 359 * descriptor's flags that we're supposed to use the PCI or UART1 360 * consoles rather than UART0. No point doing that reorganization 361 * until we actually intercept UART_DEV_CONSOLE for the UART1 case 362 * and somehow handle the PCI console, which we lack code for 363 * entirely. 364 */ 365 366 /* Initialize pcpu stuff */ 367 mips_pcpu0_init(); 368 mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 369 cninit(); 370 371 octeon_ciu_reset(); 372 octeon_boot_params_init(a3); 373 /* 374 * XXX 375 * We can certainly parse command line arguments or U-Boot environment 376 * to determine whether to bootverbose / single user / ... I think 377 * stass has patches to add support for loader things to U-Boot even. 378 */ 379 bootverbose = 1; 380 381 /* 382 * For some reason on the cn38xx simulator ebase register is set to 383 * 0x80001000 at bootup time. Move it back to the default, but 384 * when we move to having support for multiple executives, we need 385 * to rethink this. 386 */ 387 mips_wr_ebase(0x80000000); 388 389 octeon_memory_init(); 390 init_param1(); 391 init_param2(physmem); 392 mips_cpu_init(); 393 pmap_bootstrap(); 394 mips_proc0_init(); 395 mutex_init(); 396 kdb_init(); 397#ifdef KDB 398 if (boothowto & RB_KDB) 399 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 400#endif 401 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 402 platform_counter_freq = cpu_clock; 403 octeon_timecounter.tc_frequency = cpu_clock; 404 platform_timecounter = &octeon_timecounter; 405 mips_timer_init_params(platform_counter_freq, 0); 406 set_cputicker(octeon_get_ticks, cpu_clock, 0); 407 408#ifdef SMP 409 /* 410 * Clear any pending IPIs. 411 */ 412 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 413#endif 414 415 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 416 printf("Available Octeon features:"); 417 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 418 if (octeon_has_feature(ofd->ofd_feature)) 419 printf(" %s", ofd->ofd_string); 420 printf("\n"); 421} 422 423static uint64_t 424octeon_get_ticks(void) 425{ 426 uint64_t cvmcount; 427 428 CVMX_MF_CYCLE(cvmcount); 429 return (cvmcount); 430} 431 432static unsigned 433octeon_get_timecount(struct timecounter *tc) 434{ 435 return ((unsigned)octeon_get_ticks()); 436} 437 438/** 439 * version of printf that works better in exception context. 440 * 441 * @param format 442 * 443 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 444 */ 445void cvmx_safe_printf(const char *format, ...) 446{ 447 char buffer[256]; 448 char *ptr = buffer; 449 int count; 450 va_list args; 451 452 va_start(args, format); 453#ifndef __U_BOOT__ 454 count = vsnprintf(buffer, sizeof(buffer), format, args); 455#else 456 count = vsprintf(buffer, format, args); 457#endif 458 va_end(args); 459 460 while (count-- > 0) 461 { 462 cvmx_uart_lsr_t lsrval; 463 464 /* Spin until there is room */ 465 do 466 { 467 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 468#if !defined(CONFIG_OCTEON_SIM_SPEED) 469 if (lsrval.s.temt == 0) 470 cvmx_wait(10000); /* Just to reduce the load on the system */ 471#endif 472 } 473 while (lsrval.s.temt == 0); 474 475 if (*ptr == '\n') 476 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 477 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 478 } 479} 480 481/* impSTART: This stuff should move back into the Cavium SDK */ 482/* 483 **************************************************************************************** 484 * 485 * APP/BOOT DESCRIPTOR STUFF 486 * 487 **************************************************************************************** 488 */ 489 490/* Define the struct that is initialized by the bootloader used by the 491 * startup code. 492 * 493 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 494 * 495 * The authors hereby grant permission to use, copy, modify, distribute, 496 * and license this software and its documentation for any purpose, provided 497 * that existing copyright notices are retained in all copies and that this 498 * notice is included verbatim in any distributions. No written agreement, 499 * license, or royalty fee is required for any of the authorized uses. 500 * Modifications to this software may be copyrighted by their authors 501 * and need not follow the licensing terms described here, provided that 502 * the new terms are clearly indicated on the first page of each file where 503 * they apply. 504 */ 505 506#define OCTEON_CURRENT_DESC_VERSION 6 507#define OCTEON_ARGV_MAX_ARGS (64) 508#define OCTOEN_SERIAL_LEN 20 509 510typedef struct { 511 /* Start of block referenced by assembly code - do not change! */ 512 uint32_t desc_version; 513 uint32_t desc_size; 514 515 uint64_t stack_top; 516 uint64_t heap_base; 517 uint64_t heap_end; 518 uint64_t entry_point; /* Only used by bootloader */ 519 uint64_t desc_vaddr; 520 /* End of This block referenced by assembly code - do not change! */ 521 522 uint32_t exception_base_addr; 523 uint32_t stack_size; 524 uint32_t heap_size; 525 uint32_t argc; /* Argc count for application */ 526 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 527 uint32_t flags; 528 uint32_t core_mask; 529 uint32_t dram_size; /**< DRAM size in megabyes */ 530 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 531 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 532 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 533 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 534 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 535 uint16_t board_type; 536 uint8_t board_rev_major; 537 uint8_t board_rev_minor; 538 uint16_t chip_type; 539 uint8_t chip_rev_major; 540 uint8_t chip_rev_minor; 541 char board_serial_number[OCTOEN_SERIAL_LEN]; 542 uint8_t mac_addr_base[6]; 543 uint8_t mac_addr_count; 544 uint64_t cvmx_desc_vaddr; 545} octeon_boot_descriptor_t; 546 547cvmx_bootinfo_t *octeon_bootinfo; 548 549static octeon_boot_descriptor_t *app_desc_ptr; 550 551int 552octeon_is_simulation(void) 553{ 554 switch (cvmx_sysinfo_get()->board_type) { 555 case CVMX_BOARD_TYPE_SIM: 556 return 1; 557 default: 558 return 0; 559 } 560} 561 562static void 563octeon_process_app_desc_ver_6(void) 564{ 565 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 566 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 567 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 568 panic("Bad octeon_bootinfo %p", octeon_bootinfo); 569 570 octeon_bootinfo = 571 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 572 octeon_bootinfo = 573 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 574 if (octeon_bootinfo->major_version != 1) 575 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 576 (int) octeon_bootinfo->major_version, 577 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 578 579 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 580 octeon_bootinfo->board_type, 581 octeon_bootinfo->board_rev_major, 582 octeon_bootinfo->board_rev_minor, 583 octeon_bootinfo->eclock_hz); 584 memcpy(cvmx_sysinfo_get()->mac_addr_base, octeon_bootinfo->mac_addr_base, 6); 585 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 586 cvmx_sysinfo_get()->compact_flash_common_base_addr = 587 octeon_bootinfo->compact_flash_common_base_addr; 588 cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 589 octeon_bootinfo->compact_flash_attribute_base_addr; 590 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 591} 592 593static void 594octeon_boot_params_init(register_t ptr) 595{ 596 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 597 panic("app descriptor passed at invalid address %#jx", 598 (uintmax_t)ptr); 599 600 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 601 if (app_desc_ptr->desc_version < 6) 602 panic("Your boot code is too old to be supported."); 603 octeon_process_app_desc_ver_6(); 604 605 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 606 607 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 608 panic("Your boot loader did not supply a memory descriptor."); 609 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 610 611 printf("Boot Descriptor Ver: %u -> %u/%u", 612 app_desc_ptr->desc_version, octeon_bootinfo->major_version, 613 octeon_bootinfo->minor_version); 614 printf(" CPU clock: %uMHz Core Mask: %#x\n", 615 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 616 cvmx_sysinfo_get()->core_mask); 617 printf(" Board Type: %u Revision: %u/%u\n", 618 cvmx_sysinfo_get()->board_type, 619 cvmx_sysinfo_get()->board_rev_major, 620 cvmx_sysinfo_get()->board_rev_minor); 621 622 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 623 octeon_bootinfo->mac_addr_base[0], 624 octeon_bootinfo->mac_addr_base[1], 625 octeon_bootinfo->mac_addr_base[2], 626 octeon_bootinfo->mac_addr_base[3], 627 octeon_bootinfo->mac_addr_base[4], 628 octeon_bootinfo->mac_addr_base[5], 629 octeon_bootinfo->mac_addr_count); 630 631#if defined(OCTEON_BOARD_CAPK_0100ND) 632 strcpy(cpu_board, "CAPK-0100ND"); 633 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 634 printf("Compiled for CAPK-0100ND, but board type is %s\n", 635 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 636 strcat(cpu_board, " hardwired, but type is "); 637 strcat(cpu_board, 638 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 639 } 640#else 641 strcpy(cpu_board, 642 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 643 printf("Board: %s\n", cpu_board); 644#endif 645 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 646 printf("Model: %s\n", cpu_model); 647} 648/* impEND: This stuff should move back into the Cavium SDK */ 649