octeon_machdep.c revision 216320
1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 216320 2010-12-09 07:47:40Z gonzo $ 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 216320 2010-12-09 07:47:40Z gonzo $"); 30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> 38#include <sys/bus.h> 39#include <sys/cpu.h> 40#include <sys/cons.h> 41#include <sys/exec.h> 42#include <sys/ucontext.h> 43#include <sys/proc.h> 44#include <sys/kdb.h> 45#include <sys/ptrace.h> 46#include <sys/reboot.h> 47#include <sys/signalvar.h> 48#include <sys/sysent.h> 49#include <sys/sysproto.h> 50#include <sys/time.h> 51#include <sys/timetc.h> 52#include <sys/user.h> 53 54#include <vm/vm.h> 55#include <vm/vm_object.h> 56#include <vm/vm_page.h> 57#include <vm/vm_pager.h> 58 59#include <machine/atomic.h> 60#include <machine/cache.h> 61#include <machine/clock.h> 62#include <machine/cpu.h> 63#include <machine/cpuregs.h> 64#include <machine/cpufunc.h> 65#include <mips/cavium/octeon_pcmap_regs.h> 66#include <machine/hwfunc.h> 67#include <machine/intr_machdep.h> 68#include <machine/locore.h> 69#include <machine/md_var.h> 70#include <machine/pcpu.h> 71#include <machine/pte.h> 72#include <machine/trap.h> 73#include <machine/vmparam.h> 74 75#include <contrib/octeon-sdk/cvmx.h> 76#include <contrib/octeon-sdk/cvmx-bootmem.h> 77#include <contrib/octeon-sdk/cvmx-interrupt.h> 78#include <contrib/octeon-sdk/cvmx-version.h> 79 80#if defined(__mips_n64) 81#define MAX_APP_DESC_ADDR 0xffffffffafffffff 82#else 83#define MAX_APP_DESC_ADDR 0xafffffff 84#endif 85 86#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 87 88struct octeon_feature_description { 89 octeon_feature_t ofd_feature; 90 const char *ofd_string; 91}; 92 93extern int *edata; 94extern int *end; 95 96static const struct octeon_feature_description octeon_feature_descriptions[] = { 97 { OCTEON_FEATURE_SAAD, "SAAD" }, 98 { OCTEON_FEATURE_ZIP, "ZIP" }, 99 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 100 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 101 { OCTEON_FEATURE_PCIE, "PCIE" }, 102 { OCTEON_FEATURE_SRIO, "SRIO" }, 103 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 104 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 105 { OCTEON_FEATURE_TRA, "TRA" }, 106 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 107 { OCTEON_FEATURE_RAID, "RAID" }, 108 { OCTEON_FEATURE_USB, "USB" }, 109 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 110 { OCTEON_FEATURE_DFA, "DFA" }, 111 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 112 { OCTEON_FEATURE_NPEI, "NPEI" }, 113 { 0, NULL } 114}; 115 116uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 117void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 118 119static uint64_t octeon_get_ticks(void); 120static unsigned octeon_get_timecount(struct timecounter *tc); 121 122static void octeon_boot_params_init(register_t ptr); 123 124static struct timecounter octeon_timecounter = { 125 octeon_get_timecount, /* get_timecount */ 126 0, /* no poll_pps */ 127 0xffffffffu, /* octeon_mask */ 128 0, /* frequency */ 129 "Octeon", /* name */ 130 900, /* quality (adjusted in code) */ 131}; 132 133void 134platform_cpu_init() 135{ 136 /* Nothing special yet */ 137} 138 139/* 140 * Perform a board-level soft-reset. 141 */ 142void 143platform_reset(void) 144{ 145 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 146} 147 148void 149octeon_led_write_char(int char_position, char val) 150{ 151 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 152 153 if (octeon_is_simulation()) 154 return; 155 156 char_position &= 0x7; /* only 8 chars */ 157 ptr += char_position; 158 oct_write8_x8(ptr, val); 159} 160 161void 162octeon_led_write_char0(char val) 163{ 164 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 165 166 if (octeon_is_simulation()) 167 return; 168 oct_write8_x8(ptr, val); 169} 170 171void 172octeon_led_write_hexchar(int char_position, char hexval) 173{ 174 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 175 char char1, char2; 176 177 if (octeon_is_simulation()) 178 return; 179 180 char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7'; 181 char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7'; 182 char_position &= 0x7; /* only 8 chars */ 183 if (char_position > 6) 184 char_position = 6; 185 ptr += char_position; 186 oct_write8_x8(ptr, char1); 187 ptr++; 188 oct_write8_x8(ptr, char2); 189} 190 191void 192octeon_led_write_string(const char *str) 193{ 194 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 195 int i; 196 197 if (octeon_is_simulation()) 198 return; 199 200 for (i=0; i<8; i++, ptr++) { 201 if (str && *str) 202 oct_write8_x8(ptr, *str++); 203 else 204 oct_write8_x8(ptr, ' '); 205 (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT); 206 } 207} 208 209static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'}; 210 211void 212octeon_led_run_wheel(int *prog_count, int led_position) 213{ 214 if (octeon_is_simulation()) 215 return; 216 octeon_led_write_char(led_position, progress[*prog_count]); 217 *prog_count += 1; 218 *prog_count &= 0x7; 219} 220 221void 222octeon_led_write_hex(uint32_t wl) 223{ 224 char nbuf[80]; 225 226 sprintf(nbuf, "%X", wl); 227 octeon_led_write_string(nbuf); 228} 229 230/* 231 * octeon_debug_symbol 232 * 233 * Does nothing. 234 * Used to mark the point for simulator to begin tracing 235 */ 236void 237octeon_debug_symbol(void) 238{ 239} 240 241/* 242 * octeon_ciu_reset 243 * 244 * Shutdown all CIU to IP2, IP3 mappings 245 */ 246void 247octeon_ciu_reset(void) 248{ 249 /* Disable all CIU interrupts by default */ 250 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 251 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 252 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 253 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 254 255#ifdef SMP 256 /* Enable the MBOX interrupts. */ 257 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 258 (1ull << (CVMX_IRQ_MBOX0 - 8)) | 259 (1ull << (CVMX_IRQ_MBOX1 - 8))); 260#endif 261} 262 263static void 264octeon_memory_init(void) 265{ 266 vm_paddr_t phys_end; 267 int64_t addr; 268 unsigned i, j; 269 270 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 271 272 if (octeon_is_simulation()) { 273 /* Simulator we limit to 96 meg */ 274 phys_avail[0] = phys_end; 275 phys_avail[1] = 96 << 20; 276 277 dump_avail[0] = phys_avail[0]; 278 dump_avail[1] = phys_avail[1]; 279 280 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 281 return; 282 } 283 284 /* 285 * Allocate memory from bootmem 1MB at a time and merge 286 * adjacent entries. 287 */ 288 i = 0; 289 while (i < PHYS_AVAIL_ENTRIES) { 290 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 291 ~(vm_paddr_t)0, PAGE_SIZE, 0); 292 if (addr == -1) 293 break; 294 295 /* 296 * The SDK needs to be able to easily map any memory that might 297 * come to it e.g. in the form of an mbuf. Because on !n64 we 298 * can't direct-map some addresses and we don't want to manage 299 * temporary mappings within the SDK, don't feed memory that 300 * can't be direct-mapped to the kernel. 301 */ 302#if !defined(__mips_n64) 303 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 304 continue; 305#endif 306 307 physmem += btoc(1 << 20); 308 309 if (i > 0 && phys_avail[i - 1] == addr) { 310 phys_avail[i - 1] += 1 << 20; 311 continue; 312 } 313 314 phys_avail[i + 0] = addr; 315 phys_avail[i + 1] = addr + (1 << 20); 316 317 i += 2; 318 } 319 320 for (j = 0; j < i; j++) 321 dump_avail[j] = phys_avail[j]; 322 323 realmem = physmem; 324} 325 326void 327platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 328 __register_t a3) 329{ 330 const struct octeon_feature_description *ofd; 331 uint64_t platform_counter_freq; 332 333 /* 334 * XXX 335 * octeon_boot_params_init() should be called before anything else, 336 * certainly before any output; we may find out from the boot 337 * descriptor's flags that we're supposed to use the PCI or UART1 338 * consoles rather than UART0. No point doing that reorganization 339 * until we actually intercept UART_DEV_CONSOLE for the UART1 case 340 * and somehow handle the PCI console, which we lack code for 341 * entirely. 342 */ 343 344 /* Initialize pcpu stuff */ 345 mips_pcpu0_init(); 346 mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 347 cninit(); 348 349 octeon_ciu_reset(); 350 octeon_boot_params_init(a3); 351 /* 352 * XXX 353 * We can certainly parse command line arguments or U-Boot environment 354 * to determine whether to bootverbose / single user / ... I think 355 * stass has patches to add support for loader things to U-Boot even. 356 */ 357 bootverbose = 1; 358 359 /* 360 * For some reason on the cn38xx simulator ebase register is set to 361 * 0x80001000 at bootup time. Move it back to the default, but 362 * when we move to having support for multiple executives, we need 363 * to rethink this. 364 */ 365 mips_wr_ebase(0x80000000); 366 367 octeon_memory_init(); 368 init_param1(); 369 init_param2(physmem); 370 mips_cpu_init(); 371 pmap_bootstrap(); 372 mips_proc0_init(); 373 mutex_init(); 374 kdb_init(); 375#ifdef KDB 376 if (boothowto & RB_KDB) 377 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 378#endif 379 platform_counter_freq = cvmx_sysinfo_get()->cpu_clock_hz; 380 381 octeon_timecounter.tc_frequency = cvmx_sysinfo_get()->cpu_clock_hz; 382 platform_timecounter = &octeon_timecounter; 383 384 mips_timer_init_params(platform_counter_freq, 0); 385 386 set_cputicker(octeon_get_ticks, cvmx_sysinfo_get()->cpu_clock_hz, 0); 387 388#ifdef SMP 389 /* 390 * Clear any pending IPIs. 391 */ 392 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 393#endif 394 395 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 396 printf("Available Octeon features:"); 397 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 398 if (octeon_has_feature(ofd->ofd_feature)) 399 printf(" %s", ofd->ofd_string); 400 printf("\n"); 401} 402 403static uint64_t 404octeon_get_ticks(void) 405{ 406 uint64_t cvmcount; 407 408 CVMX_MF_CYCLE(cvmcount); 409 return (cvmcount); 410} 411 412static unsigned 413octeon_get_timecount(struct timecounter *tc) 414{ 415 return ((unsigned)octeon_get_ticks()); 416} 417 418/** 419 * version of printf that works better in exception context. 420 * 421 * @param format 422 * 423 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 424 */ 425void cvmx_safe_printf(const char *format, ...) 426{ 427 char buffer[256]; 428 char *ptr = buffer; 429 int count; 430 va_list args; 431 432 va_start(args, format); 433#ifndef __U_BOOT__ 434 count = vsnprintf(buffer, sizeof(buffer), format, args); 435#else 436 count = vsprintf(buffer, format, args); 437#endif 438 va_end(args); 439 440 while (count-- > 0) 441 { 442 cvmx_uart_lsr_t lsrval; 443 444 /* Spin until there is room */ 445 do 446 { 447 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 448#if !defined(CONFIG_OCTEON_SIM_SPEED) 449 if (lsrval.s.temt == 0) 450 cvmx_wait(10000); /* Just to reduce the load on the system */ 451#endif 452 } 453 while (lsrval.s.temt == 0); 454 455 if (*ptr == '\n') 456 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 457 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 458 } 459} 460 461/* impSTART: This stuff should move back into the Cavium SDK */ 462/* 463 **************************************************************************************** 464 * 465 * APP/BOOT DESCRIPTOR STUFF 466 * 467 **************************************************************************************** 468 */ 469 470/* Define the struct that is initialized by the bootloader used by the 471 * startup code. 472 * 473 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 474 * 475 * The authors hereby grant permission to use, copy, modify, distribute, 476 * and license this software and its documentation for any purpose, provided 477 * that existing copyright notices are retained in all copies and that this 478 * notice is included verbatim in any distributions. No written agreement, 479 * license, or royalty fee is required for any of the authorized uses. 480 * Modifications to this software may be copyrighted by their authors 481 * and need not follow the licensing terms described here, provided that 482 * the new terms are clearly indicated on the first page of each file where 483 * they apply. 484 */ 485 486#define OCTEON_CURRENT_DESC_VERSION 6 487#define OCTEON_ARGV_MAX_ARGS (64) 488#define OCTOEN_SERIAL_LEN 20 489 490typedef struct { 491 /* Start of block referenced by assembly code - do not change! */ 492 uint32_t desc_version; 493 uint32_t desc_size; 494 495 uint64_t stack_top; 496 uint64_t heap_base; 497 uint64_t heap_end; 498 uint64_t entry_point; /* Only used by bootloader */ 499 uint64_t desc_vaddr; 500 /* End of This block referenced by assembly code - do not change! */ 501 502 uint32_t exception_base_addr; 503 uint32_t stack_size; 504 uint32_t heap_size; 505 uint32_t argc; /* Argc count for application */ 506 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 507 uint32_t flags; 508 uint32_t core_mask; 509 uint32_t dram_size; /**< DRAM size in megabyes */ 510 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 511 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 512 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 513 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 514 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 515 uint16_t board_type; 516 uint8_t board_rev_major; 517 uint8_t board_rev_minor; 518 uint16_t chip_type; 519 uint8_t chip_rev_major; 520 uint8_t chip_rev_minor; 521 char board_serial_number[OCTOEN_SERIAL_LEN]; 522 uint8_t mac_addr_base[6]; 523 uint8_t mac_addr_count; 524 uint64_t cvmx_desc_vaddr; 525} octeon_boot_descriptor_t; 526 527cvmx_bootinfo_t *octeon_bootinfo; 528 529static octeon_boot_descriptor_t *app_desc_ptr; 530 531int 532octeon_is_simulation(void) 533{ 534 switch (cvmx_sysinfo_get()->board_type) { 535 case CVMX_BOARD_TYPE_SIM: 536 return 1; 537 default: 538 return 0; 539 } 540} 541 542static void 543octeon_process_app_desc_ver_6(void) 544{ 545 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 546 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 547 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 548 panic("Bad octeon_bootinfo %p", octeon_bootinfo); 549 550 octeon_bootinfo = 551 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 552 octeon_bootinfo = 553 (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 554 if (octeon_bootinfo->major_version != 1) 555 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 556 (int) octeon_bootinfo->major_version, 557 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 558 559 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 560 octeon_bootinfo->board_type, 561 octeon_bootinfo->board_rev_major, 562 octeon_bootinfo->board_rev_minor, 563 octeon_bootinfo->eclock_hz); 564} 565 566static void 567octeon_boot_params_init(register_t ptr) 568{ 569 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 570 panic("app descriptor passed at invalid address %#jx", 571 (uintmax_t)ptr); 572 573 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 574 if (app_desc_ptr->desc_version < 6) 575 panic("Your boot code is too old to be supported."); 576 octeon_process_app_desc_ver_6(); 577 578 KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 579 580 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 581 panic("Your boot loader did not supply a memory descriptor."); 582 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 583 584 printf("Boot Descriptor Ver: %u -> %u/%u", 585 app_desc_ptr->desc_version, octeon_bootinfo->major_version, 586 octeon_bootinfo->minor_version); 587 printf(" CPU clock: %uMHz Core Mask: %#x\n", 588 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 589 cvmx_sysinfo_get()->core_mask); 590 printf(" Board Type: %u Revision: %u/%u\n", 591 cvmx_sysinfo_get()->board_type, 592 cvmx_sysinfo_get()->board_rev_major, 593 cvmx_sysinfo_get()->board_rev_minor); 594 595 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 596 octeon_bootinfo->mac_addr_base[0], 597 octeon_bootinfo->mac_addr_base[1], 598 octeon_bootinfo->mac_addr_base[2], 599 octeon_bootinfo->mac_addr_base[3], 600 octeon_bootinfo->mac_addr_base[4], 601 octeon_bootinfo->mac_addr_base[5], 602 octeon_bootinfo->mac_addr_count); 603 604#if defined(OCTEON_BOARD_CAPK_0100ND) 605 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) 606 printf("Compiled for CAPK-0100ND, but board type is %s\n", 607 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 608#else 609 printf("Board: %s\n", 610 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 611#endif 612 printf("Model: %s\n", octeon_model_get_string(cvmx_get_proc_id())); 613} 614/* impEND: This stuff should move back into the Cavium SDK */ 615