if_arge.c revision 228064
1188808Sgonzo/*- 2188808Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko 3188808Sgonzo * All rights reserved. 4188808Sgonzo * 5188808Sgonzo * Redistribution and use in source and binary forms, with or without 6188808Sgonzo * modification, are permitted provided that the following conditions 7188808Sgonzo * are met: 8188808Sgonzo * 1. Redistributions of source code must retain the above copyright 9188808Sgonzo * notice unmodified, this list of conditions, and the following 10188808Sgonzo * disclaimer. 11188808Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12188808Sgonzo * notice, this list of conditions and the following disclaimer in the 13188808Sgonzo * documentation and/or other materials provided with the distribution. 14188808Sgonzo * 15188808Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16188808Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17188808Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18188808Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19188808Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20188808Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21188808Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22188808Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23188808Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24188808Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25188808Sgonzo * SUCH DAMAGE. 26188808Sgonzo */ 27188808Sgonzo 28188808Sgonzo#include <sys/cdefs.h> 29188808Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/if_arge.c 228064 2011-11-28 13:42:59Z ray $"); 30188808Sgonzo 31188808Sgonzo/* 32188808Sgonzo * AR71XX gigabit ethernet driver 33188808Sgonzo */ 34192783Sgonzo#ifdef HAVE_KERNEL_OPTION_HEADERS 35192783Sgonzo#include "opt_device_polling.h" 36192783Sgonzo#endif 37192783Sgonzo 38188808Sgonzo#include <sys/param.h> 39188808Sgonzo#include <sys/endian.h> 40188808Sgonzo#include <sys/systm.h> 41188808Sgonzo#include <sys/sockio.h> 42188808Sgonzo#include <sys/mbuf.h> 43188808Sgonzo#include <sys/malloc.h> 44188808Sgonzo#include <sys/kernel.h> 45188808Sgonzo#include <sys/module.h> 46188808Sgonzo#include <sys/socket.h> 47188808Sgonzo#include <sys/taskqueue.h> 48209802Sadrian#include <sys/sysctl.h> 49188808Sgonzo 50188808Sgonzo#include <net/if.h> 51188808Sgonzo#include <net/if_arp.h> 52188808Sgonzo#include <net/ethernet.h> 53188808Sgonzo#include <net/if_dl.h> 54188808Sgonzo#include <net/if_media.h> 55188808Sgonzo#include <net/if_types.h> 56188808Sgonzo 57188808Sgonzo#include <net/bpf.h> 58188808Sgonzo 59188808Sgonzo#include <machine/bus.h> 60188808Sgonzo#include <machine/cache.h> 61188808Sgonzo#include <machine/resource.h> 62188808Sgonzo#include <vm/vm_param.h> 63188808Sgonzo#include <vm/vm.h> 64188808Sgonzo#include <vm/pmap.h> 65188808Sgonzo#include <machine/pmap.h> 66188808Sgonzo#include <sys/bus.h> 67188808Sgonzo#include <sys/rman.h> 68188808Sgonzo 69188808Sgonzo#include <dev/mii/mii.h> 70188808Sgonzo#include <dev/mii/miivar.h> 71188808Sgonzo 72188808Sgonzo#include <dev/pci/pcireg.h> 73188808Sgonzo#include <dev/pci/pcivar.h> 74188808Sgonzo 75188808SgonzoMODULE_DEPEND(arge, ether, 1, 1, 1); 76188808SgonzoMODULE_DEPEND(arge, miibus, 1, 1, 1); 77188808Sgonzo 78188808Sgonzo#include "miibus_if.h" 79188808Sgonzo 80188808Sgonzo#include <mips/atheros/ar71xxreg.h> 81188808Sgonzo#include <mips/atheros/if_argevar.h> 82219589Sadrian#include <mips/atheros/ar71xx_setup.h> 83211477Sadrian#include <mips/atheros/ar71xx_cpudef.h> 84188808Sgonzo 85220354Sadriantypedef enum { 86220354Sadrian ARGE_DBG_MII = 0x00000001, 87220356Sadrian ARGE_DBG_INTR = 0x00000002, 88220356Sadrian ARGE_DBG_TX = 0x00000004, 89220356Sadrian ARGE_DBG_RX = 0x00000008, 90220356Sadrian ARGE_DBG_ERR = 0x00000010, 91220356Sadrian ARGE_DBG_RESET = 0x00000020, 92220354Sadrian} arge_debug_flags; 93220354Sadrian 94188808Sgonzo#ifdef ARGE_DEBUG 95220354Sadrian#define ARGEDEBUG(_sc, _m, ...) \ 96220354Sadrian do { \ 97220354Sadrian if ((_m) & (_sc)->arge_debug) \ 98220354Sadrian device_printf((_sc)->arge_dev, __VA_ARGS__); \ 99220354Sadrian } while (0) 100188808Sgonzo#else 101220354Sadrian#define ARGEDEBUG(_sc, _m, ...) 102188808Sgonzo#endif 103188808Sgonzo 104188808Sgonzostatic int arge_attach(device_t); 105188808Sgonzostatic int arge_detach(device_t); 106188808Sgonzostatic void arge_flush_ddr(struct arge_softc *); 107188808Sgonzostatic int arge_ifmedia_upd(struct ifnet *); 108188808Sgonzostatic void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109188808Sgonzostatic int arge_ioctl(struct ifnet *, u_long, caddr_t); 110188808Sgonzostatic void arge_init(void *); 111188808Sgonzostatic void arge_init_locked(struct arge_softc *); 112188808Sgonzostatic void arge_link_task(void *, int); 113199234Sgonzostatic void arge_set_pll(struct arge_softc *, int, int); 114188808Sgonzostatic int arge_miibus_readreg(device_t, int, int); 115188808Sgonzostatic void arge_miibus_statchg(device_t); 116188808Sgonzostatic int arge_miibus_writereg(device_t, int, int, int); 117188808Sgonzostatic int arge_probe(device_t); 118188808Sgonzostatic void arge_reset_dma(struct arge_softc *); 119188808Sgonzostatic int arge_resume(device_t); 120188808Sgonzostatic int arge_rx_ring_init(struct arge_softc *); 121188808Sgonzostatic int arge_tx_ring_init(struct arge_softc *); 122192821Sgonzo#ifdef DEVICE_POLLING 123198667Sgonzostatic int arge_poll(struct ifnet *, enum poll_cmd, int); 124192821Sgonzo#endif 125194059Sgonzostatic int arge_shutdown(device_t); 126188808Sgonzostatic void arge_start(struct ifnet *); 127188808Sgonzostatic void arge_start_locked(struct ifnet *); 128188808Sgonzostatic void arge_stop(struct arge_softc *); 129188808Sgonzostatic int arge_suspend(device_t); 130188808Sgonzo 131198667Sgonzostatic int arge_rx_locked(struct arge_softc *); 132188808Sgonzostatic void arge_tx_locked(struct arge_softc *); 133188808Sgonzostatic void arge_intr(void *); 134188808Sgonzostatic int arge_intr_filter(void *); 135188808Sgonzostatic void arge_tick(void *); 136188808Sgonzo 137199234Sgonzo/* 138199234Sgonzo * ifmedia callbacks for multiPHY MAC 139199234Sgonzo */ 140199234Sgonzovoid arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *); 141199234Sgonzoint arge_multiphy_mediachange(struct ifnet *); 142199234Sgonzo 143188808Sgonzostatic void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 144188808Sgonzostatic int arge_dma_alloc(struct arge_softc *); 145188808Sgonzostatic void arge_dma_free(struct arge_softc *); 146188808Sgonzostatic int arge_newbuf(struct arge_softc *, int); 147188808Sgonzostatic __inline void arge_fixup_rx(struct mbuf *); 148188808Sgonzo 149188808Sgonzostatic device_method_t arge_methods[] = { 150188808Sgonzo /* Device interface */ 151188808Sgonzo DEVMETHOD(device_probe, arge_probe), 152188808Sgonzo DEVMETHOD(device_attach, arge_attach), 153188808Sgonzo DEVMETHOD(device_detach, arge_detach), 154188808Sgonzo DEVMETHOD(device_suspend, arge_suspend), 155188808Sgonzo DEVMETHOD(device_resume, arge_resume), 156188808Sgonzo DEVMETHOD(device_shutdown, arge_shutdown), 157188808Sgonzo 158188808Sgonzo /* MII interface */ 159188808Sgonzo DEVMETHOD(miibus_readreg, arge_miibus_readreg), 160188808Sgonzo DEVMETHOD(miibus_writereg, arge_miibus_writereg), 161188808Sgonzo DEVMETHOD(miibus_statchg, arge_miibus_statchg), 162188808Sgonzo 163227843Smarius DEVMETHOD_END 164188808Sgonzo}; 165188808Sgonzo 166188808Sgonzostatic driver_t arge_driver = { 167188808Sgonzo "arge", 168188808Sgonzo arge_methods, 169188808Sgonzo sizeof(struct arge_softc) 170188808Sgonzo}; 171188808Sgonzo 172188808Sgonzostatic devclass_t arge_devclass; 173188808Sgonzo 174188808SgonzoDRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0); 175188808SgonzoDRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0); 176188808Sgonzo 177188808Sgonzo/* 178192179Sgonzo * RedBoot passes MAC address to entry point as environment 179192179Sgonzo * variable. platfrom_start parses it and stores in this variable 180192179Sgonzo */ 181192179Sgonzoextern uint32_t ar711_base_mac[ETHER_ADDR_LEN]; 182192179Sgonzo 183199038Sgonzostatic struct mtx miibus_mtx; 184199038Sgonzo 185206400SgonzoMTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF); 186199038Sgonzo 187199038Sgonzo 188192179Sgonzo/* 189188808Sgonzo * Flushes all 190188808Sgonzo */ 191188808Sgonzostatic void 192188808Sgonzoarge_flush_ddr(struct arge_softc *sc) 193188808Sgonzo{ 194228064Sray 195228064Sray ar71xx_device_flush_ddr_ge(sc->arge_mac_unit); 196188808Sgonzo} 197188808Sgonzo 198188808Sgonzostatic int 199188808Sgonzoarge_probe(device_t dev) 200188808Sgonzo{ 201188808Sgonzo 202188808Sgonzo device_set_desc(dev, "Atheros AR71xx built-in ethernet interface"); 203188808Sgonzo return (0); 204188808Sgonzo} 205188808Sgonzo 206209802Sadrianstatic void 207209802Sadrianarge_attach_sysctl(device_t dev) 208209802Sadrian{ 209209802Sadrian struct arge_softc *sc = device_get_softc(dev); 210209802Sadrian struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 211209802Sadrian struct sysctl_oid *tree = device_get_sysctl_tree(dev); 212209802Sadrian 213220355Sadrian#ifdef ARGE_DEBUG 214209802Sadrian SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 215209802Sadrian "debug", CTLFLAG_RW, &sc->arge_debug, 0, 216209802Sadrian "arge interface debugging flags"); 217220355Sadrian#endif 218209809Sadrian 219209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 220209809Sadrian "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0, 221209809Sadrian "number of TX aligned packets"); 222209809Sadrian 223209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 224209809Sadrian "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 0, 225209809Sadrian "number of TX unaligned packets"); 226220354Sadrian 227220355Sadrian#ifdef ARGE_DEBUG 228220355Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod", 229220355Sadrian CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, ""); 230220355Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons", 231220355Sadrian CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, ""); 232220355Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt", 233220355Sadrian CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, ""); 234220355Sadrian#endif 235209802Sadrian} 236209802Sadrian 237188808Sgonzostatic int 238188808Sgonzoarge_attach(device_t dev) 239188808Sgonzo{ 240188808Sgonzo uint8_t eaddr[ETHER_ADDR_LEN]; 241188808Sgonzo struct ifnet *ifp; 242188808Sgonzo struct arge_softc *sc; 243199234Sgonzo int error = 0, rid, phymask; 244192179Sgonzo uint32_t reg, rnd; 245199234Sgonzo int is_base_mac_empty, i, phys_total; 246199234Sgonzo uint32_t hint; 247220260Sadrian long eeprom_mac_addr = 0; 248188808Sgonzo 249188808Sgonzo sc = device_get_softc(dev); 250188808Sgonzo sc->arge_dev = dev; 251188808Sgonzo sc->arge_mac_unit = device_get_unit(dev); 252188808Sgonzo 253220260Sadrian /* 254220260Sadrian * Some units (eg the TP-Link WR-1043ND) do not have a convenient 255220260Sadrian * EEPROM location to read the ethernet MAC address from. 256220260Sadrian * OpenWRT simply snaffles it from a fixed location. 257220260Sadrian * 258220260Sadrian * Since multiple units seem to use this feature, include 259220260Sadrian * a method of setting the MAC address based on an flash location 260220260Sadrian * in CPU address space. 261220260Sadrian */ 262220260Sadrian if (sc->arge_mac_unit == 0 && 263220260Sadrian resource_long_value(device_get_name(dev), device_get_unit(dev), 264220260Sadrian "eeprommac", &eeprom_mac_addr) == 0) { 265220260Sadrian int i; 266220260Sadrian const char *mac = (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr); 267220260Sadrian device_printf(dev, "Overriding MAC from EEPROM\n"); 268220260Sadrian for (i = 0; i < 6; i++) { 269220260Sadrian ar711_base_mac[i] = mac[i]; 270220260Sadrian } 271220260Sadrian } 272220260Sadrian 273188808Sgonzo KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 274188808Sgonzo ("if_arge: Only MAC0 and MAC1 supported")); 275188808Sgonzo 276188808Sgonzo /* 277188808Sgonzo * Get which PHY of 5 available we should use for this unit 278188808Sgonzo */ 279188808Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 280199234Sgonzo "phymask", &phymask) != 0) { 281188808Sgonzo /* 282188808Sgonzo * Use port 4 (WAN) for GE0. For any other port use 283188808Sgonzo * its PHY the same as its unit number 284188808Sgonzo */ 285188808Sgonzo if (sc->arge_mac_unit == 0) 286199234Sgonzo phymask = (1 << 4); 287188808Sgonzo else 288199234Sgonzo /* Use all phys up to 4 */ 289199234Sgonzo phymask = (1 << 4) - 1; 290188808Sgonzo 291199234Sgonzo device_printf(dev, "No PHY specified, using mask %d\n", phymask); 292188808Sgonzo } 293188808Sgonzo 294199234Sgonzo /* 295199234Sgonzo * Get default media & duplex mode, by default its Base100T 296199234Sgonzo * and full duplex 297199234Sgonzo */ 298199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 299199234Sgonzo "media", &hint) != 0) 300199234Sgonzo hint = 0; 301188808Sgonzo 302199234Sgonzo if (hint == 1000) 303199234Sgonzo sc->arge_media_type = IFM_1000_T; 304199234Sgonzo else 305199234Sgonzo sc->arge_media_type = IFM_100_TX; 306199234Sgonzo 307199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 308199234Sgonzo "fduplex", &hint) != 0) 309199234Sgonzo hint = 1; 310199234Sgonzo 311199234Sgonzo if (hint) 312199234Sgonzo sc->arge_duplex_mode = IFM_FDX; 313199234Sgonzo else 314199234Sgonzo sc->arge_duplex_mode = 0; 315199234Sgonzo 316199234Sgonzo sc->arge_phymask = phymask; 317199234Sgonzo 318188808Sgonzo mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 319188808Sgonzo MTX_DEF); 320188808Sgonzo callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0); 321188808Sgonzo TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc); 322188808Sgonzo 323188808Sgonzo /* Map control/status registers. */ 324188808Sgonzo sc->arge_rid = 0; 325188808Sgonzo sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 326188808Sgonzo &sc->arge_rid, RF_ACTIVE); 327188808Sgonzo 328188808Sgonzo if (sc->arge_res == NULL) { 329188808Sgonzo device_printf(dev, "couldn't map memory\n"); 330188808Sgonzo error = ENXIO; 331188808Sgonzo goto fail; 332188808Sgonzo } 333188808Sgonzo 334188808Sgonzo /* Allocate interrupts */ 335188808Sgonzo rid = 0; 336188808Sgonzo sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 337188808Sgonzo RF_SHAREABLE | RF_ACTIVE); 338188808Sgonzo 339188808Sgonzo if (sc->arge_irq == NULL) { 340188808Sgonzo device_printf(dev, "couldn't map interrupt\n"); 341188808Sgonzo error = ENXIO; 342188808Sgonzo goto fail; 343188808Sgonzo } 344188808Sgonzo 345188808Sgonzo /* Allocate ifnet structure. */ 346188808Sgonzo ifp = sc->arge_ifp = if_alloc(IFT_ETHER); 347188808Sgonzo 348188808Sgonzo if (ifp == NULL) { 349188808Sgonzo device_printf(dev, "couldn't allocate ifnet structure\n"); 350188808Sgonzo error = ENOSPC; 351188808Sgonzo goto fail; 352188808Sgonzo } 353188808Sgonzo 354188808Sgonzo ifp->if_softc = sc; 355188808Sgonzo if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 356188808Sgonzo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 357188808Sgonzo ifp->if_ioctl = arge_ioctl; 358188808Sgonzo ifp->if_start = arge_start; 359188808Sgonzo ifp->if_init = arge_init; 360198932Sgonzo sc->arge_if_flags = ifp->if_flags; 361188808Sgonzo 362188808Sgonzo /* XXX: add real size */ 363207554Ssobomax IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 364207554Ssobomax ifp->if_snd.ifq_maxlen = ifqmaxlen; 365188808Sgonzo IFQ_SET_READY(&ifp->if_snd); 366188808Sgonzo 367188808Sgonzo ifp->if_capenable = ifp->if_capabilities; 368192783Sgonzo#ifdef DEVICE_POLLING 369192783Sgonzo ifp->if_capabilities |= IFCAP_POLLING; 370192783Sgonzo#endif 371188808Sgonzo 372192179Sgonzo is_base_mac_empty = 1; 373192179Sgonzo for (i = 0; i < ETHER_ADDR_LEN; i++) { 374192179Sgonzo eaddr[i] = ar711_base_mac[i] & 0xff; 375192179Sgonzo if (eaddr[i] != 0) 376192179Sgonzo is_base_mac_empty = 0; 377192179Sgonzo } 378188808Sgonzo 379192179Sgonzo if (is_base_mac_empty) { 380192179Sgonzo /* 381192179Sgonzo * No MAC address configured. Generate the random one. 382192179Sgonzo */ 383198933Sgonzo if (bootverbose) 384192179Sgonzo device_printf(dev, 385192179Sgonzo "Generating random ethernet address.\n"); 386192179Sgonzo 387192179Sgonzo rnd = arc4random(); 388192179Sgonzo eaddr[0] = 'b'; 389192179Sgonzo eaddr[1] = 's'; 390192179Sgonzo eaddr[2] = 'd'; 391192179Sgonzo eaddr[3] = (rnd >> 24) & 0xff; 392192179Sgonzo eaddr[4] = (rnd >> 16) & 0xff; 393192179Sgonzo eaddr[5] = (rnd >> 8) & 0xff; 394192179Sgonzo } 395192179Sgonzo 396198970Sgonzo if (sc->arge_mac_unit != 0) 397198970Sgonzo eaddr[5] += sc->arge_mac_unit; 398198970Sgonzo 399188808Sgonzo if (arge_dma_alloc(sc) != 0) { 400188808Sgonzo error = ENXIO; 401188808Sgonzo goto fail; 402188808Sgonzo } 403188808Sgonzo 404192569Sdwhite /* Initialize the MAC block */ 405192569Sdwhite 406192569Sdwhite /* Step 1. Soft-reset MAC */ 407192569Sdwhite ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET); 408192569Sdwhite DELAY(20); 409192569Sdwhite 410192569Sdwhite /* Step 2. Punt the MAC core from the central reset register */ 411211477Sadrian ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 412192569Sdwhite DELAY(100); 413211477Sadrian ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 414192569Sdwhite 415192569Sdwhite /* Step 3. Reconfigure MAC block */ 416188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG1, 417188808Sgonzo MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE | 418188808Sgonzo MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE); 419188808Sgonzo 420188808Sgonzo reg = ARGE_READ(sc, AR71XX_MAC_CFG2); 421188808Sgonzo reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ; 422188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg); 423188808Sgonzo 424188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536); 425188808Sgonzo 426188808Sgonzo /* Reset MII bus */ 427188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET); 428188808Sgonzo DELAY(100); 429188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28); 430188808Sgonzo DELAY(100); 431188808Sgonzo 432188808Sgonzo /* 433188808Sgonzo * Set all Ethernet address registers to the same initial values 434188808Sgonzo * set all four addresses to 66-88-aa-cc-dd-ee 435188808Sgonzo */ 436192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 437192783Sgonzo (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]); 438192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]); 439188808Sgonzo 440188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 441188808Sgonzo FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT); 442188808Sgonzo 443219589Sadrian switch (ar71xx_soc) { 444219589Sadrian case AR71XX_SOC_AR7240: 445219589Sadrian case AR71XX_SOC_AR7241: 446219589Sadrian case AR71XX_SOC_AR7242: 447219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff); 448219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa); 449219589Sadrian break; 450219589Sadrian default: 451219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000); 452219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff); 453219589Sadrian } 454219589Sadrian 455192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 456192783Sgonzo FIFO_RX_FILTMATCH_DEFAULT); 457188808Sgonzo 458192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 459192783Sgonzo FIFO_RX_FILTMASK_DEFAULT); 460188808Sgonzo 461199234Sgonzo /* 462199234Sgonzo * Check if we have single-PHY MAC or multi-PHY 463199234Sgonzo */ 464199234Sgonzo phys_total = 0; 465199234Sgonzo for (i = 0; i < ARGE_NPHY; i++) 466199234Sgonzo if (phymask & (1 << i)) 467199234Sgonzo phys_total ++; 468199234Sgonzo 469199234Sgonzo if (phys_total == 0) { 470199234Sgonzo error = EINVAL; 471188808Sgonzo goto fail; 472188808Sgonzo } 473188808Sgonzo 474199234Sgonzo if (phys_total == 1) { 475199234Sgonzo /* Do MII setup. */ 476213894Smarius error = mii_attach(dev, &sc->arge_miibus, ifp, 477213894Smarius arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK, 478213894Smarius MII_PHY_ANY, MII_OFFSET_ANY, 0); 479213894Smarius if (error != 0) { 480213894Smarius device_printf(dev, "attaching PHYs failed\n"); 481199234Sgonzo goto fail; 482199234Sgonzo } 483199234Sgonzo } 484199234Sgonzo else { 485199234Sgonzo ifmedia_init(&sc->arge_ifmedia, 0, 486199234Sgonzo arge_multiphy_mediachange, 487199234Sgonzo arge_multiphy_mediastatus); 488199234Sgonzo ifmedia_add(&sc->arge_ifmedia, 489199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode, 490199234Sgonzo 0, NULL); 491199234Sgonzo ifmedia_set(&sc->arge_ifmedia, 492199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode); 493199234Sgonzo arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode); 494199234Sgonzo } 495199234Sgonzo 496188808Sgonzo /* Call MI attach routine. */ 497188808Sgonzo ether_ifattach(ifp, eaddr); 498188808Sgonzo 499188808Sgonzo /* Hook interrupt last to avoid having to lock softc */ 500188808Sgonzo error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE, 501188808Sgonzo arge_intr_filter, arge_intr, sc, &sc->arge_intrhand); 502188808Sgonzo 503188808Sgonzo if (error) { 504188808Sgonzo device_printf(dev, "couldn't set up irq\n"); 505188808Sgonzo ether_ifdetach(ifp); 506188808Sgonzo goto fail; 507188808Sgonzo } 508188808Sgonzo 509209802Sadrian /* setup sysctl variables */ 510209802Sadrian arge_attach_sysctl(dev); 511209802Sadrian 512188808Sgonzofail: 513188808Sgonzo if (error) 514188808Sgonzo arge_detach(dev); 515188808Sgonzo 516188808Sgonzo return (error); 517188808Sgonzo} 518188808Sgonzo 519188808Sgonzostatic int 520188808Sgonzoarge_detach(device_t dev) 521188808Sgonzo{ 522192783Sgonzo struct arge_softc *sc = device_get_softc(dev); 523188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 524188808Sgonzo 525188808Sgonzo KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized")); 526188808Sgonzo 527188808Sgonzo /* These should only be active if attach succeeded */ 528188808Sgonzo if (device_is_attached(dev)) { 529188808Sgonzo ARGE_LOCK(sc); 530188808Sgonzo sc->arge_detach = 1; 531192783Sgonzo#ifdef DEVICE_POLLING 532192783Sgonzo if (ifp->if_capenable & IFCAP_POLLING) 533192783Sgonzo ether_poll_deregister(ifp); 534192783Sgonzo#endif 535192783Sgonzo 536188808Sgonzo arge_stop(sc); 537188808Sgonzo ARGE_UNLOCK(sc); 538188808Sgonzo taskqueue_drain(taskqueue_swi, &sc->arge_link_task); 539188808Sgonzo ether_ifdetach(ifp); 540188808Sgonzo } 541188808Sgonzo 542188808Sgonzo if (sc->arge_miibus) 543188808Sgonzo device_delete_child(dev, sc->arge_miibus); 544199234Sgonzo 545188808Sgonzo bus_generic_detach(dev); 546188808Sgonzo 547188808Sgonzo if (sc->arge_intrhand) 548188808Sgonzo bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand); 549188808Sgonzo 550188808Sgonzo if (sc->arge_res) 551188808Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 552188808Sgonzo sc->arge_res); 553188808Sgonzo 554188808Sgonzo if (ifp) 555188808Sgonzo if_free(ifp); 556188808Sgonzo 557188808Sgonzo arge_dma_free(sc); 558188808Sgonzo 559188808Sgonzo mtx_destroy(&sc->arge_mtx); 560188808Sgonzo 561188808Sgonzo return (0); 562188808Sgonzo 563188808Sgonzo} 564188808Sgonzo 565188808Sgonzostatic int 566188808Sgonzoarge_suspend(device_t dev) 567188808Sgonzo{ 568188808Sgonzo 569188808Sgonzo panic("%s", __func__); 570188808Sgonzo return 0; 571188808Sgonzo} 572188808Sgonzo 573188808Sgonzostatic int 574188808Sgonzoarge_resume(device_t dev) 575188808Sgonzo{ 576188808Sgonzo 577188808Sgonzo panic("%s", __func__); 578188808Sgonzo return 0; 579188808Sgonzo} 580188808Sgonzo 581194059Sgonzostatic int 582188808Sgonzoarge_shutdown(device_t dev) 583188808Sgonzo{ 584188808Sgonzo struct arge_softc *sc; 585188808Sgonzo 586188808Sgonzo sc = device_get_softc(dev); 587188808Sgonzo 588188808Sgonzo ARGE_LOCK(sc); 589188808Sgonzo arge_stop(sc); 590188808Sgonzo ARGE_UNLOCK(sc); 591194059Sgonzo 592194059Sgonzo return (0); 593188808Sgonzo} 594188808Sgonzo 595188808Sgonzostatic int 596188808Sgonzoarge_miibus_readreg(device_t dev, int phy, int reg) 597188808Sgonzo{ 598188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 599188808Sgonzo int i, result; 600196794Sgonzo uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 601188808Sgonzo | (reg & MAC_MII_REG_MASK); 602188808Sgonzo 603199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 604188808Sgonzo return (0); 605188808Sgonzo 606199038Sgonzo mtx_lock(&miibus_mtx); 607199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 608199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 609199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); 610188808Sgonzo 611188808Sgonzo i = ARGE_MII_TIMEOUT; 612199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 613188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 614188808Sgonzo DELAY(5); 615188808Sgonzo 616188808Sgonzo if (i < 0) { 617199038Sgonzo mtx_unlock(&miibus_mtx); 618220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 619188808Sgonzo /* XXX: return ERRNO istead? */ 620188808Sgonzo return (-1); 621188808Sgonzo } 622188808Sgonzo 623199038Sgonzo result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; 624199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 625199038Sgonzo mtx_unlock(&miibus_mtx); 626199038Sgonzo 627220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 628188808Sgonzo phy, reg, addr, result); 629188808Sgonzo 630188808Sgonzo return (result); 631188808Sgonzo} 632188808Sgonzo 633188808Sgonzostatic int 634188808Sgonzoarge_miibus_writereg(device_t dev, int phy, int reg, int data) 635188808Sgonzo{ 636188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 637188808Sgonzo int i; 638196794Sgonzo uint32_t addr = 639196794Sgonzo (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK); 640188808Sgonzo 641199038Sgonzo 642199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 643199038Sgonzo return (-1); 644199038Sgonzo 645220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__, 646188808Sgonzo phy, reg, data); 647188808Sgonzo 648199038Sgonzo mtx_lock(&miibus_mtx); 649199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 650199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data); 651188808Sgonzo 652188808Sgonzo i = ARGE_MII_TIMEOUT; 653199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 654188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 655188808Sgonzo DELAY(5); 656188808Sgonzo 657199038Sgonzo mtx_unlock(&miibus_mtx); 658199038Sgonzo 659188808Sgonzo if (i < 0) { 660220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 661188808Sgonzo /* XXX: return ERRNO istead? */ 662188808Sgonzo return (-1); 663188808Sgonzo } 664188808Sgonzo 665188808Sgonzo return (0); 666188808Sgonzo} 667188808Sgonzo 668188808Sgonzostatic void 669188808Sgonzoarge_miibus_statchg(device_t dev) 670188808Sgonzo{ 671188808Sgonzo struct arge_softc *sc; 672188808Sgonzo 673188808Sgonzo sc = device_get_softc(dev); 674188808Sgonzo taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task); 675188808Sgonzo} 676188808Sgonzo 677188808Sgonzostatic void 678188808Sgonzoarge_link_task(void *arg, int pending) 679188808Sgonzo{ 680188808Sgonzo struct arge_softc *sc; 681188808Sgonzo struct mii_data *mii; 682188808Sgonzo struct ifnet *ifp; 683199234Sgonzo uint32_t media, duplex; 684188808Sgonzo 685188808Sgonzo sc = (struct arge_softc *)arg; 686188808Sgonzo 687188808Sgonzo ARGE_LOCK(sc); 688188808Sgonzo mii = device_get_softc(sc->arge_miibus); 689188808Sgonzo ifp = sc->arge_ifp; 690188808Sgonzo if (mii == NULL || ifp == NULL || 691188808Sgonzo (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 692188808Sgonzo ARGE_UNLOCK(sc); 693188808Sgonzo return; 694188808Sgonzo } 695188808Sgonzo 696188808Sgonzo if (mii->mii_media_status & IFM_ACTIVE) { 697188808Sgonzo 698188808Sgonzo media = IFM_SUBTYPE(mii->mii_media_active); 699188808Sgonzo 700188808Sgonzo if (media != IFM_NONE) { 701188808Sgonzo sc->arge_link_status = 1; 702199234Sgonzo duplex = mii->mii_media_active & IFM_GMASK; 703199234Sgonzo arge_set_pll(sc, media, duplex); 704199234Sgonzo } 705199234Sgonzo } else 706199234Sgonzo sc->arge_link_status = 0; 707188808Sgonzo 708199234Sgonzo ARGE_UNLOCK(sc); 709199234Sgonzo} 710192783Sgonzo 711199234Sgonzostatic void 712199234Sgonzoarge_set_pll(struct arge_softc *sc, int media, int duplex) 713199234Sgonzo{ 714211511Sadrian uint32_t cfg, ifcontrol, rx_filtmask; 715219589Sadrian uint32_t fifo_tx; 716211511Sadrian int if_speed; 717192783Sgonzo 718199234Sgonzo cfg = ARGE_READ(sc, AR71XX_MAC_CFG2); 719199234Sgonzo cfg &= ~(MAC_CFG2_IFACE_MODE_1000 720199234Sgonzo | MAC_CFG2_IFACE_MODE_10_100 721199234Sgonzo | MAC_CFG2_FULL_DUPLEX); 722188808Sgonzo 723199234Sgonzo if (duplex == IFM_FDX) 724199234Sgonzo cfg |= MAC_CFG2_FULL_DUPLEX; 725188808Sgonzo 726199234Sgonzo ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL); 727199234Sgonzo ifcontrol &= ~MAC_IFCONTROL_SPEED; 728199234Sgonzo rx_filtmask = 729199234Sgonzo ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK); 730199234Sgonzo rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE; 731188808Sgonzo 732199234Sgonzo switch(media) { 733199234Sgonzo case IFM_10_T: 734199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 735211511Sadrian if_speed = 10; 736199234Sgonzo break; 737199234Sgonzo case IFM_100_TX: 738199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 739199234Sgonzo ifcontrol |= MAC_IFCONTROL_SPEED; 740211511Sadrian if_speed = 100; 741199234Sgonzo break; 742199234Sgonzo case IFM_1000_T: 743199234Sgonzo case IFM_1000_SX: 744199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_1000; 745199234Sgonzo rx_filtmask |= FIFO_RX_MASK_BYTE_MODE; 746211511Sadrian if_speed = 1000; 747199234Sgonzo break; 748199234Sgonzo default: 749211511Sadrian if_speed = 100; 750199234Sgonzo device_printf(sc->arge_dev, 751199234Sgonzo "Unknown media %d\n", media); 752199234Sgonzo } 753188808Sgonzo 754219589Sadrian switch (ar71xx_soc) { 755219589Sadrian case AR71XX_SOC_AR7240: 756219589Sadrian case AR71XX_SOC_AR7241: 757219589Sadrian case AR71XX_SOC_AR7242: 758219589Sadrian fifo_tx = 0x01f00140; 759219589Sadrian break; 760219589Sadrian case AR71XX_SOC_AR9130: 761219589Sadrian case AR71XX_SOC_AR9132: 762219589Sadrian fifo_tx = 0x00780fff; 763219589Sadrian break; 764219589Sadrian default: 765219589Sadrian fifo_tx = 0x008001ff; 766219589Sadrian } 767188808Sgonzo 768199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg); 769199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol); 770199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 771199234Sgonzo rx_filtmask); 772219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx); 773188808Sgonzo 774199234Sgonzo /* set PLL registers */ 775228018Sray ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed); 776188808Sgonzo} 777188808Sgonzo 778199234Sgonzo 779188808Sgonzostatic void 780188808Sgonzoarge_reset_dma(struct arge_softc *sc) 781188808Sgonzo{ 782188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0); 783188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0); 784188808Sgonzo 785188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0); 786188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0); 787188808Sgonzo 788188808Sgonzo /* Clear all possible RX interrupts */ 789192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD) 790188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 791188808Sgonzo 792188808Sgonzo /* 793188808Sgonzo * Clear all possible TX interrupts 794188808Sgonzo */ 795192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT) 796188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 797188808Sgonzo 798188808Sgonzo /* 799188808Sgonzo * Now Rx/Tx errors 800188808Sgonzo */ 801188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 802188808Sgonzo DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW); 803188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 804188808Sgonzo DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN); 805188808Sgonzo} 806188808Sgonzo 807188808Sgonzo 808188808Sgonzo 809188808Sgonzostatic void 810188808Sgonzoarge_init(void *xsc) 811188808Sgonzo{ 812188808Sgonzo struct arge_softc *sc = xsc; 813188808Sgonzo 814188808Sgonzo ARGE_LOCK(sc); 815188808Sgonzo arge_init_locked(sc); 816188808Sgonzo ARGE_UNLOCK(sc); 817188808Sgonzo} 818188808Sgonzo 819188808Sgonzostatic void 820188808Sgonzoarge_init_locked(struct arge_softc *sc) 821188808Sgonzo{ 822188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 823188808Sgonzo struct mii_data *mii; 824188808Sgonzo 825188808Sgonzo ARGE_LOCK_ASSERT(sc); 826188808Sgonzo 827188808Sgonzo arge_stop(sc); 828188808Sgonzo 829188808Sgonzo /* Init circular RX list. */ 830188808Sgonzo if (arge_rx_ring_init(sc) != 0) { 831188808Sgonzo device_printf(sc->arge_dev, 832188808Sgonzo "initialization failed: no memory for rx buffers\n"); 833188808Sgonzo arge_stop(sc); 834188808Sgonzo return; 835188808Sgonzo } 836188808Sgonzo 837188808Sgonzo /* Init tx descriptors. */ 838188808Sgonzo arge_tx_ring_init(sc); 839188808Sgonzo 840188808Sgonzo arge_reset_dma(sc); 841188808Sgonzo 842188808Sgonzo 843199234Sgonzo if (sc->arge_miibus) { 844199234Sgonzo sc->arge_link_status = 0; 845199234Sgonzo mii = device_get_softc(sc->arge_miibus); 846199234Sgonzo mii_mediachg(mii); 847199234Sgonzo } 848199234Sgonzo else { 849199234Sgonzo /* 850199234Sgonzo * Sun always shines over multiPHY interface 851199234Sgonzo */ 852199234Sgonzo sc->arge_link_status = 1; 853199234Sgonzo } 854199234Sgonzo 855188808Sgonzo ifp->if_drv_flags |= IFF_DRV_RUNNING; 856188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 857188808Sgonzo 858199234Sgonzo if (sc->arge_miibus) 859199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 860192783Sgonzo 861188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0)); 862188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0)); 863188808Sgonzo 864188808Sgonzo /* Start listening */ 865188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 866188808Sgonzo 867188808Sgonzo /* Enable interrupts */ 868188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 869188808Sgonzo} 870188808Sgonzo 871188808Sgonzo/* 872209807Sadrian * Return whether the mbuf chain is correctly aligned 873209807Sadrian * for the arge TX engine. 874209807Sadrian * 875209807Sadrian * The TX engine requires each fragment to be aligned to a 876209807Sadrian * 4 byte boundary and the size of each fragment except 877209807Sadrian * the last to be a multiple of 4 bytes. 878209807Sadrian */ 879209807Sadrianstatic int 880209807Sadrianarge_mbuf_chain_is_tx_aligned(struct mbuf *m0) 881209807Sadrian{ 882209807Sadrian struct mbuf *m; 883209807Sadrian 884209807Sadrian for (m = m0; m != NULL; m = m->m_next) { 885209807Sadrian if((mtod(m, intptr_t) & 3) != 0) 886209807Sadrian return 0; 887209807Sadrian if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) 888209807Sadrian return 0; 889209807Sadrian } 890209807Sadrian return 1; 891209807Sadrian} 892209807Sadrian 893209807Sadrian/* 894188808Sgonzo * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 895188808Sgonzo * pointers to the fragment pointers. 896188808Sgonzo */ 897188808Sgonzostatic int 898188808Sgonzoarge_encap(struct arge_softc *sc, struct mbuf **m_head) 899188808Sgonzo{ 900188808Sgonzo struct arge_txdesc *txd; 901188808Sgonzo struct arge_desc *desc, *prev_desc; 902188808Sgonzo bus_dma_segment_t txsegs[ARGE_MAXFRAGS]; 903192569Sdwhite int error, i, nsegs, prod, prev_prod; 904192783Sgonzo struct mbuf *m; 905188808Sgonzo 906188808Sgonzo ARGE_LOCK_ASSERT(sc); 907188808Sgonzo 908192783Sgonzo /* 909192783Sgonzo * Fix mbuf chain, all fragments should be 4 bytes aligned and 910192783Sgonzo * even 4 bytes 911192783Sgonzo */ 912192783Sgonzo m = *m_head; 913209807Sadrian if (! arge_mbuf_chain_is_tx_aligned(m)) { 914209809Sadrian sc->stats.tx_pkts_unaligned++; 915192783Sgonzo m = m_defrag(*m_head, M_DONTWAIT); 916192783Sgonzo if (m == NULL) { 917192783Sgonzo *m_head = NULL; 918192783Sgonzo return (ENOBUFS); 919192783Sgonzo } 920192783Sgonzo *m_head = m; 921209809Sadrian } else 922209809Sadrian sc->stats.tx_pkts_aligned++; 923192783Sgonzo 924188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 925188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[prod]; 926188808Sgonzo error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 927188808Sgonzo txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 928188808Sgonzo 929188808Sgonzo if (error == EFBIG) { 930188808Sgonzo panic("EFBIG"); 931188808Sgonzo } else if (error != 0) 932188808Sgonzo return (error); 933188808Sgonzo 934188808Sgonzo if (nsegs == 0) { 935188808Sgonzo m_freem(*m_head); 936188808Sgonzo *m_head = NULL; 937188808Sgonzo return (EIO); 938188808Sgonzo } 939188808Sgonzo 940188808Sgonzo /* Check number of available descriptors. */ 941188808Sgonzo if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) { 942188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 943188808Sgonzo return (ENOBUFS); 944188808Sgonzo } 945188808Sgonzo 946188808Sgonzo txd->tx_m = *m_head; 947188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 948188808Sgonzo BUS_DMASYNC_PREWRITE); 949188808Sgonzo 950188808Sgonzo /* 951188808Sgonzo * Make a list of descriptors for this packet. DMA controller will 952188808Sgonzo * walk through it while arge_link is not zero. 953188808Sgonzo */ 954188808Sgonzo prev_prod = prod; 955188808Sgonzo desc = prev_desc = NULL; 956188808Sgonzo for (i = 0; i < nsegs; i++) { 957188808Sgonzo desc = &sc->arge_rdata.arge_tx_ring[prod]; 958188808Sgonzo desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len); 959188808Sgonzo 960192783Sgonzo if (txsegs[i].ds_addr & 3) 961192783Sgonzo panic("TX packet address unaligned\n"); 962192783Sgonzo 963188808Sgonzo desc->packet_addr = txsegs[i].ds_addr; 964192783Sgonzo 965188808Sgonzo /* link with previous descriptor */ 966188808Sgonzo if (prev_desc) 967188808Sgonzo prev_desc->packet_ctrl |= ARGE_DESC_MORE; 968188808Sgonzo 969188808Sgonzo sc->arge_cdata.arge_tx_cnt++; 970188808Sgonzo prev_desc = desc; 971188808Sgonzo ARGE_INC(prod, ARGE_TX_RING_COUNT); 972188808Sgonzo } 973188808Sgonzo 974188808Sgonzo /* Update producer index. */ 975188808Sgonzo sc->arge_cdata.arge_tx_prod = prod; 976188808Sgonzo 977188808Sgonzo /* Sync descriptors. */ 978188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 979188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 980188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 981188808Sgonzo 982188808Sgonzo /* Start transmitting */ 983220356Sadrian ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n", __func__); 984188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN); 985188808Sgonzo return (0); 986188808Sgonzo} 987188808Sgonzo 988188808Sgonzostatic void 989188808Sgonzoarge_start(struct ifnet *ifp) 990188808Sgonzo{ 991188808Sgonzo struct arge_softc *sc; 992188808Sgonzo 993188808Sgonzo sc = ifp->if_softc; 994188808Sgonzo 995188808Sgonzo ARGE_LOCK(sc); 996188808Sgonzo arge_start_locked(ifp); 997188808Sgonzo ARGE_UNLOCK(sc); 998188808Sgonzo} 999188808Sgonzo 1000188808Sgonzostatic void 1001188808Sgonzoarge_start_locked(struct ifnet *ifp) 1002188808Sgonzo{ 1003188808Sgonzo struct arge_softc *sc; 1004188808Sgonzo struct mbuf *m_head; 1005220356Sadrian int enq = 0; 1006188808Sgonzo 1007188808Sgonzo sc = ifp->if_softc; 1008188808Sgonzo 1009188808Sgonzo ARGE_LOCK_ASSERT(sc); 1010188808Sgonzo 1011220356Sadrian ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__); 1012220356Sadrian 1013188808Sgonzo if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1014188808Sgonzo IFF_DRV_RUNNING || sc->arge_link_status == 0 ) 1015188808Sgonzo return; 1016188808Sgonzo 1017220356Sadrian /* 1018220356Sadrian * Before we go any further, check whether we're already full. 1019220356Sadrian * The below check errors out immediately if the ring is full 1020220356Sadrian * and never gets a chance to set this flag. Although it's 1021220356Sadrian * likely never needed, this at least avoids an unexpected 1022220356Sadrian * situation. 1023220356Sadrian */ 1024220356Sadrian if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) { 1025220356Sadrian ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1026220356Sadrian ARGEDEBUG(sc, ARGE_DBG_ERR, "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n", 1027220356Sadrian __func__, sc->arge_cdata.arge_tx_cnt, ARGE_TX_RING_COUNT - 2); 1028220356Sadrian return; 1029220356Sadrian } 1030220356Sadrian 1031188808Sgonzo arge_flush_ddr(sc); 1032188808Sgonzo 1033188808Sgonzo for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1034188808Sgonzo sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) { 1035188808Sgonzo IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1036188808Sgonzo if (m_head == NULL) 1037188808Sgonzo break; 1038188808Sgonzo 1039188808Sgonzo 1040188808Sgonzo /* 1041188808Sgonzo * Pack the data into the transmit ring. 1042188808Sgonzo */ 1043188808Sgonzo if (arge_encap(sc, &m_head)) { 1044188808Sgonzo if (m_head == NULL) 1045188808Sgonzo break; 1046188808Sgonzo IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1047188808Sgonzo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1048188808Sgonzo break; 1049188808Sgonzo } 1050188808Sgonzo 1051188808Sgonzo enq++; 1052188808Sgonzo /* 1053188808Sgonzo * If there's a BPF listener, bounce a copy of this frame 1054188808Sgonzo * to him. 1055188808Sgonzo */ 1056188808Sgonzo ETHER_BPF_MTAP(ifp, m_head); 1057188808Sgonzo } 1058220356Sadrian ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n", __func__, enq); 1059188808Sgonzo} 1060188808Sgonzo 1061188808Sgonzostatic void 1062188808Sgonzoarge_stop(struct arge_softc *sc) 1063188808Sgonzo{ 1064188808Sgonzo struct ifnet *ifp; 1065188808Sgonzo 1066188808Sgonzo ARGE_LOCK_ASSERT(sc); 1067188808Sgonzo 1068188808Sgonzo ifp = sc->arge_ifp; 1069188808Sgonzo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1070199234Sgonzo if (sc->arge_miibus) 1071199234Sgonzo callout_stop(&sc->arge_stat_callout); 1072188808Sgonzo 1073188808Sgonzo /* mask out interrupts */ 1074188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1075188808Sgonzo 1076188808Sgonzo arge_reset_dma(sc); 1077188808Sgonzo} 1078188808Sgonzo 1079188808Sgonzo 1080188808Sgonzostatic int 1081188808Sgonzoarge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1082188808Sgonzo{ 1083188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1084188808Sgonzo struct ifreq *ifr = (struct ifreq *) data; 1085188808Sgonzo struct mii_data *mii; 1086188808Sgonzo int error; 1087192783Sgonzo#ifdef DEVICE_POLLING 1088192783Sgonzo int mask; 1089192783Sgonzo#endif 1090188808Sgonzo 1091188808Sgonzo switch (command) { 1092188808Sgonzo case SIOCSIFFLAGS: 1093198932Sgonzo ARGE_LOCK(sc); 1094198932Sgonzo if ((ifp->if_flags & IFF_UP) != 0) { 1095198932Sgonzo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1096198932Sgonzo if (((ifp->if_flags ^ sc->arge_if_flags) 1097198939Sgonzo & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1098198939Sgonzo /* XXX: handle promisc & multi flags */ 1099198939Sgonzo } 1100198939Sgonzo 1101198932Sgonzo } else { 1102198932Sgonzo if (!sc->arge_detach) 1103198932Sgonzo arge_init_locked(sc); 1104198932Sgonzo } 1105198932Sgonzo } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1106198932Sgonzo ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1107198932Sgonzo arge_stop(sc); 1108198932Sgonzo } 1109198932Sgonzo sc->arge_if_flags = ifp->if_flags; 1110198932Sgonzo ARGE_UNLOCK(sc); 1111188808Sgonzo error = 0; 1112188808Sgonzo break; 1113188808Sgonzo case SIOCADDMULTI: 1114188808Sgonzo case SIOCDELMULTI: 1115198932Sgonzo /* XXX: implement SIOCDELMULTI */ 1116188808Sgonzo error = 0; 1117188808Sgonzo break; 1118188808Sgonzo case SIOCGIFMEDIA: 1119188808Sgonzo case SIOCSIFMEDIA: 1120199234Sgonzo if (sc->arge_miibus) { 1121199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1122199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1123199234Sgonzo } 1124199234Sgonzo else 1125199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command); 1126188808Sgonzo break; 1127198933Sgonzo case SIOCSIFCAP: 1128198932Sgonzo /* XXX: Check other capabilities */ 1129192783Sgonzo#ifdef DEVICE_POLLING 1130198933Sgonzo mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1131198933Sgonzo if (mask & IFCAP_POLLING) { 1132198933Sgonzo if (ifr->ifr_reqcap & IFCAP_POLLING) { 1133192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1134198933Sgonzo error = ether_poll_register(arge_poll, ifp); 1135198933Sgonzo if (error) 1136198933Sgonzo return error; 1137198933Sgonzo ARGE_LOCK(sc); 1138198933Sgonzo ifp->if_capenable |= IFCAP_POLLING; 1139198933Sgonzo ARGE_UNLOCK(sc); 1140198933Sgonzo } else { 1141192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1142198933Sgonzo error = ether_poll_deregister(ifp); 1143198933Sgonzo ARGE_LOCK(sc); 1144198933Sgonzo ifp->if_capenable &= ~IFCAP_POLLING; 1145198933Sgonzo ARGE_UNLOCK(sc); 1146198933Sgonzo } 1147198933Sgonzo } 1148198932Sgonzo error = 0; 1149198933Sgonzo break; 1150192783Sgonzo#endif 1151188808Sgonzo default: 1152188808Sgonzo error = ether_ioctl(ifp, command, data); 1153188808Sgonzo break; 1154188808Sgonzo } 1155188808Sgonzo 1156188808Sgonzo return (error); 1157188808Sgonzo} 1158188808Sgonzo 1159188808Sgonzo/* 1160188808Sgonzo * Set media options. 1161188808Sgonzo */ 1162188808Sgonzostatic int 1163188808Sgonzoarge_ifmedia_upd(struct ifnet *ifp) 1164188808Sgonzo{ 1165188808Sgonzo struct arge_softc *sc; 1166188808Sgonzo struct mii_data *mii; 1167188808Sgonzo struct mii_softc *miisc; 1168188808Sgonzo int error; 1169188808Sgonzo 1170188808Sgonzo sc = ifp->if_softc; 1171188808Sgonzo ARGE_LOCK(sc); 1172188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1173221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1174221407Smarius PHY_RESET(miisc); 1175188808Sgonzo error = mii_mediachg(mii); 1176188808Sgonzo ARGE_UNLOCK(sc); 1177188808Sgonzo 1178188808Sgonzo return (error); 1179188808Sgonzo} 1180188808Sgonzo 1181188808Sgonzo/* 1182188808Sgonzo * Report current media status. 1183188808Sgonzo */ 1184188808Sgonzostatic void 1185188808Sgonzoarge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1186188808Sgonzo{ 1187188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1188188808Sgonzo struct mii_data *mii; 1189188808Sgonzo 1190188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1191188808Sgonzo ARGE_LOCK(sc); 1192188808Sgonzo mii_pollstat(mii); 1193188808Sgonzo ifmr->ifm_active = mii->mii_media_active; 1194188808Sgonzo ifmr->ifm_status = mii->mii_media_status; 1195226478Syongari ARGE_UNLOCK(sc); 1196188808Sgonzo} 1197188808Sgonzo 1198188808Sgonzostruct arge_dmamap_arg { 1199188808Sgonzo bus_addr_t arge_busaddr; 1200188808Sgonzo}; 1201188808Sgonzo 1202188808Sgonzostatic void 1203188808Sgonzoarge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1204188808Sgonzo{ 1205188808Sgonzo struct arge_dmamap_arg *ctx; 1206188808Sgonzo 1207188808Sgonzo if (error != 0) 1208188808Sgonzo return; 1209188808Sgonzo ctx = arg; 1210188808Sgonzo ctx->arge_busaddr = segs[0].ds_addr; 1211188808Sgonzo} 1212188808Sgonzo 1213188808Sgonzostatic int 1214188808Sgonzoarge_dma_alloc(struct arge_softc *sc) 1215188808Sgonzo{ 1216188808Sgonzo struct arge_dmamap_arg ctx; 1217188808Sgonzo struct arge_txdesc *txd; 1218188808Sgonzo struct arge_rxdesc *rxd; 1219188808Sgonzo int error, i; 1220188808Sgonzo 1221188808Sgonzo /* Create parent DMA tag. */ 1222188808Sgonzo error = bus_dma_tag_create( 1223188808Sgonzo bus_get_dma_tag(sc->arge_dev), /* parent */ 1224188808Sgonzo 1, 0, /* alignment, boundary */ 1225188808Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1226188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1227188808Sgonzo NULL, NULL, /* filter, filterarg */ 1228188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1229188808Sgonzo 0, /* nsegments */ 1230188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1231188808Sgonzo 0, /* flags */ 1232188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1233188808Sgonzo &sc->arge_cdata.arge_parent_tag); 1234188808Sgonzo if (error != 0) { 1235188808Sgonzo device_printf(sc->arge_dev, "failed to create parent DMA tag\n"); 1236188808Sgonzo goto fail; 1237188808Sgonzo } 1238188808Sgonzo /* Create tag for Tx ring. */ 1239188808Sgonzo error = bus_dma_tag_create( 1240188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1241188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1242188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1243188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1244188808Sgonzo NULL, NULL, /* filter, filterarg */ 1245188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsize */ 1246188808Sgonzo 1, /* nsegments */ 1247188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsegsize */ 1248188808Sgonzo 0, /* flags */ 1249188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1250188808Sgonzo &sc->arge_cdata.arge_tx_ring_tag); 1251188808Sgonzo if (error != 0) { 1252188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n"); 1253188808Sgonzo goto fail; 1254188808Sgonzo } 1255188808Sgonzo 1256188808Sgonzo /* Create tag for Rx ring. */ 1257188808Sgonzo error = bus_dma_tag_create( 1258188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1259188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1260188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1261188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1262188808Sgonzo NULL, NULL, /* filter, filterarg */ 1263188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsize */ 1264188808Sgonzo 1, /* nsegments */ 1265188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsegsize */ 1266188808Sgonzo 0, /* flags */ 1267188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1268188808Sgonzo &sc->arge_cdata.arge_rx_ring_tag); 1269188808Sgonzo if (error != 0) { 1270188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n"); 1271188808Sgonzo goto fail; 1272188808Sgonzo } 1273188808Sgonzo 1274188808Sgonzo /* Create tag for Tx buffers. */ 1275188808Sgonzo error = bus_dma_tag_create( 1276188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1277188808Sgonzo sizeof(uint32_t), 0, /* alignment, boundary */ 1278188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1279188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1280188808Sgonzo NULL, NULL, /* filter, filterarg */ 1281188808Sgonzo MCLBYTES * ARGE_MAXFRAGS, /* maxsize */ 1282188808Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1283188808Sgonzo MCLBYTES, /* maxsegsize */ 1284188808Sgonzo 0, /* flags */ 1285188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1286188808Sgonzo &sc->arge_cdata.arge_tx_tag); 1287188808Sgonzo if (error != 0) { 1288188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx DMA tag\n"); 1289188808Sgonzo goto fail; 1290188808Sgonzo } 1291188808Sgonzo 1292188808Sgonzo /* Create tag for Rx buffers. */ 1293188808Sgonzo error = bus_dma_tag_create( 1294188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1295188808Sgonzo ARGE_RX_ALIGN, 0, /* alignment, boundary */ 1296188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1297188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1298188808Sgonzo NULL, NULL, /* filter, filterarg */ 1299188808Sgonzo MCLBYTES, /* maxsize */ 1300192821Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1301188808Sgonzo MCLBYTES, /* maxsegsize */ 1302188808Sgonzo 0, /* flags */ 1303188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1304188808Sgonzo &sc->arge_cdata.arge_rx_tag); 1305188808Sgonzo if (error != 0) { 1306188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx DMA tag\n"); 1307188808Sgonzo goto fail; 1308188808Sgonzo } 1309188808Sgonzo 1310188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1311188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag, 1312188808Sgonzo (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK | 1313188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_tx_ring_map); 1314188808Sgonzo if (error != 0) { 1315188808Sgonzo device_printf(sc->arge_dev, 1316188808Sgonzo "failed to allocate DMA'able memory for Tx ring\n"); 1317188808Sgonzo goto fail; 1318188808Sgonzo } 1319188808Sgonzo 1320188808Sgonzo ctx.arge_busaddr = 0; 1321188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag, 1322188808Sgonzo sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring, 1323188808Sgonzo ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1324188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1325188808Sgonzo device_printf(sc->arge_dev, 1326188808Sgonzo "failed to load DMA'able memory for Tx ring\n"); 1327188808Sgonzo goto fail; 1328188808Sgonzo } 1329188808Sgonzo sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr; 1330188808Sgonzo 1331188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1332188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag, 1333188808Sgonzo (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK | 1334188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_rx_ring_map); 1335188808Sgonzo if (error != 0) { 1336188808Sgonzo device_printf(sc->arge_dev, 1337188808Sgonzo "failed to allocate DMA'able memory for Rx ring\n"); 1338188808Sgonzo goto fail; 1339188808Sgonzo } 1340188808Sgonzo 1341188808Sgonzo ctx.arge_busaddr = 0; 1342188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag, 1343188808Sgonzo sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring, 1344188808Sgonzo ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1345188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1346188808Sgonzo device_printf(sc->arge_dev, 1347188808Sgonzo "failed to load DMA'able memory for Rx ring\n"); 1348188808Sgonzo goto fail; 1349188808Sgonzo } 1350188808Sgonzo sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr; 1351188808Sgonzo 1352188808Sgonzo /* Create DMA maps for Tx buffers. */ 1353188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1354188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1355188808Sgonzo txd->tx_m = NULL; 1356188808Sgonzo txd->tx_dmamap = NULL; 1357188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0, 1358188808Sgonzo &txd->tx_dmamap); 1359188808Sgonzo if (error != 0) { 1360188808Sgonzo device_printf(sc->arge_dev, 1361188808Sgonzo "failed to create Tx dmamap\n"); 1362188808Sgonzo goto fail; 1363188808Sgonzo } 1364188808Sgonzo } 1365188808Sgonzo /* Create DMA maps for Rx buffers. */ 1366188808Sgonzo if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1367188808Sgonzo &sc->arge_cdata.arge_rx_sparemap)) != 0) { 1368188808Sgonzo device_printf(sc->arge_dev, 1369188808Sgonzo "failed to create spare Rx dmamap\n"); 1370188808Sgonzo goto fail; 1371188808Sgonzo } 1372188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1373188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1374188808Sgonzo rxd->rx_m = NULL; 1375188808Sgonzo rxd->rx_dmamap = NULL; 1376188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1377188808Sgonzo &rxd->rx_dmamap); 1378188808Sgonzo if (error != 0) { 1379188808Sgonzo device_printf(sc->arge_dev, 1380188808Sgonzo "failed to create Rx dmamap\n"); 1381188808Sgonzo goto fail; 1382188808Sgonzo } 1383188808Sgonzo } 1384188808Sgonzo 1385188808Sgonzofail: 1386188808Sgonzo return (error); 1387188808Sgonzo} 1388188808Sgonzo 1389188808Sgonzostatic void 1390188808Sgonzoarge_dma_free(struct arge_softc *sc) 1391188808Sgonzo{ 1392188808Sgonzo struct arge_txdesc *txd; 1393188808Sgonzo struct arge_rxdesc *rxd; 1394188808Sgonzo int i; 1395188808Sgonzo 1396188808Sgonzo /* Tx ring. */ 1397188808Sgonzo if (sc->arge_cdata.arge_tx_ring_tag) { 1398188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map) 1399188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag, 1400188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1401188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map && 1402188808Sgonzo sc->arge_rdata.arge_tx_ring) 1403188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag, 1404188808Sgonzo sc->arge_rdata.arge_tx_ring, 1405188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1406188808Sgonzo sc->arge_rdata.arge_tx_ring = NULL; 1407188808Sgonzo sc->arge_cdata.arge_tx_ring_map = NULL; 1408188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag); 1409188808Sgonzo sc->arge_cdata.arge_tx_ring_tag = NULL; 1410188808Sgonzo } 1411188808Sgonzo /* Rx ring. */ 1412188808Sgonzo if (sc->arge_cdata.arge_rx_ring_tag) { 1413188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map) 1414188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag, 1415188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1416188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map && 1417188808Sgonzo sc->arge_rdata.arge_rx_ring) 1418188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag, 1419188808Sgonzo sc->arge_rdata.arge_rx_ring, 1420188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1421188808Sgonzo sc->arge_rdata.arge_rx_ring = NULL; 1422188808Sgonzo sc->arge_cdata.arge_rx_ring_map = NULL; 1423188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag); 1424188808Sgonzo sc->arge_cdata.arge_rx_ring_tag = NULL; 1425188808Sgonzo } 1426188808Sgonzo /* Tx buffers. */ 1427188808Sgonzo if (sc->arge_cdata.arge_tx_tag) { 1428188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1429188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1430188808Sgonzo if (txd->tx_dmamap) { 1431188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag, 1432188808Sgonzo txd->tx_dmamap); 1433188808Sgonzo txd->tx_dmamap = NULL; 1434188808Sgonzo } 1435188808Sgonzo } 1436188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag); 1437188808Sgonzo sc->arge_cdata.arge_tx_tag = NULL; 1438188808Sgonzo } 1439188808Sgonzo /* Rx buffers. */ 1440188808Sgonzo if (sc->arge_cdata.arge_rx_tag) { 1441188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1442188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1443188808Sgonzo if (rxd->rx_dmamap) { 1444188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1445188808Sgonzo rxd->rx_dmamap); 1446188808Sgonzo rxd->rx_dmamap = NULL; 1447188808Sgonzo } 1448188808Sgonzo } 1449188808Sgonzo if (sc->arge_cdata.arge_rx_sparemap) { 1450188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1451188808Sgonzo sc->arge_cdata.arge_rx_sparemap); 1452188808Sgonzo sc->arge_cdata.arge_rx_sparemap = 0; 1453188808Sgonzo } 1454188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag); 1455188808Sgonzo sc->arge_cdata.arge_rx_tag = NULL; 1456188808Sgonzo } 1457188808Sgonzo 1458188808Sgonzo if (sc->arge_cdata.arge_parent_tag) { 1459188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag); 1460188808Sgonzo sc->arge_cdata.arge_parent_tag = NULL; 1461188808Sgonzo } 1462188808Sgonzo} 1463188808Sgonzo 1464188808Sgonzo/* 1465188808Sgonzo * Initialize the transmit descriptors. 1466188808Sgonzo */ 1467188808Sgonzostatic int 1468188808Sgonzoarge_tx_ring_init(struct arge_softc *sc) 1469188808Sgonzo{ 1470188808Sgonzo struct arge_ring_data *rd; 1471188808Sgonzo struct arge_txdesc *txd; 1472188808Sgonzo bus_addr_t addr; 1473188808Sgonzo int i; 1474188808Sgonzo 1475188808Sgonzo sc->arge_cdata.arge_tx_prod = 0; 1476188808Sgonzo sc->arge_cdata.arge_tx_cons = 0; 1477188808Sgonzo sc->arge_cdata.arge_tx_cnt = 0; 1478188808Sgonzo 1479188808Sgonzo rd = &sc->arge_rdata; 1480188808Sgonzo bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring)); 1481188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1482188808Sgonzo if (i == ARGE_TX_RING_COUNT - 1) 1483188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, 0); 1484188808Sgonzo else 1485188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, i + 1); 1486188808Sgonzo rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY; 1487188808Sgonzo rd->arge_tx_ring[i].next_desc = addr; 1488188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1489188808Sgonzo txd->tx_m = NULL; 1490188808Sgonzo } 1491188808Sgonzo 1492188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1493188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1494188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1495188808Sgonzo 1496188808Sgonzo return (0); 1497188808Sgonzo} 1498188808Sgonzo 1499188808Sgonzo/* 1500188808Sgonzo * Initialize the RX descriptors and allocate mbufs for them. Note that 1501188808Sgonzo * we arrange the descriptors in a closed ring, so that the last descriptor 1502188808Sgonzo * points back to the first. 1503188808Sgonzo */ 1504188808Sgonzostatic int 1505188808Sgonzoarge_rx_ring_init(struct arge_softc *sc) 1506188808Sgonzo{ 1507188808Sgonzo struct arge_ring_data *rd; 1508188808Sgonzo struct arge_rxdesc *rxd; 1509188808Sgonzo bus_addr_t addr; 1510188808Sgonzo int i; 1511188808Sgonzo 1512188808Sgonzo sc->arge_cdata.arge_rx_cons = 0; 1513188808Sgonzo 1514188808Sgonzo rd = &sc->arge_rdata; 1515188808Sgonzo bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring)); 1516188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1517188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1518188808Sgonzo rxd->rx_m = NULL; 1519188808Sgonzo rxd->desc = &rd->arge_rx_ring[i]; 1520188808Sgonzo if (i == ARGE_RX_RING_COUNT - 1) 1521188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, 0); 1522188808Sgonzo else 1523188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, i + 1); 1524188808Sgonzo rd->arge_rx_ring[i].next_desc = addr; 1525192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1526188808Sgonzo return (ENOBUFS); 1527192783Sgonzo } 1528188808Sgonzo } 1529188808Sgonzo 1530188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1531188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1532195434Sgonzo BUS_DMASYNC_PREWRITE); 1533188808Sgonzo 1534188808Sgonzo return (0); 1535188808Sgonzo} 1536188808Sgonzo 1537188808Sgonzo/* 1538188808Sgonzo * Initialize an RX descriptor and attach an MBUF cluster. 1539188808Sgonzo */ 1540188808Sgonzostatic int 1541188808Sgonzoarge_newbuf(struct arge_softc *sc, int idx) 1542188808Sgonzo{ 1543188808Sgonzo struct arge_desc *desc; 1544188808Sgonzo struct arge_rxdesc *rxd; 1545188808Sgonzo struct mbuf *m; 1546188808Sgonzo bus_dma_segment_t segs[1]; 1547188808Sgonzo bus_dmamap_t map; 1548188808Sgonzo int nsegs; 1549188808Sgonzo 1550188808Sgonzo m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1551188808Sgonzo if (m == NULL) 1552188808Sgonzo return (ENOBUFS); 1553188808Sgonzo m->m_len = m->m_pkthdr.len = MCLBYTES; 1554188808Sgonzo m_adj(m, sizeof(uint64_t)); 1555188808Sgonzo 1556188808Sgonzo if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag, 1557188808Sgonzo sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1558188808Sgonzo m_freem(m); 1559188808Sgonzo return (ENOBUFS); 1560188808Sgonzo } 1561188808Sgonzo KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1562188808Sgonzo 1563188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[idx]; 1564188808Sgonzo if (rxd->rx_m != NULL) { 1565188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap); 1566188808Sgonzo } 1567188808Sgonzo map = rxd->rx_dmamap; 1568188808Sgonzo rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap; 1569188808Sgonzo sc->arge_cdata.arge_rx_sparemap = map; 1570188808Sgonzo rxd->rx_m = m; 1571188808Sgonzo desc = rxd->desc; 1572192783Sgonzo if (segs[0].ds_addr & 3) 1573192783Sgonzo panic("RX packet address unaligned"); 1574188808Sgonzo desc->packet_addr = segs[0].ds_addr; 1575192783Sgonzo desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len); 1576188808Sgonzo 1577195434Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1578195434Sgonzo sc->arge_cdata.arge_rx_ring_map, 1579195434Sgonzo BUS_DMASYNC_PREWRITE); 1580195434Sgonzo 1581188808Sgonzo return (0); 1582188808Sgonzo} 1583188808Sgonzo 1584188808Sgonzostatic __inline void 1585188808Sgonzoarge_fixup_rx(struct mbuf *m) 1586188808Sgonzo{ 1587198933Sgonzo int i; 1588198933Sgonzo uint16_t *src, *dst; 1589188808Sgonzo 1590188808Sgonzo src = mtod(m, uint16_t *); 1591188808Sgonzo dst = src - 1; 1592188808Sgonzo 1593195434Sgonzo for (i = 0; i < m->m_len / sizeof(uint16_t); i++) { 1594188808Sgonzo *dst++ = *src++; 1595195434Sgonzo } 1596188808Sgonzo 1597195434Sgonzo if (m->m_len % sizeof(uint16_t)) 1598195434Sgonzo *(uint8_t *)dst = *(uint8_t *)src; 1599195434Sgonzo 1600188808Sgonzo m->m_data -= ETHER_ALIGN; 1601188808Sgonzo} 1602188808Sgonzo 1603192783Sgonzo#ifdef DEVICE_POLLING 1604198667Sgonzostatic int 1605192783Sgonzoarge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1606192783Sgonzo{ 1607192783Sgonzo struct arge_softc *sc = ifp->if_softc; 1608198667Sgonzo int rx_npkts = 0; 1609188808Sgonzo 1610198933Sgonzo if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1611192783Sgonzo ARGE_LOCK(sc); 1612192783Sgonzo arge_tx_locked(sc); 1613198667Sgonzo rx_npkts = arge_rx_locked(sc); 1614192783Sgonzo ARGE_UNLOCK(sc); 1615198933Sgonzo } 1616198667Sgonzo 1617198667Sgonzo return (rx_npkts); 1618192783Sgonzo} 1619192783Sgonzo#endif /* DEVICE_POLLING */ 1620192783Sgonzo 1621192783Sgonzo 1622188808Sgonzostatic void 1623188808Sgonzoarge_tx_locked(struct arge_softc *sc) 1624188808Sgonzo{ 1625188808Sgonzo struct arge_txdesc *txd; 1626188808Sgonzo struct arge_desc *cur_tx; 1627188808Sgonzo struct ifnet *ifp; 1628188808Sgonzo uint32_t ctrl; 1629188808Sgonzo int cons, prod; 1630188808Sgonzo 1631188808Sgonzo ARGE_LOCK_ASSERT(sc); 1632188808Sgonzo 1633188808Sgonzo cons = sc->arge_cdata.arge_tx_cons; 1634188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 1635220356Sadrian 1636220356Sadrian ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons, prod); 1637220356Sadrian 1638188808Sgonzo if (cons == prod) 1639188808Sgonzo return; 1640188808Sgonzo 1641188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1642188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1643188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1644188808Sgonzo 1645188808Sgonzo ifp = sc->arge_ifp; 1646188808Sgonzo /* 1647188808Sgonzo * Go through our tx list and free mbufs for those 1648188808Sgonzo * frames that have been transmitted. 1649188808Sgonzo */ 1650188808Sgonzo for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) { 1651188808Sgonzo cur_tx = &sc->arge_rdata.arge_tx_ring[cons]; 1652188808Sgonzo ctrl = cur_tx->packet_ctrl; 1653188808Sgonzo /* Check if descriptor has "finished" flag */ 1654188808Sgonzo if ((ctrl & ARGE_DESC_EMPTY) == 0) 1655188808Sgonzo break; 1656188808Sgonzo 1657188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 1658188808Sgonzo 1659188808Sgonzo sc->arge_cdata.arge_tx_cnt--; 1660188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1661188808Sgonzo 1662188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[cons]; 1663188808Sgonzo 1664188808Sgonzo ifp->if_opackets++; 1665188808Sgonzo 1666188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 1667188808Sgonzo BUS_DMASYNC_POSTWRITE); 1668188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 1669188808Sgonzo 1670188808Sgonzo /* Free only if it's first descriptor in list */ 1671188808Sgonzo if (txd->tx_m) 1672188808Sgonzo m_freem(txd->tx_m); 1673188808Sgonzo txd->tx_m = NULL; 1674188808Sgonzo 1675188808Sgonzo /* reset descriptor */ 1676188808Sgonzo cur_tx->packet_addr = 0; 1677188808Sgonzo } 1678188808Sgonzo 1679188808Sgonzo sc->arge_cdata.arge_tx_cons = cons; 1680188808Sgonzo 1681188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1682188808Sgonzo sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1683188808Sgonzo} 1684188808Sgonzo 1685188808Sgonzo 1686198667Sgonzostatic int 1687188808Sgonzoarge_rx_locked(struct arge_softc *sc) 1688188808Sgonzo{ 1689188808Sgonzo struct arge_rxdesc *rxd; 1690188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 1691192783Sgonzo int cons, prog, packet_len, i; 1692188808Sgonzo struct arge_desc *cur_rx; 1693188808Sgonzo struct mbuf *m; 1694198667Sgonzo int rx_npkts = 0; 1695188808Sgonzo 1696188808Sgonzo ARGE_LOCK_ASSERT(sc); 1697188808Sgonzo 1698188808Sgonzo cons = sc->arge_cdata.arge_rx_cons; 1699188808Sgonzo 1700188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1701188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1702188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1703188808Sgonzo 1704188808Sgonzo for (prog = 0; prog < ARGE_RX_RING_COUNT; 1705188808Sgonzo ARGE_INC(cons, ARGE_RX_RING_COUNT)) { 1706188808Sgonzo cur_rx = &sc->arge_rdata.arge_rx_ring[cons]; 1707188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[cons]; 1708188808Sgonzo m = rxd->rx_m; 1709188808Sgonzo 1710188808Sgonzo if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0) 1711188808Sgonzo break; 1712188808Sgonzo 1713188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 1714188808Sgonzo 1715188808Sgonzo prog++; 1716188808Sgonzo 1717188808Sgonzo packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl); 1718188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap, 1719195434Sgonzo BUS_DMASYNC_POSTREAD); 1720188808Sgonzo m = rxd->rx_m; 1721188808Sgonzo 1722188808Sgonzo arge_fixup_rx(m); 1723188808Sgonzo m->m_pkthdr.rcvif = ifp; 1724188808Sgonzo /* Skip 4 bytes of CRC */ 1725188808Sgonzo m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN; 1726188808Sgonzo ifp->if_ipackets++; 1727198667Sgonzo rx_npkts++; 1728188808Sgonzo 1729188808Sgonzo ARGE_UNLOCK(sc); 1730188808Sgonzo (*ifp->if_input)(ifp, m); 1731188808Sgonzo ARGE_LOCK(sc); 1732192783Sgonzo cur_rx->packet_addr = 0; 1733192783Sgonzo } 1734188808Sgonzo 1735192783Sgonzo if (prog > 0) { 1736192783Sgonzo 1737192783Sgonzo i = sc->arge_cdata.arge_rx_cons; 1738192783Sgonzo for (; prog > 0 ; prog--) { 1739192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1740192783Sgonzo device_printf(sc->arge_dev, 1741192783Sgonzo "Failed to allocate buffer\n"); 1742192783Sgonzo break; 1743192783Sgonzo } 1744192783Sgonzo ARGE_INC(i, ARGE_RX_RING_COUNT); 1745188808Sgonzo } 1746188808Sgonzo 1747188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1748188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1749195434Sgonzo BUS_DMASYNC_PREWRITE); 1750188808Sgonzo 1751188808Sgonzo sc->arge_cdata.arge_rx_cons = cons; 1752188808Sgonzo } 1753198667Sgonzo 1754198667Sgonzo return (rx_npkts); 1755188808Sgonzo} 1756188808Sgonzo 1757188808Sgonzostatic int 1758188808Sgonzoarge_intr_filter(void *arg) 1759188808Sgonzo{ 1760188808Sgonzo struct arge_softc *sc = arg; 1761188808Sgonzo uint32_t status, ints; 1762188808Sgonzo 1763188808Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1764188808Sgonzo ints = ARGE_READ(sc, AR71XX_DMA_INTR); 1765188808Sgonzo 1766220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints, 1767188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1768188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1769220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status, 1770188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1771188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1772188808Sgonzo 1773188808Sgonzo if (status & DMA_INTR_ALL) { 1774191644Sgonzo sc->arge_intr_status |= status; 1775192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1776188808Sgonzo return (FILTER_SCHEDULE_THREAD); 1777192783Sgonzo } 1778188808Sgonzo 1779188808Sgonzo sc->arge_intr_status = 0; 1780188808Sgonzo return (FILTER_STRAY); 1781188808Sgonzo} 1782188808Sgonzo 1783188808Sgonzostatic void 1784188808Sgonzoarge_intr(void *arg) 1785188808Sgonzo{ 1786188808Sgonzo struct arge_softc *sc = arg; 1787188808Sgonzo uint32_t status; 1788220356Sadrian struct ifnet *ifp = sc->arge_ifp; 1789188808Sgonzo 1790192783Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1791192783Sgonzo status |= sc->arge_intr_status; 1792188808Sgonzo 1793220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status, 1794188808Sgonzo "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD" 1795188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1796188808Sgonzo 1797188808Sgonzo /* 1798188808Sgonzo * Is it our interrupt at all? 1799188808Sgonzo */ 1800188808Sgonzo if (status == 0) 1801188808Sgonzo return; 1802188808Sgonzo 1803188808Sgonzo if (status & DMA_INTR_RX_BUS_ERROR) { 1804188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR); 1805188808Sgonzo device_printf(sc->arge_dev, "RX bus error"); 1806188808Sgonzo return; 1807188808Sgonzo } 1808188808Sgonzo 1809188808Sgonzo if (status & DMA_INTR_TX_BUS_ERROR) { 1810188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR); 1811188808Sgonzo device_printf(sc->arge_dev, "TX bus error"); 1812188808Sgonzo return; 1813188808Sgonzo } 1814188808Sgonzo 1815192783Sgonzo ARGE_LOCK(sc); 1816188808Sgonzo 1817192783Sgonzo if (status & DMA_INTR_RX_PKT_RCVD) 1818192783Sgonzo arge_rx_locked(sc); 1819188808Sgonzo 1820192783Sgonzo /* 1821192783Sgonzo * RX overrun disables the receiver. 1822192783Sgonzo * Clear indication and re-enable rx. 1823192783Sgonzo */ 1824192783Sgonzo if ( status & DMA_INTR_RX_OVERFLOW) { 1825192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW); 1826192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 1827220356Sadrian sc->stats.rx_overflow++; 1828192783Sgonzo } 1829188808Sgonzo 1830192783Sgonzo if (status & DMA_INTR_TX_PKT_SENT) 1831192783Sgonzo arge_tx_locked(sc); 1832192783Sgonzo /* 1833192783Sgonzo * Underrun turns off TX. Clear underrun indication. 1834192783Sgonzo * If there's anything left in the ring, reactivate the tx. 1835192783Sgonzo */ 1836192569Sdwhite if (status & DMA_INTR_TX_UNDERRUN) { 1837192569Sdwhite ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN); 1838220356Sadrian sc->stats.tx_underflow++; 1839220356Sadrian ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n", __func__, sc->arge_cdata.arge_tx_cnt); 1840219590Sadrian if (sc->arge_cdata.arge_tx_cnt > 0 ) { 1841192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 1842192783Sgonzo DMA_TX_CONTROL_EN); 1843192783Sgonzo } 1844192569Sdwhite } 1845192569Sdwhite 1846192946Sgonzo /* 1847220357Sadrian * If we've finished TXing and there's space for more packets 1848220357Sadrian * to be queued for TX, do so. Otherwise we may end up in a 1849220357Sadrian * situation where the interface send queue was filled 1850220357Sadrian * whilst the hardware queue was full, then the hardware 1851220357Sadrian * queue was drained by the interface send queue wasn't, 1852220357Sadrian * and thus if_start() is never called to kick-start 1853220357Sadrian * the send process (and all subsequent packets are simply 1854220357Sadrian * discarded. 1855220357Sadrian * 1856220357Sadrian * XXX TODO: make sure that the hardware deals nicely 1857220357Sadrian * with the possibility of the queue being enabled above 1858220357Sadrian * after a TX underrun, then having the hardware queue added 1859220357Sadrian * to below. 1860220357Sadrian */ 1861220357Sadrian if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) && 1862220357Sadrian (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1863220357Sadrian if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1864220357Sadrian arge_start_locked(ifp); 1865220357Sadrian } 1866220357Sadrian 1867220357Sadrian /* 1868192946Sgonzo * We handled all bits, clear status 1869192946Sgonzo */ 1870192946Sgonzo sc->arge_intr_status = 0; 1871188808Sgonzo ARGE_UNLOCK(sc); 1872192783Sgonzo /* 1873192783Sgonzo * re-enable all interrupts 1874192783Sgonzo */ 1875192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1876188808Sgonzo} 1877188808Sgonzo 1878192783Sgonzo 1879188808Sgonzostatic void 1880188808Sgonzoarge_tick(void *xsc) 1881188808Sgonzo{ 1882188808Sgonzo struct arge_softc *sc = xsc; 1883188808Sgonzo struct mii_data *mii; 1884188808Sgonzo 1885188808Sgonzo ARGE_LOCK_ASSERT(sc); 1886188808Sgonzo 1887199234Sgonzo if (sc->arge_miibus) { 1888199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1889199234Sgonzo mii_tick(mii); 1890199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 1891199234Sgonzo } 1892188808Sgonzo} 1893199234Sgonzo 1894199234Sgonzoint 1895199234Sgonzoarge_multiphy_mediachange(struct ifnet *ifp) 1896199234Sgonzo{ 1897199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1898199234Sgonzo struct ifmedia *ifm = &sc->arge_ifmedia; 1899199234Sgonzo struct ifmedia_entry *ife = ifm->ifm_cur; 1900199234Sgonzo 1901199234Sgonzo if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1902199234Sgonzo return (EINVAL); 1903199234Sgonzo 1904199234Sgonzo if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1905199234Sgonzo device_printf(sc->arge_dev, 1906199234Sgonzo "AUTO is not supported for multiphy MAC"); 1907199234Sgonzo return (EINVAL); 1908199234Sgonzo } 1909199234Sgonzo 1910199234Sgonzo /* 1911199234Sgonzo * Ignore everything 1912199234Sgonzo */ 1913199234Sgonzo return (0); 1914199234Sgonzo} 1915199234Sgonzo 1916199234Sgonzovoid 1917199234Sgonzoarge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1918199234Sgonzo{ 1919199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1920199234Sgonzo 1921199234Sgonzo ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1922199234Sgonzo ifmr->ifm_active = IFM_ETHER | sc->arge_media_type | 1923199234Sgonzo sc->arge_duplex_mode; 1924199234Sgonzo} 1925199234Sgonzo 1926