if_arge.c revision 213894
1188808Sgonzo/*- 2188808Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko 3188808Sgonzo * All rights reserved. 4188808Sgonzo * 5188808Sgonzo * Redistribution and use in source and binary forms, with or without 6188808Sgonzo * modification, are permitted provided that the following conditions 7188808Sgonzo * are met: 8188808Sgonzo * 1. Redistributions of source code must retain the above copyright 9188808Sgonzo * notice unmodified, this list of conditions, and the following 10188808Sgonzo * disclaimer. 11188808Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12188808Sgonzo * notice, this list of conditions and the following disclaimer in the 13188808Sgonzo * documentation and/or other materials provided with the distribution. 14188808Sgonzo * 15188808Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16188808Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17188808Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18188808Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19188808Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20188808Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21188808Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22188808Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23188808Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24188808Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25188808Sgonzo * SUCH DAMAGE. 26188808Sgonzo */ 27188808Sgonzo 28188808Sgonzo#include <sys/cdefs.h> 29188808Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/if_arge.c 213894 2010-10-15 15:00:30Z marius $"); 30188808Sgonzo 31188808Sgonzo/* 32188808Sgonzo * AR71XX gigabit ethernet driver 33188808Sgonzo */ 34192783Sgonzo#ifdef HAVE_KERNEL_OPTION_HEADERS 35192783Sgonzo#include "opt_device_polling.h" 36192783Sgonzo#endif 37192783Sgonzo 38188808Sgonzo#include <sys/param.h> 39188808Sgonzo#include <sys/endian.h> 40188808Sgonzo#include <sys/systm.h> 41188808Sgonzo#include <sys/sockio.h> 42188808Sgonzo#include <sys/mbuf.h> 43188808Sgonzo#include <sys/malloc.h> 44188808Sgonzo#include <sys/kernel.h> 45188808Sgonzo#include <sys/module.h> 46188808Sgonzo#include <sys/socket.h> 47188808Sgonzo#include <sys/taskqueue.h> 48209802Sadrian#include <sys/sysctl.h> 49188808Sgonzo 50188808Sgonzo#include <net/if.h> 51188808Sgonzo#include <net/if_arp.h> 52188808Sgonzo#include <net/ethernet.h> 53188808Sgonzo#include <net/if_dl.h> 54188808Sgonzo#include <net/if_media.h> 55188808Sgonzo#include <net/if_types.h> 56188808Sgonzo 57188808Sgonzo#include <net/bpf.h> 58188808Sgonzo 59188808Sgonzo#include <machine/bus.h> 60188808Sgonzo#include <machine/cache.h> 61188808Sgonzo#include <machine/resource.h> 62188808Sgonzo#include <vm/vm_param.h> 63188808Sgonzo#include <vm/vm.h> 64188808Sgonzo#include <vm/pmap.h> 65188808Sgonzo#include <machine/pmap.h> 66188808Sgonzo#include <sys/bus.h> 67188808Sgonzo#include <sys/rman.h> 68188808Sgonzo 69188808Sgonzo#include <dev/mii/mii.h> 70188808Sgonzo#include <dev/mii/miivar.h> 71188808Sgonzo 72188808Sgonzo#include <dev/pci/pcireg.h> 73188808Sgonzo#include <dev/pci/pcivar.h> 74188808Sgonzo 75188808SgonzoMODULE_DEPEND(arge, ether, 1, 1, 1); 76188808SgonzoMODULE_DEPEND(arge, miibus, 1, 1, 1); 77188808Sgonzo 78188808Sgonzo#include "miibus_if.h" 79188808Sgonzo 80188808Sgonzo#include <mips/atheros/ar71xxreg.h> 81188808Sgonzo#include <mips/atheros/if_argevar.h> 82211477Sadrian#include <mips/atheros/ar71xx_cpudef.h> 83188808Sgonzo 84188808Sgonzo#undef ARGE_DEBUG 85188808Sgonzo#ifdef ARGE_DEBUG 86188808Sgonzo#define dprintf printf 87188808Sgonzo#else 88188808Sgonzo#define dprintf(x, arg...) 89188808Sgonzo#endif 90188808Sgonzo 91188808Sgonzostatic int arge_attach(device_t); 92188808Sgonzostatic int arge_detach(device_t); 93188808Sgonzostatic void arge_flush_ddr(struct arge_softc *); 94188808Sgonzostatic int arge_ifmedia_upd(struct ifnet *); 95188808Sgonzostatic void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 96188808Sgonzostatic int arge_ioctl(struct ifnet *, u_long, caddr_t); 97188808Sgonzostatic void arge_init(void *); 98188808Sgonzostatic void arge_init_locked(struct arge_softc *); 99188808Sgonzostatic void arge_link_task(void *, int); 100199234Sgonzostatic void arge_set_pll(struct arge_softc *, int, int); 101188808Sgonzostatic int arge_miibus_readreg(device_t, int, int); 102188808Sgonzostatic void arge_miibus_statchg(device_t); 103188808Sgonzostatic int arge_miibus_writereg(device_t, int, int, int); 104188808Sgonzostatic int arge_probe(device_t); 105188808Sgonzostatic void arge_reset_dma(struct arge_softc *); 106188808Sgonzostatic int arge_resume(device_t); 107188808Sgonzostatic int arge_rx_ring_init(struct arge_softc *); 108188808Sgonzostatic int arge_tx_ring_init(struct arge_softc *); 109192821Sgonzo#ifdef DEVICE_POLLING 110198667Sgonzostatic int arge_poll(struct ifnet *, enum poll_cmd, int); 111192821Sgonzo#endif 112194059Sgonzostatic int arge_shutdown(device_t); 113188808Sgonzostatic void arge_start(struct ifnet *); 114188808Sgonzostatic void arge_start_locked(struct ifnet *); 115188808Sgonzostatic void arge_stop(struct arge_softc *); 116188808Sgonzostatic int arge_suspend(device_t); 117188808Sgonzo 118198667Sgonzostatic int arge_rx_locked(struct arge_softc *); 119188808Sgonzostatic void arge_tx_locked(struct arge_softc *); 120188808Sgonzostatic void arge_intr(void *); 121188808Sgonzostatic int arge_intr_filter(void *); 122188808Sgonzostatic void arge_tick(void *); 123188808Sgonzo 124199234Sgonzo/* 125199234Sgonzo * ifmedia callbacks for multiPHY MAC 126199234Sgonzo */ 127199234Sgonzovoid arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *); 128199234Sgonzoint arge_multiphy_mediachange(struct ifnet *); 129199234Sgonzo 130188808Sgonzostatic void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 131188808Sgonzostatic int arge_dma_alloc(struct arge_softc *); 132188808Sgonzostatic void arge_dma_free(struct arge_softc *); 133188808Sgonzostatic int arge_newbuf(struct arge_softc *, int); 134188808Sgonzostatic __inline void arge_fixup_rx(struct mbuf *); 135188808Sgonzo 136188808Sgonzostatic device_method_t arge_methods[] = { 137188808Sgonzo /* Device interface */ 138188808Sgonzo DEVMETHOD(device_probe, arge_probe), 139188808Sgonzo DEVMETHOD(device_attach, arge_attach), 140188808Sgonzo DEVMETHOD(device_detach, arge_detach), 141188808Sgonzo DEVMETHOD(device_suspend, arge_suspend), 142188808Sgonzo DEVMETHOD(device_resume, arge_resume), 143188808Sgonzo DEVMETHOD(device_shutdown, arge_shutdown), 144188808Sgonzo 145188808Sgonzo /* bus interface */ 146188808Sgonzo DEVMETHOD(bus_print_child, bus_generic_print_child), 147188808Sgonzo DEVMETHOD(bus_driver_added, bus_generic_driver_added), 148188808Sgonzo 149188808Sgonzo /* MII interface */ 150188808Sgonzo DEVMETHOD(miibus_readreg, arge_miibus_readreg), 151188808Sgonzo DEVMETHOD(miibus_writereg, arge_miibus_writereg), 152188808Sgonzo DEVMETHOD(miibus_statchg, arge_miibus_statchg), 153188808Sgonzo 154188808Sgonzo { 0, 0 } 155188808Sgonzo}; 156188808Sgonzo 157188808Sgonzostatic driver_t arge_driver = { 158188808Sgonzo "arge", 159188808Sgonzo arge_methods, 160188808Sgonzo sizeof(struct arge_softc) 161188808Sgonzo}; 162188808Sgonzo 163188808Sgonzostatic devclass_t arge_devclass; 164188808Sgonzo 165188808SgonzoDRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0); 166188808SgonzoDRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0); 167188808Sgonzo 168188808Sgonzo/* 169192179Sgonzo * RedBoot passes MAC address to entry point as environment 170192179Sgonzo * variable. platfrom_start parses it and stores in this variable 171192179Sgonzo */ 172192179Sgonzoextern uint32_t ar711_base_mac[ETHER_ADDR_LEN]; 173192179Sgonzo 174199038Sgonzostatic struct mtx miibus_mtx; 175199038Sgonzo 176206400SgonzoMTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF); 177199038Sgonzo 178199038Sgonzo 179192179Sgonzo/* 180188808Sgonzo * Flushes all 181188808Sgonzo */ 182188808Sgonzostatic void 183188808Sgonzoarge_flush_ddr(struct arge_softc *sc) 184188808Sgonzo{ 185211497Sadrian if (sc->arge_mac_unit == 0) 186211477Sadrian ar71xx_device_flush_ddr_ge0(); 187211497Sadrian else 188211477Sadrian ar71xx_device_flush_ddr_ge1(); 189188808Sgonzo} 190188808Sgonzo 191188808Sgonzostatic int 192188808Sgonzoarge_probe(device_t dev) 193188808Sgonzo{ 194188808Sgonzo 195188808Sgonzo device_set_desc(dev, "Atheros AR71xx built-in ethernet interface"); 196188808Sgonzo return (0); 197188808Sgonzo} 198188808Sgonzo 199209802Sadrianstatic void 200209802Sadrianarge_attach_sysctl(device_t dev) 201209802Sadrian{ 202209802Sadrian struct arge_softc *sc = device_get_softc(dev); 203209802Sadrian struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 204209802Sadrian struct sysctl_oid *tree = device_get_sysctl_tree(dev); 205209802Sadrian 206209802Sadrian SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 207209802Sadrian "debug", CTLFLAG_RW, &sc->arge_debug, 0, 208209802Sadrian "arge interface debugging flags"); 209209809Sadrian 210209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 211209809Sadrian "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0, 212209809Sadrian "number of TX aligned packets"); 213209809Sadrian 214209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 215209809Sadrian "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 0, 216209809Sadrian "number of TX unaligned packets"); 217209802Sadrian} 218209802Sadrian 219188808Sgonzostatic int 220188808Sgonzoarge_attach(device_t dev) 221188808Sgonzo{ 222188808Sgonzo uint8_t eaddr[ETHER_ADDR_LEN]; 223188808Sgonzo struct ifnet *ifp; 224188808Sgonzo struct arge_softc *sc; 225199234Sgonzo int error = 0, rid, phymask; 226192179Sgonzo uint32_t reg, rnd; 227199234Sgonzo int is_base_mac_empty, i, phys_total; 228199234Sgonzo uint32_t hint; 229188808Sgonzo 230188808Sgonzo sc = device_get_softc(dev); 231188808Sgonzo sc->arge_dev = dev; 232188808Sgonzo sc->arge_mac_unit = device_get_unit(dev); 233188808Sgonzo 234188808Sgonzo KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 235188808Sgonzo ("if_arge: Only MAC0 and MAC1 supported")); 236188808Sgonzo 237188808Sgonzo /* 238188808Sgonzo * Get which PHY of 5 available we should use for this unit 239188808Sgonzo */ 240188808Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 241199234Sgonzo "phymask", &phymask) != 0) { 242188808Sgonzo /* 243188808Sgonzo * Use port 4 (WAN) for GE0. For any other port use 244188808Sgonzo * its PHY the same as its unit number 245188808Sgonzo */ 246188808Sgonzo if (sc->arge_mac_unit == 0) 247199234Sgonzo phymask = (1 << 4); 248188808Sgonzo else 249199234Sgonzo /* Use all phys up to 4 */ 250199234Sgonzo phymask = (1 << 4) - 1; 251188808Sgonzo 252199234Sgonzo device_printf(dev, "No PHY specified, using mask %d\n", phymask); 253188808Sgonzo } 254188808Sgonzo 255199234Sgonzo /* 256199234Sgonzo * Get default media & duplex mode, by default its Base100T 257199234Sgonzo * and full duplex 258199234Sgonzo */ 259199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 260199234Sgonzo "media", &hint) != 0) 261199234Sgonzo hint = 0; 262188808Sgonzo 263199234Sgonzo if (hint == 1000) 264199234Sgonzo sc->arge_media_type = IFM_1000_T; 265199234Sgonzo else 266199234Sgonzo sc->arge_media_type = IFM_100_TX; 267199234Sgonzo 268199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 269199234Sgonzo "fduplex", &hint) != 0) 270199234Sgonzo hint = 1; 271199234Sgonzo 272199234Sgonzo if (hint) 273199234Sgonzo sc->arge_duplex_mode = IFM_FDX; 274199234Sgonzo else 275199234Sgonzo sc->arge_duplex_mode = 0; 276199234Sgonzo 277199234Sgonzo sc->arge_phymask = phymask; 278199234Sgonzo 279188808Sgonzo mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 280188808Sgonzo MTX_DEF); 281188808Sgonzo callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0); 282188808Sgonzo TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc); 283188808Sgonzo 284188808Sgonzo /* Map control/status registers. */ 285188808Sgonzo sc->arge_rid = 0; 286188808Sgonzo sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 287188808Sgonzo &sc->arge_rid, RF_ACTIVE); 288188808Sgonzo 289188808Sgonzo if (sc->arge_res == NULL) { 290188808Sgonzo device_printf(dev, "couldn't map memory\n"); 291188808Sgonzo error = ENXIO; 292188808Sgonzo goto fail; 293188808Sgonzo } 294188808Sgonzo 295188808Sgonzo /* Allocate interrupts */ 296188808Sgonzo rid = 0; 297188808Sgonzo sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 298188808Sgonzo RF_SHAREABLE | RF_ACTIVE); 299188808Sgonzo 300188808Sgonzo if (sc->arge_irq == NULL) { 301188808Sgonzo device_printf(dev, "couldn't map interrupt\n"); 302188808Sgonzo error = ENXIO; 303188808Sgonzo goto fail; 304188808Sgonzo } 305188808Sgonzo 306188808Sgonzo /* Allocate ifnet structure. */ 307188808Sgonzo ifp = sc->arge_ifp = if_alloc(IFT_ETHER); 308188808Sgonzo 309188808Sgonzo if (ifp == NULL) { 310188808Sgonzo device_printf(dev, "couldn't allocate ifnet structure\n"); 311188808Sgonzo error = ENOSPC; 312188808Sgonzo goto fail; 313188808Sgonzo } 314188808Sgonzo 315188808Sgonzo ifp->if_softc = sc; 316188808Sgonzo if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 317188808Sgonzo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 318188808Sgonzo ifp->if_ioctl = arge_ioctl; 319188808Sgonzo ifp->if_start = arge_start; 320188808Sgonzo ifp->if_init = arge_init; 321198932Sgonzo sc->arge_if_flags = ifp->if_flags; 322188808Sgonzo 323188808Sgonzo /* XXX: add real size */ 324207554Ssobomax IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 325207554Ssobomax ifp->if_snd.ifq_maxlen = ifqmaxlen; 326188808Sgonzo IFQ_SET_READY(&ifp->if_snd); 327188808Sgonzo 328188808Sgonzo ifp->if_capenable = ifp->if_capabilities; 329192783Sgonzo#ifdef DEVICE_POLLING 330192783Sgonzo ifp->if_capabilities |= IFCAP_POLLING; 331192783Sgonzo#endif 332188808Sgonzo 333192179Sgonzo is_base_mac_empty = 1; 334192179Sgonzo for (i = 0; i < ETHER_ADDR_LEN; i++) { 335192179Sgonzo eaddr[i] = ar711_base_mac[i] & 0xff; 336192179Sgonzo if (eaddr[i] != 0) 337192179Sgonzo is_base_mac_empty = 0; 338192179Sgonzo } 339188808Sgonzo 340192179Sgonzo if (is_base_mac_empty) { 341192179Sgonzo /* 342192179Sgonzo * No MAC address configured. Generate the random one. 343192179Sgonzo */ 344198933Sgonzo if (bootverbose) 345192179Sgonzo device_printf(dev, 346192179Sgonzo "Generating random ethernet address.\n"); 347192179Sgonzo 348192179Sgonzo rnd = arc4random(); 349192179Sgonzo eaddr[0] = 'b'; 350192179Sgonzo eaddr[1] = 's'; 351192179Sgonzo eaddr[2] = 'd'; 352192179Sgonzo eaddr[3] = (rnd >> 24) & 0xff; 353192179Sgonzo eaddr[4] = (rnd >> 16) & 0xff; 354192179Sgonzo eaddr[5] = (rnd >> 8) & 0xff; 355192179Sgonzo } 356192179Sgonzo 357198970Sgonzo if (sc->arge_mac_unit != 0) 358198970Sgonzo eaddr[5] += sc->arge_mac_unit; 359198970Sgonzo 360188808Sgonzo if (arge_dma_alloc(sc) != 0) { 361188808Sgonzo error = ENXIO; 362188808Sgonzo goto fail; 363188808Sgonzo } 364188808Sgonzo 365192569Sdwhite /* Initialize the MAC block */ 366192569Sdwhite 367192569Sdwhite /* Step 1. Soft-reset MAC */ 368192569Sdwhite ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET); 369192569Sdwhite DELAY(20); 370192569Sdwhite 371192569Sdwhite /* Step 2. Punt the MAC core from the central reset register */ 372211477Sadrian ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 373192569Sdwhite DELAY(100); 374211477Sadrian ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 375192569Sdwhite 376192569Sdwhite /* Step 3. Reconfigure MAC block */ 377188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG1, 378188808Sgonzo MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE | 379188808Sgonzo MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE); 380188808Sgonzo 381188808Sgonzo reg = ARGE_READ(sc, AR71XX_MAC_CFG2); 382188808Sgonzo reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ; 383188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg); 384188808Sgonzo 385188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536); 386188808Sgonzo 387188808Sgonzo /* Reset MII bus */ 388188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET); 389188808Sgonzo DELAY(100); 390188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28); 391188808Sgonzo DELAY(100); 392188808Sgonzo 393188808Sgonzo /* 394188808Sgonzo * Set all Ethernet address registers to the same initial values 395188808Sgonzo * set all four addresses to 66-88-aa-cc-dd-ee 396188808Sgonzo */ 397192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 398192783Sgonzo (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]); 399192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]); 400188808Sgonzo 401188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 402188808Sgonzo FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT); 403188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000); 404188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff); 405188808Sgonzo 406192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 407192783Sgonzo FIFO_RX_FILTMATCH_DEFAULT); 408188808Sgonzo 409192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 410192783Sgonzo FIFO_RX_FILTMASK_DEFAULT); 411188808Sgonzo 412199234Sgonzo /* 413199234Sgonzo * Check if we have single-PHY MAC or multi-PHY 414199234Sgonzo */ 415199234Sgonzo phys_total = 0; 416199234Sgonzo for (i = 0; i < ARGE_NPHY; i++) 417199234Sgonzo if (phymask & (1 << i)) 418199234Sgonzo phys_total ++; 419199234Sgonzo 420199234Sgonzo if (phys_total == 0) { 421199234Sgonzo error = EINVAL; 422188808Sgonzo goto fail; 423188808Sgonzo } 424188808Sgonzo 425199234Sgonzo if (phys_total == 1) { 426199234Sgonzo /* Do MII setup. */ 427213894Smarius error = mii_attach(dev, &sc->arge_miibus, ifp, 428213894Smarius arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK, 429213894Smarius MII_PHY_ANY, MII_OFFSET_ANY, 0); 430213894Smarius if (error != 0) { 431213894Smarius device_printf(dev, "attaching PHYs failed\n"); 432199234Sgonzo goto fail; 433199234Sgonzo } 434199234Sgonzo } 435199234Sgonzo else { 436199234Sgonzo ifmedia_init(&sc->arge_ifmedia, 0, 437199234Sgonzo arge_multiphy_mediachange, 438199234Sgonzo arge_multiphy_mediastatus); 439199234Sgonzo ifmedia_add(&sc->arge_ifmedia, 440199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode, 441199234Sgonzo 0, NULL); 442199234Sgonzo ifmedia_set(&sc->arge_ifmedia, 443199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode); 444199234Sgonzo arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode); 445199234Sgonzo } 446199234Sgonzo 447188808Sgonzo /* Call MI attach routine. */ 448188808Sgonzo ether_ifattach(ifp, eaddr); 449188808Sgonzo 450188808Sgonzo /* Hook interrupt last to avoid having to lock softc */ 451188808Sgonzo error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE, 452188808Sgonzo arge_intr_filter, arge_intr, sc, &sc->arge_intrhand); 453188808Sgonzo 454188808Sgonzo if (error) { 455188808Sgonzo device_printf(dev, "couldn't set up irq\n"); 456188808Sgonzo ether_ifdetach(ifp); 457188808Sgonzo goto fail; 458188808Sgonzo } 459188808Sgonzo 460209802Sadrian /* setup sysctl variables */ 461209802Sadrian arge_attach_sysctl(dev); 462209802Sadrian 463188808Sgonzofail: 464188808Sgonzo if (error) 465188808Sgonzo arge_detach(dev); 466188808Sgonzo 467188808Sgonzo return (error); 468188808Sgonzo} 469188808Sgonzo 470188808Sgonzostatic int 471188808Sgonzoarge_detach(device_t dev) 472188808Sgonzo{ 473192783Sgonzo struct arge_softc *sc = device_get_softc(dev); 474188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 475188808Sgonzo 476188808Sgonzo KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized")); 477188808Sgonzo 478188808Sgonzo /* These should only be active if attach succeeded */ 479188808Sgonzo if (device_is_attached(dev)) { 480188808Sgonzo ARGE_LOCK(sc); 481188808Sgonzo sc->arge_detach = 1; 482192783Sgonzo#ifdef DEVICE_POLLING 483192783Sgonzo if (ifp->if_capenable & IFCAP_POLLING) 484192783Sgonzo ether_poll_deregister(ifp); 485192783Sgonzo#endif 486192783Sgonzo 487188808Sgonzo arge_stop(sc); 488188808Sgonzo ARGE_UNLOCK(sc); 489188808Sgonzo taskqueue_drain(taskqueue_swi, &sc->arge_link_task); 490188808Sgonzo ether_ifdetach(ifp); 491188808Sgonzo } 492188808Sgonzo 493188808Sgonzo if (sc->arge_miibus) 494188808Sgonzo device_delete_child(dev, sc->arge_miibus); 495199234Sgonzo 496188808Sgonzo bus_generic_detach(dev); 497188808Sgonzo 498188808Sgonzo if (sc->arge_intrhand) 499188808Sgonzo bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand); 500188808Sgonzo 501188808Sgonzo if (sc->arge_res) 502188808Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 503188808Sgonzo sc->arge_res); 504188808Sgonzo 505188808Sgonzo if (ifp) 506188808Sgonzo if_free(ifp); 507188808Sgonzo 508188808Sgonzo arge_dma_free(sc); 509188808Sgonzo 510188808Sgonzo mtx_destroy(&sc->arge_mtx); 511188808Sgonzo 512188808Sgonzo return (0); 513188808Sgonzo 514188808Sgonzo} 515188808Sgonzo 516188808Sgonzostatic int 517188808Sgonzoarge_suspend(device_t dev) 518188808Sgonzo{ 519188808Sgonzo 520188808Sgonzo panic("%s", __func__); 521188808Sgonzo return 0; 522188808Sgonzo} 523188808Sgonzo 524188808Sgonzostatic int 525188808Sgonzoarge_resume(device_t dev) 526188808Sgonzo{ 527188808Sgonzo 528188808Sgonzo panic("%s", __func__); 529188808Sgonzo return 0; 530188808Sgonzo} 531188808Sgonzo 532194059Sgonzostatic int 533188808Sgonzoarge_shutdown(device_t dev) 534188808Sgonzo{ 535188808Sgonzo struct arge_softc *sc; 536188808Sgonzo 537188808Sgonzo sc = device_get_softc(dev); 538188808Sgonzo 539188808Sgonzo ARGE_LOCK(sc); 540188808Sgonzo arge_stop(sc); 541188808Sgonzo ARGE_UNLOCK(sc); 542194059Sgonzo 543194059Sgonzo return (0); 544188808Sgonzo} 545188808Sgonzo 546188808Sgonzostatic int 547188808Sgonzoarge_miibus_readreg(device_t dev, int phy, int reg) 548188808Sgonzo{ 549188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 550188808Sgonzo int i, result; 551196794Sgonzo uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 552188808Sgonzo | (reg & MAC_MII_REG_MASK); 553188808Sgonzo 554199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 555188808Sgonzo return (0); 556188808Sgonzo 557199038Sgonzo mtx_lock(&miibus_mtx); 558199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 559199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 560199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); 561188808Sgonzo 562188808Sgonzo i = ARGE_MII_TIMEOUT; 563199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 564188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 565188808Sgonzo DELAY(5); 566188808Sgonzo 567188808Sgonzo if (i < 0) { 568199038Sgonzo mtx_unlock(&miibus_mtx); 569188808Sgonzo dprintf("%s timedout\n", __func__); 570188808Sgonzo /* XXX: return ERRNO istead? */ 571188808Sgonzo return (-1); 572188808Sgonzo } 573188808Sgonzo 574199038Sgonzo result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; 575199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 576199038Sgonzo mtx_unlock(&miibus_mtx); 577199038Sgonzo 578188808Sgonzo dprintf("%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 579188808Sgonzo phy, reg, addr, result); 580188808Sgonzo 581188808Sgonzo return (result); 582188808Sgonzo} 583188808Sgonzo 584188808Sgonzostatic int 585188808Sgonzoarge_miibus_writereg(device_t dev, int phy, int reg, int data) 586188808Sgonzo{ 587188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 588188808Sgonzo int i; 589196794Sgonzo uint32_t addr = 590196794Sgonzo (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK); 591188808Sgonzo 592199038Sgonzo 593199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 594199038Sgonzo return (-1); 595199038Sgonzo 596188808Sgonzo dprintf("%s: phy=%d, reg=%02x, value=%04x\n", __func__, 597188808Sgonzo phy, reg, data); 598188808Sgonzo 599199038Sgonzo mtx_lock(&miibus_mtx); 600199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 601199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data); 602188808Sgonzo 603188808Sgonzo i = ARGE_MII_TIMEOUT; 604199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 605188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 606188808Sgonzo DELAY(5); 607188808Sgonzo 608199038Sgonzo mtx_unlock(&miibus_mtx); 609199038Sgonzo 610188808Sgonzo if (i < 0) { 611188808Sgonzo dprintf("%s timedout\n", __func__); 612188808Sgonzo /* XXX: return ERRNO istead? */ 613188808Sgonzo return (-1); 614188808Sgonzo } 615188808Sgonzo 616188808Sgonzo return (0); 617188808Sgonzo} 618188808Sgonzo 619188808Sgonzostatic void 620188808Sgonzoarge_miibus_statchg(device_t dev) 621188808Sgonzo{ 622188808Sgonzo struct arge_softc *sc; 623188808Sgonzo 624188808Sgonzo sc = device_get_softc(dev); 625188808Sgonzo taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task); 626188808Sgonzo} 627188808Sgonzo 628188808Sgonzostatic void 629188808Sgonzoarge_link_task(void *arg, int pending) 630188808Sgonzo{ 631188808Sgonzo struct arge_softc *sc; 632188808Sgonzo struct mii_data *mii; 633188808Sgonzo struct ifnet *ifp; 634199234Sgonzo uint32_t media, duplex; 635188808Sgonzo 636188808Sgonzo sc = (struct arge_softc *)arg; 637188808Sgonzo 638188808Sgonzo ARGE_LOCK(sc); 639188808Sgonzo mii = device_get_softc(sc->arge_miibus); 640188808Sgonzo ifp = sc->arge_ifp; 641188808Sgonzo if (mii == NULL || ifp == NULL || 642188808Sgonzo (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 643188808Sgonzo ARGE_UNLOCK(sc); 644188808Sgonzo return; 645188808Sgonzo } 646188808Sgonzo 647188808Sgonzo if (mii->mii_media_status & IFM_ACTIVE) { 648188808Sgonzo 649188808Sgonzo media = IFM_SUBTYPE(mii->mii_media_active); 650188808Sgonzo 651188808Sgonzo if (media != IFM_NONE) { 652188808Sgonzo sc->arge_link_status = 1; 653199234Sgonzo duplex = mii->mii_media_active & IFM_GMASK; 654199234Sgonzo arge_set_pll(sc, media, duplex); 655199234Sgonzo } 656199234Sgonzo } else 657199234Sgonzo sc->arge_link_status = 0; 658188808Sgonzo 659199234Sgonzo ARGE_UNLOCK(sc); 660199234Sgonzo} 661192783Sgonzo 662199234Sgonzostatic void 663199234Sgonzoarge_set_pll(struct arge_softc *sc, int media, int duplex) 664199234Sgonzo{ 665211511Sadrian uint32_t cfg, ifcontrol, rx_filtmask; 666211511Sadrian int if_speed; 667192783Sgonzo 668199234Sgonzo cfg = ARGE_READ(sc, AR71XX_MAC_CFG2); 669199234Sgonzo cfg &= ~(MAC_CFG2_IFACE_MODE_1000 670199234Sgonzo | MAC_CFG2_IFACE_MODE_10_100 671199234Sgonzo | MAC_CFG2_FULL_DUPLEX); 672188808Sgonzo 673199234Sgonzo if (duplex == IFM_FDX) 674199234Sgonzo cfg |= MAC_CFG2_FULL_DUPLEX; 675188808Sgonzo 676199234Sgonzo ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL); 677199234Sgonzo ifcontrol &= ~MAC_IFCONTROL_SPEED; 678199234Sgonzo rx_filtmask = 679199234Sgonzo ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK); 680199234Sgonzo rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE; 681188808Sgonzo 682199234Sgonzo switch(media) { 683199234Sgonzo case IFM_10_T: 684199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 685211511Sadrian if_speed = 10; 686199234Sgonzo break; 687199234Sgonzo case IFM_100_TX: 688199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 689199234Sgonzo ifcontrol |= MAC_IFCONTROL_SPEED; 690211511Sadrian if_speed = 100; 691199234Sgonzo break; 692199234Sgonzo case IFM_1000_T: 693199234Sgonzo case IFM_1000_SX: 694199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_1000; 695199234Sgonzo rx_filtmask |= FIFO_RX_MASK_BYTE_MODE; 696211511Sadrian if_speed = 1000; 697199234Sgonzo break; 698199234Sgonzo default: 699211511Sadrian if_speed = 100; 700199234Sgonzo device_printf(sc->arge_dev, 701199234Sgonzo "Unknown media %d\n", media); 702199234Sgonzo } 703188808Sgonzo 704199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, 705199234Sgonzo 0x008001ff); 706188808Sgonzo 707199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg); 708199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol); 709199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 710199234Sgonzo rx_filtmask); 711188808Sgonzo 712199234Sgonzo /* set PLL registers */ 713211511Sadrian if (sc->arge_mac_unit == 0) 714211511Sadrian ar71xx_device_set_pll_ge0(if_speed); 715211511Sadrian else 716211511Sadrian ar71xx_device_set_pll_ge1(if_speed); 717188808Sgonzo} 718188808Sgonzo 719199234Sgonzo 720188808Sgonzostatic void 721188808Sgonzoarge_reset_dma(struct arge_softc *sc) 722188808Sgonzo{ 723188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0); 724188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0); 725188808Sgonzo 726188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0); 727188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0); 728188808Sgonzo 729188808Sgonzo /* Clear all possible RX interrupts */ 730192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD) 731188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 732188808Sgonzo 733188808Sgonzo /* 734188808Sgonzo * Clear all possible TX interrupts 735188808Sgonzo */ 736192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT) 737188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 738188808Sgonzo 739188808Sgonzo /* 740188808Sgonzo * Now Rx/Tx errors 741188808Sgonzo */ 742188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 743188808Sgonzo DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW); 744188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 745188808Sgonzo DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN); 746188808Sgonzo} 747188808Sgonzo 748188808Sgonzo 749188808Sgonzo 750188808Sgonzostatic void 751188808Sgonzoarge_init(void *xsc) 752188808Sgonzo{ 753188808Sgonzo struct arge_softc *sc = xsc; 754188808Sgonzo 755188808Sgonzo ARGE_LOCK(sc); 756188808Sgonzo arge_init_locked(sc); 757188808Sgonzo ARGE_UNLOCK(sc); 758188808Sgonzo} 759188808Sgonzo 760188808Sgonzostatic void 761188808Sgonzoarge_init_locked(struct arge_softc *sc) 762188808Sgonzo{ 763188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 764188808Sgonzo struct mii_data *mii; 765188808Sgonzo 766188808Sgonzo ARGE_LOCK_ASSERT(sc); 767188808Sgonzo 768188808Sgonzo arge_stop(sc); 769188808Sgonzo 770188808Sgonzo /* Init circular RX list. */ 771188808Sgonzo if (arge_rx_ring_init(sc) != 0) { 772188808Sgonzo device_printf(sc->arge_dev, 773188808Sgonzo "initialization failed: no memory for rx buffers\n"); 774188808Sgonzo arge_stop(sc); 775188808Sgonzo return; 776188808Sgonzo } 777188808Sgonzo 778188808Sgonzo /* Init tx descriptors. */ 779188808Sgonzo arge_tx_ring_init(sc); 780188808Sgonzo 781188808Sgonzo arge_reset_dma(sc); 782188808Sgonzo 783188808Sgonzo 784199234Sgonzo if (sc->arge_miibus) { 785199234Sgonzo sc->arge_link_status = 0; 786199234Sgonzo mii = device_get_softc(sc->arge_miibus); 787199234Sgonzo mii_mediachg(mii); 788199234Sgonzo } 789199234Sgonzo else { 790199234Sgonzo /* 791199234Sgonzo * Sun always shines over multiPHY interface 792199234Sgonzo */ 793199234Sgonzo sc->arge_link_status = 1; 794199234Sgonzo } 795199234Sgonzo 796188808Sgonzo ifp->if_drv_flags |= IFF_DRV_RUNNING; 797188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 798188808Sgonzo 799199234Sgonzo if (sc->arge_miibus) 800199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 801192783Sgonzo 802188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0)); 803188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0)); 804188808Sgonzo 805188808Sgonzo /* Start listening */ 806188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 807188808Sgonzo 808188808Sgonzo /* Enable interrupts */ 809188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 810188808Sgonzo} 811188808Sgonzo 812188808Sgonzo/* 813209807Sadrian * Return whether the mbuf chain is correctly aligned 814209807Sadrian * for the arge TX engine. 815209807Sadrian * 816209807Sadrian * The TX engine requires each fragment to be aligned to a 817209807Sadrian * 4 byte boundary and the size of each fragment except 818209807Sadrian * the last to be a multiple of 4 bytes. 819209807Sadrian */ 820209807Sadrianstatic int 821209807Sadrianarge_mbuf_chain_is_tx_aligned(struct mbuf *m0) 822209807Sadrian{ 823209807Sadrian struct mbuf *m; 824209807Sadrian 825209807Sadrian for (m = m0; m != NULL; m = m->m_next) { 826209807Sadrian if((mtod(m, intptr_t) & 3) != 0) 827209807Sadrian return 0; 828209807Sadrian if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) 829209807Sadrian return 0; 830209807Sadrian } 831209807Sadrian return 1; 832209807Sadrian} 833209807Sadrian 834209807Sadrian/* 835188808Sgonzo * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 836188808Sgonzo * pointers to the fragment pointers. 837188808Sgonzo */ 838188808Sgonzostatic int 839188808Sgonzoarge_encap(struct arge_softc *sc, struct mbuf **m_head) 840188808Sgonzo{ 841188808Sgonzo struct arge_txdesc *txd; 842188808Sgonzo struct arge_desc *desc, *prev_desc; 843188808Sgonzo bus_dma_segment_t txsegs[ARGE_MAXFRAGS]; 844192569Sdwhite int error, i, nsegs, prod, prev_prod; 845192783Sgonzo struct mbuf *m; 846188808Sgonzo 847188808Sgonzo ARGE_LOCK_ASSERT(sc); 848188808Sgonzo 849192783Sgonzo /* 850192783Sgonzo * Fix mbuf chain, all fragments should be 4 bytes aligned and 851192783Sgonzo * even 4 bytes 852192783Sgonzo */ 853192783Sgonzo m = *m_head; 854209807Sadrian if (! arge_mbuf_chain_is_tx_aligned(m)) { 855209809Sadrian sc->stats.tx_pkts_unaligned++; 856192783Sgonzo m = m_defrag(*m_head, M_DONTWAIT); 857192783Sgonzo if (m == NULL) { 858192783Sgonzo *m_head = NULL; 859192783Sgonzo return (ENOBUFS); 860192783Sgonzo } 861192783Sgonzo *m_head = m; 862209809Sadrian } else 863209809Sadrian sc->stats.tx_pkts_aligned++; 864192783Sgonzo 865188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 866188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[prod]; 867188808Sgonzo error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 868188808Sgonzo txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 869188808Sgonzo 870188808Sgonzo if (error == EFBIG) { 871188808Sgonzo panic("EFBIG"); 872188808Sgonzo } else if (error != 0) 873188808Sgonzo return (error); 874188808Sgonzo 875188808Sgonzo if (nsegs == 0) { 876188808Sgonzo m_freem(*m_head); 877188808Sgonzo *m_head = NULL; 878188808Sgonzo return (EIO); 879188808Sgonzo } 880188808Sgonzo 881188808Sgonzo /* Check number of available descriptors. */ 882188808Sgonzo if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) { 883188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 884188808Sgonzo return (ENOBUFS); 885188808Sgonzo } 886188808Sgonzo 887188808Sgonzo txd->tx_m = *m_head; 888188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 889188808Sgonzo BUS_DMASYNC_PREWRITE); 890188808Sgonzo 891188808Sgonzo /* 892188808Sgonzo * Make a list of descriptors for this packet. DMA controller will 893188808Sgonzo * walk through it while arge_link is not zero. 894188808Sgonzo */ 895188808Sgonzo prev_prod = prod; 896188808Sgonzo desc = prev_desc = NULL; 897188808Sgonzo for (i = 0; i < nsegs; i++) { 898188808Sgonzo desc = &sc->arge_rdata.arge_tx_ring[prod]; 899188808Sgonzo desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len); 900188808Sgonzo 901192783Sgonzo if (txsegs[i].ds_addr & 3) 902192783Sgonzo panic("TX packet address unaligned\n"); 903192783Sgonzo 904188808Sgonzo desc->packet_addr = txsegs[i].ds_addr; 905192783Sgonzo 906188808Sgonzo /* link with previous descriptor */ 907188808Sgonzo if (prev_desc) 908188808Sgonzo prev_desc->packet_ctrl |= ARGE_DESC_MORE; 909188808Sgonzo 910188808Sgonzo sc->arge_cdata.arge_tx_cnt++; 911188808Sgonzo prev_desc = desc; 912188808Sgonzo ARGE_INC(prod, ARGE_TX_RING_COUNT); 913188808Sgonzo } 914188808Sgonzo 915188808Sgonzo /* Update producer index. */ 916188808Sgonzo sc->arge_cdata.arge_tx_prod = prod; 917188808Sgonzo 918188808Sgonzo /* Sync descriptors. */ 919188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 920188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 921188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 922188808Sgonzo 923188808Sgonzo /* Start transmitting */ 924188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN); 925188808Sgonzo return (0); 926188808Sgonzo} 927188808Sgonzo 928188808Sgonzostatic void 929188808Sgonzoarge_start(struct ifnet *ifp) 930188808Sgonzo{ 931188808Sgonzo struct arge_softc *sc; 932188808Sgonzo 933188808Sgonzo sc = ifp->if_softc; 934188808Sgonzo 935188808Sgonzo ARGE_LOCK(sc); 936188808Sgonzo arge_start_locked(ifp); 937188808Sgonzo ARGE_UNLOCK(sc); 938188808Sgonzo} 939188808Sgonzo 940188808Sgonzostatic void 941188808Sgonzoarge_start_locked(struct ifnet *ifp) 942188808Sgonzo{ 943188808Sgonzo struct arge_softc *sc; 944188808Sgonzo struct mbuf *m_head; 945188808Sgonzo int enq; 946188808Sgonzo 947188808Sgonzo sc = ifp->if_softc; 948188808Sgonzo 949188808Sgonzo ARGE_LOCK_ASSERT(sc); 950188808Sgonzo 951188808Sgonzo if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 952188808Sgonzo IFF_DRV_RUNNING || sc->arge_link_status == 0 ) 953188808Sgonzo return; 954188808Sgonzo 955188808Sgonzo arge_flush_ddr(sc); 956188808Sgonzo 957188808Sgonzo for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 958188808Sgonzo sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) { 959188808Sgonzo IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 960188808Sgonzo if (m_head == NULL) 961188808Sgonzo break; 962188808Sgonzo 963188808Sgonzo 964188808Sgonzo /* 965188808Sgonzo * Pack the data into the transmit ring. 966188808Sgonzo */ 967188808Sgonzo if (arge_encap(sc, &m_head)) { 968188808Sgonzo if (m_head == NULL) 969188808Sgonzo break; 970188808Sgonzo IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 971188808Sgonzo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 972188808Sgonzo break; 973188808Sgonzo } 974188808Sgonzo 975188808Sgonzo enq++; 976188808Sgonzo /* 977188808Sgonzo * If there's a BPF listener, bounce a copy of this frame 978188808Sgonzo * to him. 979188808Sgonzo */ 980188808Sgonzo ETHER_BPF_MTAP(ifp, m_head); 981188808Sgonzo } 982188808Sgonzo} 983188808Sgonzo 984188808Sgonzostatic void 985188808Sgonzoarge_stop(struct arge_softc *sc) 986188808Sgonzo{ 987188808Sgonzo struct ifnet *ifp; 988188808Sgonzo 989188808Sgonzo ARGE_LOCK_ASSERT(sc); 990188808Sgonzo 991188808Sgonzo ifp = sc->arge_ifp; 992188808Sgonzo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 993199234Sgonzo if (sc->arge_miibus) 994199234Sgonzo callout_stop(&sc->arge_stat_callout); 995188808Sgonzo 996188808Sgonzo /* mask out interrupts */ 997188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 998188808Sgonzo 999188808Sgonzo arge_reset_dma(sc); 1000188808Sgonzo} 1001188808Sgonzo 1002188808Sgonzo 1003188808Sgonzostatic int 1004188808Sgonzoarge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1005188808Sgonzo{ 1006188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1007188808Sgonzo struct ifreq *ifr = (struct ifreq *) data; 1008188808Sgonzo struct mii_data *mii; 1009188808Sgonzo int error; 1010192783Sgonzo#ifdef DEVICE_POLLING 1011192783Sgonzo int mask; 1012192783Sgonzo#endif 1013188808Sgonzo 1014188808Sgonzo switch (command) { 1015188808Sgonzo case SIOCSIFFLAGS: 1016198932Sgonzo ARGE_LOCK(sc); 1017198932Sgonzo if ((ifp->if_flags & IFF_UP) != 0) { 1018198932Sgonzo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1019198932Sgonzo if (((ifp->if_flags ^ sc->arge_if_flags) 1020198939Sgonzo & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1021198939Sgonzo /* XXX: handle promisc & multi flags */ 1022198939Sgonzo } 1023198939Sgonzo 1024198932Sgonzo } else { 1025198932Sgonzo if (!sc->arge_detach) 1026198932Sgonzo arge_init_locked(sc); 1027198932Sgonzo } 1028198932Sgonzo } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1029198932Sgonzo ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1030198932Sgonzo arge_stop(sc); 1031198932Sgonzo } 1032198932Sgonzo sc->arge_if_flags = ifp->if_flags; 1033198932Sgonzo ARGE_UNLOCK(sc); 1034188808Sgonzo error = 0; 1035188808Sgonzo break; 1036188808Sgonzo case SIOCADDMULTI: 1037188808Sgonzo case SIOCDELMULTI: 1038198932Sgonzo /* XXX: implement SIOCDELMULTI */ 1039188808Sgonzo error = 0; 1040188808Sgonzo break; 1041188808Sgonzo case SIOCGIFMEDIA: 1042188808Sgonzo case SIOCSIFMEDIA: 1043199234Sgonzo if (sc->arge_miibus) { 1044199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1045199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1046199234Sgonzo } 1047199234Sgonzo else 1048199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command); 1049188808Sgonzo break; 1050198933Sgonzo case SIOCSIFCAP: 1051198932Sgonzo /* XXX: Check other capabilities */ 1052192783Sgonzo#ifdef DEVICE_POLLING 1053198933Sgonzo mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1054198933Sgonzo if (mask & IFCAP_POLLING) { 1055198933Sgonzo if (ifr->ifr_reqcap & IFCAP_POLLING) { 1056192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1057198933Sgonzo error = ether_poll_register(arge_poll, ifp); 1058198933Sgonzo if (error) 1059198933Sgonzo return error; 1060198933Sgonzo ARGE_LOCK(sc); 1061198933Sgonzo ifp->if_capenable |= IFCAP_POLLING; 1062198933Sgonzo ARGE_UNLOCK(sc); 1063198933Sgonzo } else { 1064192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1065198933Sgonzo error = ether_poll_deregister(ifp); 1066198933Sgonzo ARGE_LOCK(sc); 1067198933Sgonzo ifp->if_capenable &= ~IFCAP_POLLING; 1068198933Sgonzo ARGE_UNLOCK(sc); 1069198933Sgonzo } 1070198933Sgonzo } 1071198932Sgonzo error = 0; 1072198933Sgonzo break; 1073192783Sgonzo#endif 1074188808Sgonzo default: 1075188808Sgonzo error = ether_ioctl(ifp, command, data); 1076188808Sgonzo break; 1077188808Sgonzo } 1078188808Sgonzo 1079188808Sgonzo return (error); 1080188808Sgonzo} 1081188808Sgonzo 1082188808Sgonzo/* 1083188808Sgonzo * Set media options. 1084188808Sgonzo */ 1085188808Sgonzostatic int 1086188808Sgonzoarge_ifmedia_upd(struct ifnet *ifp) 1087188808Sgonzo{ 1088188808Sgonzo struct arge_softc *sc; 1089188808Sgonzo struct mii_data *mii; 1090188808Sgonzo struct mii_softc *miisc; 1091188808Sgonzo int error; 1092188808Sgonzo 1093188808Sgonzo sc = ifp->if_softc; 1094188808Sgonzo ARGE_LOCK(sc); 1095188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1096188808Sgonzo if (mii->mii_instance) { 1097188808Sgonzo LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1098188808Sgonzo mii_phy_reset(miisc); 1099188808Sgonzo } 1100188808Sgonzo error = mii_mediachg(mii); 1101188808Sgonzo ARGE_UNLOCK(sc); 1102188808Sgonzo 1103188808Sgonzo return (error); 1104188808Sgonzo} 1105188808Sgonzo 1106188808Sgonzo/* 1107188808Sgonzo * Report current media status. 1108188808Sgonzo */ 1109188808Sgonzostatic void 1110188808Sgonzoarge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1111188808Sgonzo{ 1112188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1113188808Sgonzo struct mii_data *mii; 1114188808Sgonzo 1115188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1116188808Sgonzo ARGE_LOCK(sc); 1117188808Sgonzo mii_pollstat(mii); 1118188808Sgonzo ARGE_UNLOCK(sc); 1119188808Sgonzo ifmr->ifm_active = mii->mii_media_active; 1120188808Sgonzo ifmr->ifm_status = mii->mii_media_status; 1121188808Sgonzo} 1122188808Sgonzo 1123188808Sgonzostruct arge_dmamap_arg { 1124188808Sgonzo bus_addr_t arge_busaddr; 1125188808Sgonzo}; 1126188808Sgonzo 1127188808Sgonzostatic void 1128188808Sgonzoarge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1129188808Sgonzo{ 1130188808Sgonzo struct arge_dmamap_arg *ctx; 1131188808Sgonzo 1132188808Sgonzo if (error != 0) 1133188808Sgonzo return; 1134188808Sgonzo ctx = arg; 1135188808Sgonzo ctx->arge_busaddr = segs[0].ds_addr; 1136188808Sgonzo} 1137188808Sgonzo 1138188808Sgonzostatic int 1139188808Sgonzoarge_dma_alloc(struct arge_softc *sc) 1140188808Sgonzo{ 1141188808Sgonzo struct arge_dmamap_arg ctx; 1142188808Sgonzo struct arge_txdesc *txd; 1143188808Sgonzo struct arge_rxdesc *rxd; 1144188808Sgonzo int error, i; 1145188808Sgonzo 1146188808Sgonzo /* Create parent DMA tag. */ 1147188808Sgonzo error = bus_dma_tag_create( 1148188808Sgonzo bus_get_dma_tag(sc->arge_dev), /* parent */ 1149188808Sgonzo 1, 0, /* alignment, boundary */ 1150188808Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1151188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1152188808Sgonzo NULL, NULL, /* filter, filterarg */ 1153188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1154188808Sgonzo 0, /* nsegments */ 1155188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1156188808Sgonzo 0, /* flags */ 1157188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1158188808Sgonzo &sc->arge_cdata.arge_parent_tag); 1159188808Sgonzo if (error != 0) { 1160188808Sgonzo device_printf(sc->arge_dev, "failed to create parent DMA tag\n"); 1161188808Sgonzo goto fail; 1162188808Sgonzo } 1163188808Sgonzo /* Create tag for Tx ring. */ 1164188808Sgonzo error = bus_dma_tag_create( 1165188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1166188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1167188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1168188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1169188808Sgonzo NULL, NULL, /* filter, filterarg */ 1170188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsize */ 1171188808Sgonzo 1, /* nsegments */ 1172188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsegsize */ 1173188808Sgonzo 0, /* flags */ 1174188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1175188808Sgonzo &sc->arge_cdata.arge_tx_ring_tag); 1176188808Sgonzo if (error != 0) { 1177188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n"); 1178188808Sgonzo goto fail; 1179188808Sgonzo } 1180188808Sgonzo 1181188808Sgonzo /* Create tag for Rx ring. */ 1182188808Sgonzo error = bus_dma_tag_create( 1183188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1184188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1185188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1186188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1187188808Sgonzo NULL, NULL, /* filter, filterarg */ 1188188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsize */ 1189188808Sgonzo 1, /* nsegments */ 1190188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsegsize */ 1191188808Sgonzo 0, /* flags */ 1192188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1193188808Sgonzo &sc->arge_cdata.arge_rx_ring_tag); 1194188808Sgonzo if (error != 0) { 1195188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n"); 1196188808Sgonzo goto fail; 1197188808Sgonzo } 1198188808Sgonzo 1199188808Sgonzo /* Create tag for Tx buffers. */ 1200188808Sgonzo error = bus_dma_tag_create( 1201188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1202188808Sgonzo sizeof(uint32_t), 0, /* alignment, boundary */ 1203188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1204188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1205188808Sgonzo NULL, NULL, /* filter, filterarg */ 1206188808Sgonzo MCLBYTES * ARGE_MAXFRAGS, /* maxsize */ 1207188808Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1208188808Sgonzo MCLBYTES, /* maxsegsize */ 1209188808Sgonzo 0, /* flags */ 1210188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1211188808Sgonzo &sc->arge_cdata.arge_tx_tag); 1212188808Sgonzo if (error != 0) { 1213188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx DMA tag\n"); 1214188808Sgonzo goto fail; 1215188808Sgonzo } 1216188808Sgonzo 1217188808Sgonzo /* Create tag for Rx buffers. */ 1218188808Sgonzo error = bus_dma_tag_create( 1219188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1220188808Sgonzo ARGE_RX_ALIGN, 0, /* alignment, boundary */ 1221188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1222188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1223188808Sgonzo NULL, NULL, /* filter, filterarg */ 1224188808Sgonzo MCLBYTES, /* maxsize */ 1225192821Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1226188808Sgonzo MCLBYTES, /* maxsegsize */ 1227188808Sgonzo 0, /* flags */ 1228188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1229188808Sgonzo &sc->arge_cdata.arge_rx_tag); 1230188808Sgonzo if (error != 0) { 1231188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx DMA tag\n"); 1232188808Sgonzo goto fail; 1233188808Sgonzo } 1234188808Sgonzo 1235188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1236188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag, 1237188808Sgonzo (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK | 1238188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_tx_ring_map); 1239188808Sgonzo if (error != 0) { 1240188808Sgonzo device_printf(sc->arge_dev, 1241188808Sgonzo "failed to allocate DMA'able memory for Tx ring\n"); 1242188808Sgonzo goto fail; 1243188808Sgonzo } 1244188808Sgonzo 1245188808Sgonzo ctx.arge_busaddr = 0; 1246188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag, 1247188808Sgonzo sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring, 1248188808Sgonzo ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1249188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1250188808Sgonzo device_printf(sc->arge_dev, 1251188808Sgonzo "failed to load DMA'able memory for Tx ring\n"); 1252188808Sgonzo goto fail; 1253188808Sgonzo } 1254188808Sgonzo sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr; 1255188808Sgonzo 1256188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1257188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag, 1258188808Sgonzo (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK | 1259188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_rx_ring_map); 1260188808Sgonzo if (error != 0) { 1261188808Sgonzo device_printf(sc->arge_dev, 1262188808Sgonzo "failed to allocate DMA'able memory for Rx ring\n"); 1263188808Sgonzo goto fail; 1264188808Sgonzo } 1265188808Sgonzo 1266188808Sgonzo ctx.arge_busaddr = 0; 1267188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag, 1268188808Sgonzo sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring, 1269188808Sgonzo ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1270188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1271188808Sgonzo device_printf(sc->arge_dev, 1272188808Sgonzo "failed to load DMA'able memory for Rx ring\n"); 1273188808Sgonzo goto fail; 1274188808Sgonzo } 1275188808Sgonzo sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr; 1276188808Sgonzo 1277188808Sgonzo /* Create DMA maps for Tx buffers. */ 1278188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1279188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1280188808Sgonzo txd->tx_m = NULL; 1281188808Sgonzo txd->tx_dmamap = NULL; 1282188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0, 1283188808Sgonzo &txd->tx_dmamap); 1284188808Sgonzo if (error != 0) { 1285188808Sgonzo device_printf(sc->arge_dev, 1286188808Sgonzo "failed to create Tx dmamap\n"); 1287188808Sgonzo goto fail; 1288188808Sgonzo } 1289188808Sgonzo } 1290188808Sgonzo /* Create DMA maps for Rx buffers. */ 1291188808Sgonzo if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1292188808Sgonzo &sc->arge_cdata.arge_rx_sparemap)) != 0) { 1293188808Sgonzo device_printf(sc->arge_dev, 1294188808Sgonzo "failed to create spare Rx dmamap\n"); 1295188808Sgonzo goto fail; 1296188808Sgonzo } 1297188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1298188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1299188808Sgonzo rxd->rx_m = NULL; 1300188808Sgonzo rxd->rx_dmamap = NULL; 1301188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1302188808Sgonzo &rxd->rx_dmamap); 1303188808Sgonzo if (error != 0) { 1304188808Sgonzo device_printf(sc->arge_dev, 1305188808Sgonzo "failed to create Rx dmamap\n"); 1306188808Sgonzo goto fail; 1307188808Sgonzo } 1308188808Sgonzo } 1309188808Sgonzo 1310188808Sgonzofail: 1311188808Sgonzo return (error); 1312188808Sgonzo} 1313188808Sgonzo 1314188808Sgonzostatic void 1315188808Sgonzoarge_dma_free(struct arge_softc *sc) 1316188808Sgonzo{ 1317188808Sgonzo struct arge_txdesc *txd; 1318188808Sgonzo struct arge_rxdesc *rxd; 1319188808Sgonzo int i; 1320188808Sgonzo 1321188808Sgonzo /* Tx ring. */ 1322188808Sgonzo if (sc->arge_cdata.arge_tx_ring_tag) { 1323188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map) 1324188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag, 1325188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1326188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map && 1327188808Sgonzo sc->arge_rdata.arge_tx_ring) 1328188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag, 1329188808Sgonzo sc->arge_rdata.arge_tx_ring, 1330188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1331188808Sgonzo sc->arge_rdata.arge_tx_ring = NULL; 1332188808Sgonzo sc->arge_cdata.arge_tx_ring_map = NULL; 1333188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag); 1334188808Sgonzo sc->arge_cdata.arge_tx_ring_tag = NULL; 1335188808Sgonzo } 1336188808Sgonzo /* Rx ring. */ 1337188808Sgonzo if (sc->arge_cdata.arge_rx_ring_tag) { 1338188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map) 1339188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag, 1340188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1341188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map && 1342188808Sgonzo sc->arge_rdata.arge_rx_ring) 1343188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag, 1344188808Sgonzo sc->arge_rdata.arge_rx_ring, 1345188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1346188808Sgonzo sc->arge_rdata.arge_rx_ring = NULL; 1347188808Sgonzo sc->arge_cdata.arge_rx_ring_map = NULL; 1348188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag); 1349188808Sgonzo sc->arge_cdata.arge_rx_ring_tag = NULL; 1350188808Sgonzo } 1351188808Sgonzo /* Tx buffers. */ 1352188808Sgonzo if (sc->arge_cdata.arge_tx_tag) { 1353188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1354188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1355188808Sgonzo if (txd->tx_dmamap) { 1356188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag, 1357188808Sgonzo txd->tx_dmamap); 1358188808Sgonzo txd->tx_dmamap = NULL; 1359188808Sgonzo } 1360188808Sgonzo } 1361188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag); 1362188808Sgonzo sc->arge_cdata.arge_tx_tag = NULL; 1363188808Sgonzo } 1364188808Sgonzo /* Rx buffers. */ 1365188808Sgonzo if (sc->arge_cdata.arge_rx_tag) { 1366188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1367188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1368188808Sgonzo if (rxd->rx_dmamap) { 1369188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1370188808Sgonzo rxd->rx_dmamap); 1371188808Sgonzo rxd->rx_dmamap = NULL; 1372188808Sgonzo } 1373188808Sgonzo } 1374188808Sgonzo if (sc->arge_cdata.arge_rx_sparemap) { 1375188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1376188808Sgonzo sc->arge_cdata.arge_rx_sparemap); 1377188808Sgonzo sc->arge_cdata.arge_rx_sparemap = 0; 1378188808Sgonzo } 1379188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag); 1380188808Sgonzo sc->arge_cdata.arge_rx_tag = NULL; 1381188808Sgonzo } 1382188808Sgonzo 1383188808Sgonzo if (sc->arge_cdata.arge_parent_tag) { 1384188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag); 1385188808Sgonzo sc->arge_cdata.arge_parent_tag = NULL; 1386188808Sgonzo } 1387188808Sgonzo} 1388188808Sgonzo 1389188808Sgonzo/* 1390188808Sgonzo * Initialize the transmit descriptors. 1391188808Sgonzo */ 1392188808Sgonzostatic int 1393188808Sgonzoarge_tx_ring_init(struct arge_softc *sc) 1394188808Sgonzo{ 1395188808Sgonzo struct arge_ring_data *rd; 1396188808Sgonzo struct arge_txdesc *txd; 1397188808Sgonzo bus_addr_t addr; 1398188808Sgonzo int i; 1399188808Sgonzo 1400188808Sgonzo sc->arge_cdata.arge_tx_prod = 0; 1401188808Sgonzo sc->arge_cdata.arge_tx_cons = 0; 1402188808Sgonzo sc->arge_cdata.arge_tx_cnt = 0; 1403188808Sgonzo sc->arge_cdata.arge_tx_pkts = 0; 1404188808Sgonzo 1405188808Sgonzo rd = &sc->arge_rdata; 1406188808Sgonzo bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring)); 1407188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1408188808Sgonzo if (i == ARGE_TX_RING_COUNT - 1) 1409188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, 0); 1410188808Sgonzo else 1411188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, i + 1); 1412188808Sgonzo rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY; 1413188808Sgonzo rd->arge_tx_ring[i].next_desc = addr; 1414188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1415188808Sgonzo txd->tx_m = NULL; 1416188808Sgonzo } 1417188808Sgonzo 1418188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1419188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1420188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1421188808Sgonzo 1422188808Sgonzo return (0); 1423188808Sgonzo} 1424188808Sgonzo 1425188808Sgonzo/* 1426188808Sgonzo * Initialize the RX descriptors and allocate mbufs for them. Note that 1427188808Sgonzo * we arrange the descriptors in a closed ring, so that the last descriptor 1428188808Sgonzo * points back to the first. 1429188808Sgonzo */ 1430188808Sgonzostatic int 1431188808Sgonzoarge_rx_ring_init(struct arge_softc *sc) 1432188808Sgonzo{ 1433188808Sgonzo struct arge_ring_data *rd; 1434188808Sgonzo struct arge_rxdesc *rxd; 1435188808Sgonzo bus_addr_t addr; 1436188808Sgonzo int i; 1437188808Sgonzo 1438188808Sgonzo sc->arge_cdata.arge_rx_cons = 0; 1439188808Sgonzo 1440188808Sgonzo rd = &sc->arge_rdata; 1441188808Sgonzo bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring)); 1442188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1443188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1444188808Sgonzo rxd->rx_m = NULL; 1445188808Sgonzo rxd->desc = &rd->arge_rx_ring[i]; 1446188808Sgonzo if (i == ARGE_RX_RING_COUNT - 1) 1447188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, 0); 1448188808Sgonzo else 1449188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, i + 1); 1450188808Sgonzo rd->arge_rx_ring[i].next_desc = addr; 1451192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1452188808Sgonzo return (ENOBUFS); 1453192783Sgonzo } 1454188808Sgonzo } 1455188808Sgonzo 1456188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1457188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1458195434Sgonzo BUS_DMASYNC_PREWRITE); 1459188808Sgonzo 1460188808Sgonzo return (0); 1461188808Sgonzo} 1462188808Sgonzo 1463188808Sgonzo/* 1464188808Sgonzo * Initialize an RX descriptor and attach an MBUF cluster. 1465188808Sgonzo */ 1466188808Sgonzostatic int 1467188808Sgonzoarge_newbuf(struct arge_softc *sc, int idx) 1468188808Sgonzo{ 1469188808Sgonzo struct arge_desc *desc; 1470188808Sgonzo struct arge_rxdesc *rxd; 1471188808Sgonzo struct mbuf *m; 1472188808Sgonzo bus_dma_segment_t segs[1]; 1473188808Sgonzo bus_dmamap_t map; 1474188808Sgonzo int nsegs; 1475188808Sgonzo 1476188808Sgonzo m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1477188808Sgonzo if (m == NULL) 1478188808Sgonzo return (ENOBUFS); 1479188808Sgonzo m->m_len = m->m_pkthdr.len = MCLBYTES; 1480188808Sgonzo m_adj(m, sizeof(uint64_t)); 1481188808Sgonzo 1482188808Sgonzo if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag, 1483188808Sgonzo sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1484188808Sgonzo m_freem(m); 1485188808Sgonzo return (ENOBUFS); 1486188808Sgonzo } 1487188808Sgonzo KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1488188808Sgonzo 1489188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[idx]; 1490188808Sgonzo if (rxd->rx_m != NULL) { 1491188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap); 1492188808Sgonzo } 1493188808Sgonzo map = rxd->rx_dmamap; 1494188808Sgonzo rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap; 1495188808Sgonzo sc->arge_cdata.arge_rx_sparemap = map; 1496188808Sgonzo rxd->rx_m = m; 1497188808Sgonzo desc = rxd->desc; 1498192783Sgonzo if (segs[0].ds_addr & 3) 1499192783Sgonzo panic("RX packet address unaligned"); 1500188808Sgonzo desc->packet_addr = segs[0].ds_addr; 1501192783Sgonzo desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len); 1502188808Sgonzo 1503195434Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1504195434Sgonzo sc->arge_cdata.arge_rx_ring_map, 1505195434Sgonzo BUS_DMASYNC_PREWRITE); 1506195434Sgonzo 1507188808Sgonzo return (0); 1508188808Sgonzo} 1509188808Sgonzo 1510188808Sgonzostatic __inline void 1511188808Sgonzoarge_fixup_rx(struct mbuf *m) 1512188808Sgonzo{ 1513198933Sgonzo int i; 1514198933Sgonzo uint16_t *src, *dst; 1515188808Sgonzo 1516188808Sgonzo src = mtod(m, uint16_t *); 1517188808Sgonzo dst = src - 1; 1518188808Sgonzo 1519195434Sgonzo for (i = 0; i < m->m_len / sizeof(uint16_t); i++) { 1520188808Sgonzo *dst++ = *src++; 1521195434Sgonzo } 1522188808Sgonzo 1523195434Sgonzo if (m->m_len % sizeof(uint16_t)) 1524195434Sgonzo *(uint8_t *)dst = *(uint8_t *)src; 1525195434Sgonzo 1526188808Sgonzo m->m_data -= ETHER_ALIGN; 1527188808Sgonzo} 1528188808Sgonzo 1529192783Sgonzo#ifdef DEVICE_POLLING 1530198667Sgonzostatic int 1531192783Sgonzoarge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1532192783Sgonzo{ 1533192783Sgonzo struct arge_softc *sc = ifp->if_softc; 1534198667Sgonzo int rx_npkts = 0; 1535188808Sgonzo 1536198933Sgonzo if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1537192783Sgonzo ARGE_LOCK(sc); 1538192783Sgonzo arge_tx_locked(sc); 1539198667Sgonzo rx_npkts = arge_rx_locked(sc); 1540192783Sgonzo ARGE_UNLOCK(sc); 1541198933Sgonzo } 1542198667Sgonzo 1543198667Sgonzo return (rx_npkts); 1544192783Sgonzo} 1545192783Sgonzo#endif /* DEVICE_POLLING */ 1546192783Sgonzo 1547192783Sgonzo 1548188808Sgonzostatic void 1549188808Sgonzoarge_tx_locked(struct arge_softc *sc) 1550188808Sgonzo{ 1551188808Sgonzo struct arge_txdesc *txd; 1552188808Sgonzo struct arge_desc *cur_tx; 1553188808Sgonzo struct ifnet *ifp; 1554188808Sgonzo uint32_t ctrl; 1555188808Sgonzo int cons, prod; 1556188808Sgonzo 1557188808Sgonzo ARGE_LOCK_ASSERT(sc); 1558188808Sgonzo 1559188808Sgonzo cons = sc->arge_cdata.arge_tx_cons; 1560188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 1561188808Sgonzo if (cons == prod) 1562188808Sgonzo return; 1563188808Sgonzo 1564188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1565188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1566188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1567188808Sgonzo 1568188808Sgonzo ifp = sc->arge_ifp; 1569188808Sgonzo /* 1570188808Sgonzo * Go through our tx list and free mbufs for those 1571188808Sgonzo * frames that have been transmitted. 1572188808Sgonzo */ 1573188808Sgonzo for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) { 1574188808Sgonzo cur_tx = &sc->arge_rdata.arge_tx_ring[cons]; 1575188808Sgonzo ctrl = cur_tx->packet_ctrl; 1576188808Sgonzo /* Check if descriptor has "finished" flag */ 1577188808Sgonzo if ((ctrl & ARGE_DESC_EMPTY) == 0) 1578188808Sgonzo break; 1579188808Sgonzo 1580188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 1581188808Sgonzo 1582188808Sgonzo sc->arge_cdata.arge_tx_cnt--; 1583188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1584188808Sgonzo 1585188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[cons]; 1586188808Sgonzo 1587188808Sgonzo ifp->if_opackets++; 1588188808Sgonzo 1589188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 1590188808Sgonzo BUS_DMASYNC_POSTWRITE); 1591188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 1592188808Sgonzo 1593188808Sgonzo /* Free only if it's first descriptor in list */ 1594188808Sgonzo if (txd->tx_m) 1595188808Sgonzo m_freem(txd->tx_m); 1596188808Sgonzo txd->tx_m = NULL; 1597188808Sgonzo 1598188808Sgonzo /* reset descriptor */ 1599188808Sgonzo cur_tx->packet_addr = 0; 1600188808Sgonzo } 1601188808Sgonzo 1602188808Sgonzo sc->arge_cdata.arge_tx_cons = cons; 1603188808Sgonzo 1604188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1605188808Sgonzo sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1606188808Sgonzo} 1607188808Sgonzo 1608188808Sgonzo 1609198667Sgonzostatic int 1610188808Sgonzoarge_rx_locked(struct arge_softc *sc) 1611188808Sgonzo{ 1612188808Sgonzo struct arge_rxdesc *rxd; 1613188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 1614192783Sgonzo int cons, prog, packet_len, i; 1615188808Sgonzo struct arge_desc *cur_rx; 1616188808Sgonzo struct mbuf *m; 1617198667Sgonzo int rx_npkts = 0; 1618188808Sgonzo 1619188808Sgonzo ARGE_LOCK_ASSERT(sc); 1620188808Sgonzo 1621188808Sgonzo cons = sc->arge_cdata.arge_rx_cons; 1622188808Sgonzo 1623188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1624188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1625188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1626188808Sgonzo 1627188808Sgonzo for (prog = 0; prog < ARGE_RX_RING_COUNT; 1628188808Sgonzo ARGE_INC(cons, ARGE_RX_RING_COUNT)) { 1629188808Sgonzo cur_rx = &sc->arge_rdata.arge_rx_ring[cons]; 1630188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[cons]; 1631188808Sgonzo m = rxd->rx_m; 1632188808Sgonzo 1633188808Sgonzo if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0) 1634188808Sgonzo break; 1635188808Sgonzo 1636188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 1637188808Sgonzo 1638188808Sgonzo prog++; 1639188808Sgonzo 1640188808Sgonzo packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl); 1641188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap, 1642195434Sgonzo BUS_DMASYNC_POSTREAD); 1643188808Sgonzo m = rxd->rx_m; 1644188808Sgonzo 1645188808Sgonzo arge_fixup_rx(m); 1646188808Sgonzo m->m_pkthdr.rcvif = ifp; 1647188808Sgonzo /* Skip 4 bytes of CRC */ 1648188808Sgonzo m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN; 1649188808Sgonzo ifp->if_ipackets++; 1650198667Sgonzo rx_npkts++; 1651188808Sgonzo 1652188808Sgonzo ARGE_UNLOCK(sc); 1653188808Sgonzo (*ifp->if_input)(ifp, m); 1654188808Sgonzo ARGE_LOCK(sc); 1655192783Sgonzo cur_rx->packet_addr = 0; 1656192783Sgonzo } 1657188808Sgonzo 1658192783Sgonzo if (prog > 0) { 1659192783Sgonzo 1660192783Sgonzo i = sc->arge_cdata.arge_rx_cons; 1661192783Sgonzo for (; prog > 0 ; prog--) { 1662192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1663192783Sgonzo device_printf(sc->arge_dev, 1664192783Sgonzo "Failed to allocate buffer\n"); 1665192783Sgonzo break; 1666192783Sgonzo } 1667192783Sgonzo ARGE_INC(i, ARGE_RX_RING_COUNT); 1668188808Sgonzo } 1669188808Sgonzo 1670188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1671188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1672195434Sgonzo BUS_DMASYNC_PREWRITE); 1673188808Sgonzo 1674188808Sgonzo sc->arge_cdata.arge_rx_cons = cons; 1675188808Sgonzo } 1676198667Sgonzo 1677198667Sgonzo return (rx_npkts); 1678188808Sgonzo} 1679188808Sgonzo 1680188808Sgonzostatic int 1681188808Sgonzoarge_intr_filter(void *arg) 1682188808Sgonzo{ 1683188808Sgonzo struct arge_softc *sc = arg; 1684188808Sgonzo uint32_t status, ints; 1685188808Sgonzo 1686188808Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1687188808Sgonzo ints = ARGE_READ(sc, AR71XX_DMA_INTR); 1688188808Sgonzo 1689188808Sgonzo#if 0 1690188808Sgonzo dprintf("int mask(filter) = %b\n", ints, 1691188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1692188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1693188808Sgonzo dprintf("status(filter) = %b\n", status, 1694188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1695188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1696188808Sgonzo#endif 1697188808Sgonzo 1698188808Sgonzo if (status & DMA_INTR_ALL) { 1699191644Sgonzo sc->arge_intr_status |= status; 1700192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1701188808Sgonzo return (FILTER_SCHEDULE_THREAD); 1702192783Sgonzo } 1703188808Sgonzo 1704188808Sgonzo sc->arge_intr_status = 0; 1705188808Sgonzo return (FILTER_STRAY); 1706188808Sgonzo} 1707188808Sgonzo 1708188808Sgonzostatic void 1709188808Sgonzoarge_intr(void *arg) 1710188808Sgonzo{ 1711188808Sgonzo struct arge_softc *sc = arg; 1712188808Sgonzo uint32_t status; 1713188808Sgonzo 1714192783Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1715192783Sgonzo status |= sc->arge_intr_status; 1716188808Sgonzo 1717188808Sgonzo#if 0 1718188808Sgonzo dprintf("int status(intr) = %b\n", status, 1719188808Sgonzo "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD" 1720188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1721188808Sgonzo#endif 1722188808Sgonzo 1723188808Sgonzo /* 1724188808Sgonzo * Is it our interrupt at all? 1725188808Sgonzo */ 1726188808Sgonzo if (status == 0) 1727188808Sgonzo return; 1728188808Sgonzo 1729188808Sgonzo if (status & DMA_INTR_RX_BUS_ERROR) { 1730188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR); 1731188808Sgonzo device_printf(sc->arge_dev, "RX bus error"); 1732188808Sgonzo return; 1733188808Sgonzo } 1734188808Sgonzo 1735188808Sgonzo if (status & DMA_INTR_TX_BUS_ERROR) { 1736188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR); 1737188808Sgonzo device_printf(sc->arge_dev, "TX bus error"); 1738188808Sgonzo return; 1739188808Sgonzo } 1740188808Sgonzo 1741192783Sgonzo ARGE_LOCK(sc); 1742188808Sgonzo 1743192783Sgonzo if (status & DMA_INTR_RX_PKT_RCVD) 1744192783Sgonzo arge_rx_locked(sc); 1745188808Sgonzo 1746192783Sgonzo /* 1747192783Sgonzo * RX overrun disables the receiver. 1748192783Sgonzo * Clear indication and re-enable rx. 1749192783Sgonzo */ 1750192783Sgonzo if ( status & DMA_INTR_RX_OVERFLOW) { 1751192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW); 1752192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 1753192783Sgonzo } 1754188808Sgonzo 1755192783Sgonzo if (status & DMA_INTR_TX_PKT_SENT) 1756192783Sgonzo arge_tx_locked(sc); 1757192783Sgonzo /* 1758192783Sgonzo * Underrun turns off TX. Clear underrun indication. 1759192783Sgonzo * If there's anything left in the ring, reactivate the tx. 1760192783Sgonzo */ 1761192569Sdwhite if (status & DMA_INTR_TX_UNDERRUN) { 1762192569Sdwhite ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN); 1763192783Sgonzo if (sc->arge_cdata.arge_tx_pkts > 0 ) { 1764192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 1765192783Sgonzo DMA_TX_CONTROL_EN); 1766192783Sgonzo } 1767192569Sdwhite } 1768192569Sdwhite 1769192946Sgonzo /* 1770192946Sgonzo * We handled all bits, clear status 1771192946Sgonzo */ 1772192946Sgonzo sc->arge_intr_status = 0; 1773188808Sgonzo ARGE_UNLOCK(sc); 1774192783Sgonzo /* 1775192783Sgonzo * re-enable all interrupts 1776192783Sgonzo */ 1777192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1778188808Sgonzo} 1779188808Sgonzo 1780192783Sgonzo 1781188808Sgonzostatic void 1782188808Sgonzoarge_tick(void *xsc) 1783188808Sgonzo{ 1784188808Sgonzo struct arge_softc *sc = xsc; 1785188808Sgonzo struct mii_data *mii; 1786188808Sgonzo 1787188808Sgonzo ARGE_LOCK_ASSERT(sc); 1788188808Sgonzo 1789199234Sgonzo if (sc->arge_miibus) { 1790199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1791199234Sgonzo mii_tick(mii); 1792199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 1793199234Sgonzo } 1794188808Sgonzo} 1795199234Sgonzo 1796199234Sgonzoint 1797199234Sgonzoarge_multiphy_mediachange(struct ifnet *ifp) 1798199234Sgonzo{ 1799199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1800199234Sgonzo struct ifmedia *ifm = &sc->arge_ifmedia; 1801199234Sgonzo struct ifmedia_entry *ife = ifm->ifm_cur; 1802199234Sgonzo 1803199234Sgonzo if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1804199234Sgonzo return (EINVAL); 1805199234Sgonzo 1806199234Sgonzo if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1807199234Sgonzo device_printf(sc->arge_dev, 1808199234Sgonzo "AUTO is not supported for multiphy MAC"); 1809199234Sgonzo return (EINVAL); 1810199234Sgonzo } 1811199234Sgonzo 1812199234Sgonzo /* 1813199234Sgonzo * Ignore everything 1814199234Sgonzo */ 1815199234Sgonzo return (0); 1816199234Sgonzo} 1817199234Sgonzo 1818199234Sgonzovoid 1819199234Sgonzoarge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1820199234Sgonzo{ 1821199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1822199234Sgonzo 1823199234Sgonzo ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1824199234Sgonzo ifmr->ifm_active = IFM_ETHER | sc->arge_media_type | 1825199234Sgonzo sc->arge_duplex_mode; 1826199234Sgonzo} 1827199234Sgonzo 1828