ar934xreg.h revision 253028 
1/*-
2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/atheros/ar934xreg.h 253028 2013-07-08 06:12:38Z adrian $
27 */
28
29#ifndef	__AR934X_REG_H__
30#define	__AR934X_REG_H__
31
32#define	AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
33#define	AR934X_WMAC_SIZE	0x20000
34#define	AR934X_EHCI_BASE	0x1b000000
35#define	AR934X_EHCI_SIZE	0x200
36#define	AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
37#define	AR934X_SRIF_SIZE	0x1000
38
39#define	AR934X_DDR_REG_FLUSH_GE0	(AR71XX_APB_BASE + 0x9c)
40#define	AR934X_DDR_REG_FLUSH_GE1	(AR71XX_APB_BASE + 0xa0)
41#define	AR934X_DDR_REG_FLUSH_USB	(AR71XX_APB_BASE + 0xa4)
42#define	AR934X_DDR_REG_FLUSH_PCIE	(AR71XX_APB_BASE + 0xa8)
43#define	AR934X_DDR_REG_FLUSH_WMAC	(AR71XX_APB_BASE + 0xac)
44
45#define	AR934X_PLL_CPU_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x00)
46#define	AR934X_PLL_DDR_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x04)
47#define	AR934X_PLL_CPU_DDR_CLK_CTRL_REG	(AR71XX_PLL_CPU_BASE + 0x08)
48
49#define	AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
50#define	AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
51#define	AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
52#define	AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
53#define	AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
54#define	AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
55#define	AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
56#define	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
57
58#define	AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
59#define	AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
60#define	AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
61#define	AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
62#define	AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
63#define	AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
64#define	AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
65#define	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
66
67#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	(1 << 2)
68#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	(1 << 3)
69#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	(1 << 4)
70#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
71#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
72#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
73#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
74#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
75#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
76#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	(1 << 20)
77#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	(1 << 21)
78#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	(1 << 24)
79
80#define	AR934X_RESET_REG_RESET_MODULE		(AR71XX_RST_BLOCK_BASE + 0x1c)
81#define	AR934X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xb0)
82#define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	(AR71XX_RST_BLOCK_BASE + 0xac)
83
84#define	AR934X_RESET_USB_PHY_ANALOG	(1 << 11)
85#define	AR934X_RESET_USB_HOST		(1 << 5)
86#define	AR934X_RESET_USB_PHY		(1 << 4)
87#define	AR934X_RESET_USBSUS_OVERRIDE	(1 << 3)
88
89#define	AR934X_BOOTSTRAP_SW_OPTION8	(1 << 23)
90#define	AR934X_BOOTSTRAP_SW_OPTION7	(1 << 22)
91#define	AR934X_BOOTSTRAP_SW_OPTION6	(1 << 21)
92#define	AR934X_BOOTSTRAP_SW_OPTION5	(1 << 20)
93#define	AR934X_BOOTSTRAP_SW_OPTION4	(1 << 19)
94#define	AR934X_BOOTSTRAP_SW_OPTION3	(1 << 18)
95#define	AR934X_BOOTSTRAP_SW_OPTION2	(1 << 17)
96#define	AR934X_BOOTSTRAP_SW_OPTION1	(1 << 16)
97#define	AR934X_BOOTSTRAP_USB_MODE_DEVICE	(1 << 7)
98#define	AR934X_BOOTSTRAP_PCIE_RC	(1 << 6)
99#define	AR934X_BOOTSTRAP_EJTAG_MODE	(1 << 5)
100#define	AR934X_BOOTSTRAP_REF_CLK_40	(1 << 4)
101#define	AR934X_BOOTSTRAP_BOOT_FROM_SPI	(1 << 2)
102#define	AR934X_BOOTSTRAP_SDRAM_DISABLED	(1 << 1)
103#define	AR934X_BOOTSTRAP_DDR1		(1 << 0)
104
105#define	AR934X_PCIE_WMAC_INT_WMAC_MISC	(1 << 0)
106#define	AR934X_PCIE_WMAC_INT_WMAC_TX	(1 << 1)
107#define	AR934X_PCIE_WMAC_INT_WMAC_RXLP	(1 << 2)
108#define	AR934X_PCIE_WMAC_INT_WMAC_RXHP	(1 << 3)
109#define	AR934X_PCIE_WMAC_INT_PCIE_RC	(1 << 4)
110#define	AR934X_PCIE_WMAC_INT_PCIE_RC0	(1 << 5)
111#define	AR934X_PCIE_WMAC_INT_PCIE_RC1	(1 << 6)
112#define	AR934X_PCIE_WMAC_INT_PCIE_RC2	(1 << 7)
113#define	AR934X_PCIE_WMAC_INT_PCIE_RC3	(1 << 8)
114#define	AR934X_PCIE_WMAC_INT_WMAC_ALL \
115        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
116         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
117
118#define	AR934X_PCIE_WMAC_INT_PCIE_ALL \
119        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
120         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
121         AR934X_PCIE_WMAC_INT_PCIE_RC3)
122
123#define	REV_ID_MAJOR_AR9341		0x0120
124#define	REV_ID_MAJOR_AR9342		0x1120
125#define	REV_ID_MAJOR_AR9344		0x2120
126
127#define	AR934X_REV_ID_REVISION_MASK     0xf
128
129/*
130 * GPIO block
131 */
132#define	AR934X_GPIO_REG_FUNC		0x6c
133#define	AR934X_GPIO_COUNT		23
134
135/*
136 * SRIF block
137 */
138#define	AR934X_SRIF_CPU_DPLL1_REG	(AR934X_SRIF_BASE + 0x1c0)
139#define	AR934X_SRIF_CPU_DPLL2_REG	(AR934X_SRIF_BASE + 0x1c4)
140#define	AR934X_SRIF_CPU_DPLL3_REG	(AR934X_SRIF_BASE + 0x1c8)
141
142#define	AR934X_SRIF_DDR_DPLL1_REG	(AR934X_SRIF_BASE + 0x240)
143#define	AR934X_SRIF_DDR_DPLL2_REG	(AR934X_SRIF_BASE + 0x244)
144#define	AR934X_SRIF_DDR_DPLL3_REG	(AR934X_SRIF_BASE + 0x248)
145
146#define	AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
147#define	AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
148#define	AR934X_SRIF_DPLL1_NINT_SHIFT	18
149#define	AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
150#define	AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
151
152#define	AR934X_SRIF_DPLL2_LOCAL_PLL	(1 << 30)
153#define	AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
154#define	AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
155
156#endif	/* __AR934X_REG_H__ */
157