1/*-
2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef	__AR934X_REG_H__
30#define	__AR934X_REG_H__
31
32#define	AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
33#define	AR934X_GMAC_SIZE	0x14
34#define	AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
35#define	AR934X_WMAC_SIZE	0x20000
36#define	AR934X_EHCI_BASE	0x1b000000
37#define	AR934X_EHCI_SIZE	0x200
38#define	AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
39#define	AR934X_SRIF_SIZE	0x1000
40
41/* AR934x GMAC configuration */
42#define	AR934X_GMAC_REG_ETH_CFG		(AR934X_GMAC_BASE + 0x00)
43
44#define	AR934X_ETH_CFG_RGMII_GMAC0		(1 << 0)
45#define	AR934X_ETH_CFG_MII_GMAC0		(1 << 1)
46#define	AR934X_ETH_CFG_GMII_GMAC0		(1 << 2)
47#define	AR934X_ETH_CFG_MII_GMAC0_MASTER		(1 << 3)
48#define	AR934X_ETH_CFG_MII_GMAC0_SLAVE		(1 << 4)
49#define	AR934X_ETH_CFG_MII_GMAC0_ERR_EN		(1 << 5)
50#define	AR934X_ETH_CFG_SW_ONLY_MODE		(1 << 6)
51#define	AR934X_ETH_CFG_SW_PHY_SWAP		(1 << 7)
52#define	AR934X_ETH_CFG_SW_APB_ACCESS		(1 << 9)
53#define	AR934X_ETH_CFG_RMII_GMAC0		(1 << 10)
54#define	AR933X_ETH_CFG_MII_CNTL_SPEED		(1 << 11)
55#define	AR934X_ETH_CFG_RMII_GMAC0_MASTER	(1 << 12)
56#define	AR934X_ETH_CFG_SW_ACC_MSB_FIRST		(1 << 13)
57
58#define	AR934X_DDR_REG_FLUSH_GE0	(AR71XX_APB_BASE + 0x9c)
59#define	AR934X_DDR_REG_FLUSH_GE1	(AR71XX_APB_BASE + 0xa0)
60#define	AR934X_DDR_REG_FLUSH_USB	(AR71XX_APB_BASE + 0xa4)
61#define	AR934X_DDR_REG_FLUSH_PCIE	(AR71XX_APB_BASE + 0xa8)
62#define	AR934X_DDR_REG_FLUSH_WMAC	(AR71XX_APB_BASE + 0xac)
63
64#define	AR934X_PLL_CPU_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x00)
65#define	AR934X_PLL_DDR_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x04)
66#define	AR934X_PLL_CPU_DDR_CLK_CTRL_REG	(AR71XX_PLL_CPU_BASE + 0x08)
67#define	AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	(AR71XX_PLL_CPU_BASE + 0x24)
68#define		AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   (1 << 6)
69#define	AR934X_PLL_ETH_XMII_CONTROL_REG	(AR71XX_PLL_CPU_BASE + 0x2c)
70
71#define	AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
72#define	AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
73#define	AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
74#define	AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
75#define	AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
76#define	AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
77#define	AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
78#define	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
79
80#define	AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
81#define	AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
82#define	AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
83#define	AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
84#define	AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
85#define	AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
86#define	AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
87#define	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
88
89#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	(1 << 2)
90#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	(1 << 3)
91#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	(1 << 4)
92#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
93#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
94#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
95#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
96#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
97#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
98#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	(1 << 20)
99#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	(1 << 21)
100#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	(1 << 24)
101
102#define	AR934X_RESET_REG_RESET_MODULE		(AR71XX_RST_BLOCK_BASE + 0x1c)
103#define	AR934X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xb0)
104#define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	(AR71XX_RST_BLOCK_BASE + 0xac)
105
106#define	AR934X_RESET_HOST		(1U << 31)
107#define	AR934X_RESET_SLIC		(1 << 30)
108#define	AR934X_RESET_HDMA		(1 << 29)
109#define	AR934X_RESET_EXTERNAL		(1 << 28)
110#define	AR934X_RESET_RTC		(1 << 27)
111#define	AR934X_RESET_PCIE_EP_INT	(1 << 26)
112#define	AR934X_RESET_CHKSUM_ACC		(1 << 25)
113#define	AR934X_RESET_FULL_CHIP		(1 << 24)
114#define	AR934X_RESET_GE1_MDIO		(1 << 23)
115#define	AR934X_RESET_GE0_MDIO		(1 << 22)
116#define	AR934X_RESET_CPU_NMI		(1 << 21)
117#define	AR934X_RESET_CPU_COLD		(1 << 20)
118#define	AR934X_RESET_HOST_RESET_INT	(1 << 19)
119#define	AR934X_RESET_PCIE_EP		(1 << 18)
120#define	AR934X_RESET_UART1		(1 << 17)
121#define	AR934X_RESET_DDR		(1 << 16)
122#define	AR934X_RESET_USB_PHY_PLL_PWD_EXT	(1 << 15)
123#define	AR934X_RESET_NANDF		(1 << 14)
124#define	AR934X_RESET_GE1_MAC		(1 << 13)
125#define	AR934X_RESET_ETH_SWITCH_ANALOG	(1 << 12)
126#define	AR934X_RESET_USB_PHY_ANALOG	(1 << 11)
127#define	AR934X_RESET_HOST_DMA_INT	(1 << 10)
128#define	AR934X_RESET_GE0_MAC		(1 << 9)
129#define	AR934X_RESET_ETH_SWITCH		(1 << 8)
130#define	AR934X_RESET_PCIE_PHY		(1 << 7)
131#define	AR934X_RESET_PCIE		(1 << 6)
132#define	AR934X_RESET_USB_HOST		(1 << 5)
133#define	AR934X_RESET_USB_PHY		(1 << 4)
134#define	AR934X_RESET_USBSUS_OVERRIDE	(1 << 3)
135#define	AR934X_RESET_LUT		(1 << 2)
136#define	AR934X_RESET_MBOX		(1 << 1)
137#define	AR934X_RESET_I2S		(1 << 0)
138
139#define	AR934X_BOOTSTRAP_SW_OPTION8	(1 << 23)
140#define	AR934X_BOOTSTRAP_SW_OPTION7	(1 << 22)
141#define	AR934X_BOOTSTRAP_SW_OPTION6	(1 << 21)
142#define	AR934X_BOOTSTRAP_SW_OPTION5	(1 << 20)
143#define	AR934X_BOOTSTRAP_SW_OPTION4	(1 << 19)
144#define	AR934X_BOOTSTRAP_SW_OPTION3	(1 << 18)
145#define	AR934X_BOOTSTRAP_SW_OPTION2	(1 << 17)
146#define	AR934X_BOOTSTRAP_SW_OPTION1	(1 << 16)
147#define	AR934X_BOOTSTRAP_USB_MODE_DEVICE	(1 << 7)
148#define	AR934X_BOOTSTRAP_PCIE_RC	(1 << 6)
149#define	AR934X_BOOTSTRAP_EJTAG_MODE	(1 << 5)
150#define	AR934X_BOOTSTRAP_REF_CLK_40	(1 << 4)
151#define	AR934X_BOOTSTRAP_BOOT_FROM_SPI	(1 << 2)
152#define	AR934X_BOOTSTRAP_SDRAM_DISABLED	(1 << 1)
153#define	AR934X_BOOTSTRAP_DDR1		(1 << 0)
154
155#define	AR934X_PCIE_WMAC_INT_WMAC_MISC	(1 << 0)
156#define	AR934X_PCIE_WMAC_INT_WMAC_TX	(1 << 1)
157#define	AR934X_PCIE_WMAC_INT_WMAC_RXLP	(1 << 2)
158#define	AR934X_PCIE_WMAC_INT_WMAC_RXHP	(1 << 3)
159#define	AR934X_PCIE_WMAC_INT_PCIE_RC	(1 << 4)
160#define	AR934X_PCIE_WMAC_INT_PCIE_RC0	(1 << 5)
161#define	AR934X_PCIE_WMAC_INT_PCIE_RC1	(1 << 6)
162#define	AR934X_PCIE_WMAC_INT_PCIE_RC2	(1 << 7)
163#define	AR934X_PCIE_WMAC_INT_PCIE_RC3	(1 << 8)
164#define	AR934X_PCIE_WMAC_INT_WMAC_ALL \
165        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
166         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
167
168#define	AR934X_PCIE_WMAC_INT_PCIE_ALL \
169        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
170         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
171         AR934X_PCIE_WMAC_INT_PCIE_RC3)
172
173#define	REV_ID_MAJOR_AR9341		0x0120
174#define	REV_ID_MAJOR_AR9342		0x1120
175#define	REV_ID_MAJOR_AR9344		0x2120
176
177#define	AR934X_REV_ID_REVISION_MASK     0xf
178
179/*
180 * GPIO block
181 */
182#define	AR934X_GPIO_REG_OUT_FUNC0	0x2c
183#define	AR934X_GPIO_REG_OUT_FUNC1	0x30
184#define	AR934X_GPIO_REG_OUT_FUNC2	0x34
185#define	AR934X_GPIO_REG_OUT_FUNC3	0x38
186#define	AR934X_GPIO_REG_OUT_FUNC4	0x3c
187#define	AR934X_GPIO_REG_OUT_FUNC5	0x40
188#define	AR934X_GPIO_REG_FUNC		0x6c
189#define	AR934X_GPIO_COUNT		23
190
191/* GPIO functions */
192#define	AR934X_GPIO_FUNC_CLK_OBS7_EN           (1 << 9)
193#define	AR934X_GPIO_FUNC_CLK_OBS6_EN           (1 << 8)
194#define	AR934X_GPIO_FUNC_CLK_OBS5_EN           (1 << 7)
195#define	AR934X_GPIO_FUNC_CLK_OBS4_EN           (1 << 6)
196#define	AR934X_GPIO_FUNC_CLK_OBS3_EN           (1 << 5)
197#define	AR934X_GPIO_FUNC_CLK_OBS2_EN           (1 << 4)
198#define	AR934X_GPIO_FUNC_CLK_OBS1_EN           (1 << 3)
199#define	AR934X_GPIO_FUNC_CLK_OBS0_EN           (1 << 2)
200#define	AR934X_GPIO_FUNC_JTAG_DISABLE          (1 << 1)
201
202/* GPIO MUX output function: AR934X_GPIO_REG_OUT_FUNCx */
203#define	AR934X_GPIO_OUT_GPIO		0	/* I'm a GPIO */
204#define	AR934X_GPIO_OUT_SPI_CS1		7	/* I'm SPI CS1 */
205#define	AR934X_GPIO_OUT_LED_LINK0	41	/* I'm switch phy link0 */
206#define	AR934X_GPIO_OUT_LED_LINK1	42
207#define	AR934X_GPIO_OUT_LED_LINK2	43
208#define	AR934X_GPIO_OUT_LED_LINK3	44
209#define	AR934X_GPIO_OUT_LED_LINK4	45
210#define	AR934X_GPIO_OUT_EXT_LNA0	46	/* I'm WMAC EXT LNA chain 0 */
211#define	AR934X_GPIO_OUT_EXT_LNA1	47	/* I'm WMAC EXT LNA chain 1 */
212
213/*
214 * SRIF block
215 */
216#define	AR934X_SRIF_CPU_DPLL1_REG	(AR934X_SRIF_BASE + 0x1c0)
217#define	AR934X_SRIF_CPU_DPLL2_REG	(AR934X_SRIF_BASE + 0x1c4)
218#define	AR934X_SRIF_CPU_DPLL3_REG	(AR934X_SRIF_BASE + 0x1c8)
219
220#define	AR934X_SRIF_DDR_DPLL1_REG	(AR934X_SRIF_BASE + 0x240)
221#define	AR934X_SRIF_DDR_DPLL2_REG	(AR934X_SRIF_BASE + 0x244)
222#define	AR934X_SRIF_DDR_DPLL3_REG	(AR934X_SRIF_BASE + 0x248)
223
224#define	AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
225#define	AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
226#define	AR934X_SRIF_DPLL1_NINT_SHIFT	18
227#define	AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
228#define	AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
229
230#define	AR934X_SRIF_DPLL2_LOCAL_PLL	(1 << 30)
231#define	AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
232#define	AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
233
234/* XXX verify! */
235#define	AR934X_PLL_VAL_1000		0x16000000
236#define	AR934X_PLL_VAL_100		0x00000101
237#define	AR934X_PLL_VAL_10		0x00001616
238
239#endif	/* __AR934X_REG_H__ */
240