1253028Sadrian/*-
2253028Sadrian * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
3253028Sadrian * All rights reserved.
4253028Sadrian *
5253028Sadrian * Redistribution and use in source and binary forms, with or without
6253028Sadrian * modification, are permitted provided that the following conditions
7253028Sadrian * are met:
8253028Sadrian * 1. Redistributions of source code must retain the above copyright
9253028Sadrian *    notice, this list of conditions and the following disclaimer.
10253028Sadrian * 2. Redistributions in binary form must reproduce the above copyright
11253028Sadrian *    notice, this list of conditions and the following disclaimer in the
12253028Sadrian *    documentation and/or other materials provided with the distribution.
13253028Sadrian *
14253028Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15253028Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16253028Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17253028Sadrian * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18253028Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19253028Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20253028Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21253028Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22253028Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23253028Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24253028Sadrian * SUCH DAMAGE.
25253028Sadrian *
26253028Sadrian * $FreeBSD$
27253028Sadrian */
28253028Sadrian
29253028Sadrian#ifndef	__AR934X_REG_H__
30253028Sadrian#define	__AR934X_REG_H__
31253028Sadrian
32256175Sadrian#define	AR934X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
33256175Sadrian#define	AR934X_GMAC_SIZE	0x14
34253028Sadrian#define	AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
35253028Sadrian#define	AR934X_WMAC_SIZE	0x20000
36253028Sadrian#define	AR934X_EHCI_BASE	0x1b000000
37253028Sadrian#define	AR934X_EHCI_SIZE	0x200
38253028Sadrian#define	AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
39253028Sadrian#define	AR934X_SRIF_SIZE	0x1000
40253028Sadrian
41256175Sadrian/* AR934x GMAC configuration */
42256175Sadrian#define	AR934X_GMAC_REG_ETH_CFG		(AR934X_GMAC_BASE + 0x00)
43256175Sadrian
44256175Sadrian#define	AR934X_ETH_CFG_RGMII_GMAC0		(1 << 0)
45256175Sadrian#define	AR934X_ETH_CFG_MII_GMAC0		(1 << 1)
46256175Sadrian#define	AR934X_ETH_CFG_GMII_GMAC0		(1 << 2)
47256175Sadrian#define	AR934X_ETH_CFG_MII_GMAC0_MASTER		(1 << 3)
48256175Sadrian#define	AR934X_ETH_CFG_MII_GMAC0_SLAVE		(1 << 4)
49256175Sadrian#define	AR934X_ETH_CFG_MII_GMAC0_ERR_EN		(1 << 5)
50256175Sadrian#define	AR934X_ETH_CFG_SW_ONLY_MODE		(1 << 6)
51256175Sadrian#define	AR934X_ETH_CFG_SW_PHY_SWAP		(1 << 7)
52256175Sadrian#define	AR934X_ETH_CFG_SW_APB_ACCESS		(1 << 9)
53256175Sadrian#define	AR934X_ETH_CFG_RMII_GMAC0		(1 << 10)
54256175Sadrian#define	AR933X_ETH_CFG_MII_CNTL_SPEED		(1 << 11)
55256175Sadrian#define	AR934X_ETH_CFG_RMII_GMAC0_MASTER	(1 << 12)
56256175Sadrian#define	AR934X_ETH_CFG_SW_ACC_MSB_FIRST		(1 << 13)
57256175Sadrian
58253028Sadrian#define	AR934X_DDR_REG_FLUSH_GE0	(AR71XX_APB_BASE + 0x9c)
59253028Sadrian#define	AR934X_DDR_REG_FLUSH_GE1	(AR71XX_APB_BASE + 0xa0)
60253028Sadrian#define	AR934X_DDR_REG_FLUSH_USB	(AR71XX_APB_BASE + 0xa4)
61253028Sadrian#define	AR934X_DDR_REG_FLUSH_PCIE	(AR71XX_APB_BASE + 0xa8)
62253028Sadrian#define	AR934X_DDR_REG_FLUSH_WMAC	(AR71XX_APB_BASE + 0xac)
63253028Sadrian
64253028Sadrian#define	AR934X_PLL_CPU_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x00)
65253028Sadrian#define	AR934X_PLL_DDR_CONFIG_REG	(AR71XX_PLL_CPU_BASE + 0x04)
66253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_REG	(AR71XX_PLL_CPU_BASE + 0x08)
67256175Sadrian#define	AR934X_PLL_SWITCH_CLOCK_CONTROL_REG	(AR71XX_PLL_CPU_BASE + 0x24)
68256175Sadrian#define		AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   (1 << 6)
69256175Sadrian#define	AR934X_PLL_ETH_XMII_CONTROL_REG	(AR71XX_PLL_CPU_BASE + 0x2c)
70253028Sadrian
71253028Sadrian#define	AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
72253028Sadrian#define	AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
73253028Sadrian#define	AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
74253028Sadrian#define	AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
75253028Sadrian#define	AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
76253028Sadrian#define	AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
77253028Sadrian#define	AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
78253028Sadrian#define	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
79253028Sadrian
80253028Sadrian#define	AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
81253028Sadrian#define	AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
82253028Sadrian#define	AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
83253028Sadrian#define	AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
84253028Sadrian#define	AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
85253028Sadrian#define	AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
86253028Sadrian#define	AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
87253028Sadrian#define	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
88253028Sadrian
89253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	(1 << 2)
90253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	(1 << 3)
91253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	(1 << 4)
92253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
93253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
94253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
95253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
96253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
97253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
98253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	(1 << 20)
99253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	(1 << 21)
100253028Sadrian#define	AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	(1 << 24)
101253028Sadrian
102253028Sadrian#define	AR934X_RESET_REG_RESET_MODULE		(AR71XX_RST_BLOCK_BASE + 0x1c)
103253028Sadrian#define	AR934X_RESET_REG_BOOTSTRAP		(AR71XX_RST_BLOCK_BASE + 0xb0)
104253028Sadrian#define	AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	(AR71XX_RST_BLOCK_BASE + 0xac)
105253028Sadrian
106258780Seadler#define	AR934X_RESET_HOST		(1U << 31)
107256483Sadrian#define	AR934X_RESET_SLIC		(1 << 30)
108256483Sadrian#define	AR934X_RESET_HDMA		(1 << 29)
109256483Sadrian#define	AR934X_RESET_EXTERNAL		(1 << 28)
110256483Sadrian#define	AR934X_RESET_RTC		(1 << 27)
111256483Sadrian#define	AR934X_RESET_PCIE_EP_INT	(1 << 26)
112256483Sadrian#define	AR934X_RESET_CHKSUM_ACC		(1 << 25)
113256483Sadrian#define	AR934X_RESET_FULL_CHIP		(1 << 24)
114256175Sadrian#define	AR934X_RESET_GE1_MDIO		(1 << 23)
115256175Sadrian#define	AR934X_RESET_GE0_MDIO		(1 << 22)
116256483Sadrian#define	AR934X_RESET_CPU_NMI		(1 << 21)
117256483Sadrian#define	AR934X_RESET_CPU_COLD		(1 << 20)
118256483Sadrian#define	AR934X_RESET_HOST_RESET_INT	(1 << 19)
119256483Sadrian#define	AR934X_RESET_PCIE_EP		(1 << 18)
120256483Sadrian#define	AR934X_RESET_UART1		(1 << 17)
121256483Sadrian#define	AR934X_RESET_DDR		(1 << 16)
122256483Sadrian#define	AR934X_RESET_USB_PHY_PLL_PWD_EXT	(1 << 15)
123256483Sadrian#define	AR934X_RESET_NANDF		(1 << 14)
124256175Sadrian#define	AR934X_RESET_GE1_MAC		(1 << 13)
125256175Sadrian#define	AR934X_RESET_ETH_SWITCH_ANALOG	(1 << 12)
126253028Sadrian#define	AR934X_RESET_USB_PHY_ANALOG	(1 << 11)
127256483Sadrian#define	AR934X_RESET_HOST_DMA_INT	(1 << 10)
128256175Sadrian#define	AR934X_RESET_GE0_MAC		(1 << 9)
129256175Sadrian#define	AR934X_RESET_ETH_SWITCH		(1 << 8)
130256483Sadrian#define	AR934X_RESET_PCIE_PHY		(1 << 7)
131256483Sadrian#define	AR934X_RESET_PCIE		(1 << 6)
132253028Sadrian#define	AR934X_RESET_USB_HOST		(1 << 5)
133253028Sadrian#define	AR934X_RESET_USB_PHY		(1 << 4)
134253028Sadrian#define	AR934X_RESET_USBSUS_OVERRIDE	(1 << 3)
135256483Sadrian#define	AR934X_RESET_LUT		(1 << 2)
136256483Sadrian#define	AR934X_RESET_MBOX		(1 << 1)
137256483Sadrian#define	AR934X_RESET_I2S		(1 << 0)
138253028Sadrian
139253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION8	(1 << 23)
140253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION7	(1 << 22)
141253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION6	(1 << 21)
142253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION5	(1 << 20)
143253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION4	(1 << 19)
144253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION3	(1 << 18)
145253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION2	(1 << 17)
146253028Sadrian#define	AR934X_BOOTSTRAP_SW_OPTION1	(1 << 16)
147253028Sadrian#define	AR934X_BOOTSTRAP_USB_MODE_DEVICE	(1 << 7)
148253028Sadrian#define	AR934X_BOOTSTRAP_PCIE_RC	(1 << 6)
149253028Sadrian#define	AR934X_BOOTSTRAP_EJTAG_MODE	(1 << 5)
150253028Sadrian#define	AR934X_BOOTSTRAP_REF_CLK_40	(1 << 4)
151253028Sadrian#define	AR934X_BOOTSTRAP_BOOT_FROM_SPI	(1 << 2)
152253028Sadrian#define	AR934X_BOOTSTRAP_SDRAM_DISABLED	(1 << 1)
153253028Sadrian#define	AR934X_BOOTSTRAP_DDR1		(1 << 0)
154253028Sadrian
155253028Sadrian#define	AR934X_PCIE_WMAC_INT_WMAC_MISC	(1 << 0)
156253028Sadrian#define	AR934X_PCIE_WMAC_INT_WMAC_TX	(1 << 1)
157253028Sadrian#define	AR934X_PCIE_WMAC_INT_WMAC_RXLP	(1 << 2)
158253028Sadrian#define	AR934X_PCIE_WMAC_INT_WMAC_RXHP	(1 << 3)
159253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_RC	(1 << 4)
160253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_RC0	(1 << 5)
161253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_RC1	(1 << 6)
162253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_RC2	(1 << 7)
163253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_RC3	(1 << 8)
164253028Sadrian#define	AR934X_PCIE_WMAC_INT_WMAC_ALL \
165253028Sadrian        (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
166253028Sadrian         AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
167253028Sadrian
168253028Sadrian#define	AR934X_PCIE_WMAC_INT_PCIE_ALL \
169253028Sadrian        (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
170253028Sadrian         AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
171253028Sadrian         AR934X_PCIE_WMAC_INT_PCIE_RC3)
172253028Sadrian
173253028Sadrian#define	REV_ID_MAJOR_AR9341		0x0120
174253028Sadrian#define	REV_ID_MAJOR_AR9342		0x1120
175253028Sadrian#define	REV_ID_MAJOR_AR9344		0x2120
176253028Sadrian
177253028Sadrian#define	AR934X_REV_ID_REVISION_MASK     0xf
178253028Sadrian
179253028Sadrian/*
180253028Sadrian * GPIO block
181253028Sadrian */
182276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC0	0x2c
183276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC1	0x30
184276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC2	0x34
185276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC3	0x38
186276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC4	0x3c
187276608Sadrian#define	AR934X_GPIO_REG_OUT_FUNC5	0x40
188253028Sadrian#define	AR934X_GPIO_REG_FUNC		0x6c
189253028Sadrian#define	AR934X_GPIO_COUNT		23
190253028Sadrian
191276609Sadrian/* GPIO functions */
192276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS7_EN           (1 << 9)
193276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS6_EN           (1 << 8)
194276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS5_EN           (1 << 7)
195276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS4_EN           (1 << 6)
196276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS3_EN           (1 << 5)
197276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS2_EN           (1 << 4)
198276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS1_EN           (1 << 3)
199276609Sadrian#define	AR934X_GPIO_FUNC_CLK_OBS0_EN           (1 << 2)
200276609Sadrian#define	AR934X_GPIO_FUNC_JTAG_DISABLE          (1 << 1)
201276609Sadrian
202276609Sadrian/* GPIO MUX output function: AR934X_GPIO_REG_OUT_FUNCx */
203276609Sadrian#define	AR934X_GPIO_OUT_GPIO		0	/* I'm a GPIO */
204276609Sadrian#define	AR934X_GPIO_OUT_SPI_CS1		7	/* I'm SPI CS1 */
205276609Sadrian#define	AR934X_GPIO_OUT_LED_LINK0	41	/* I'm switch phy link0 */
206276609Sadrian#define	AR934X_GPIO_OUT_LED_LINK1	42
207276609Sadrian#define	AR934X_GPIO_OUT_LED_LINK2	43
208276609Sadrian#define	AR934X_GPIO_OUT_LED_LINK3	44
209276609Sadrian#define	AR934X_GPIO_OUT_LED_LINK4	45
210276609Sadrian#define	AR934X_GPIO_OUT_EXT_LNA0	46	/* I'm WMAC EXT LNA chain 0 */
211276609Sadrian#define	AR934X_GPIO_OUT_EXT_LNA1	47	/* I'm WMAC EXT LNA chain 1 */
212276609Sadrian
213253028Sadrian/*
214253028Sadrian * SRIF block
215253028Sadrian */
216253028Sadrian#define	AR934X_SRIF_CPU_DPLL1_REG	(AR934X_SRIF_BASE + 0x1c0)
217253028Sadrian#define	AR934X_SRIF_CPU_DPLL2_REG	(AR934X_SRIF_BASE + 0x1c4)
218253028Sadrian#define	AR934X_SRIF_CPU_DPLL3_REG	(AR934X_SRIF_BASE + 0x1c8)
219253028Sadrian
220253028Sadrian#define	AR934X_SRIF_DDR_DPLL1_REG	(AR934X_SRIF_BASE + 0x240)
221253028Sadrian#define	AR934X_SRIF_DDR_DPLL2_REG	(AR934X_SRIF_BASE + 0x244)
222253028Sadrian#define	AR934X_SRIF_DDR_DPLL3_REG	(AR934X_SRIF_BASE + 0x248)
223253028Sadrian
224253028Sadrian#define	AR934X_SRIF_DPLL1_REFDIV_SHIFT	27
225253028Sadrian#define	AR934X_SRIF_DPLL1_REFDIV_MASK	0x1f
226253028Sadrian#define	AR934X_SRIF_DPLL1_NINT_SHIFT	18
227253028Sadrian#define	AR934X_SRIF_DPLL1_NINT_MASK	0x1ff
228253028Sadrian#define	AR934X_SRIF_DPLL1_NFRAC_MASK	0x0003ffff
229253028Sadrian
230253028Sadrian#define	AR934X_SRIF_DPLL2_LOCAL_PLL	(1 << 30)
231253028Sadrian#define	AR934X_SRIF_DPLL2_OUTDIV_SHIFT	13
232253028Sadrian#define	AR934X_SRIF_DPLL2_OUTDIV_MASK	0x7
233253028Sadrian
234256175Sadrian/* XXX verify! */
235256175Sadrian#define	AR934X_PLL_VAL_1000		0x16000000
236256175Sadrian#define	AR934X_PLL_VAL_100		0x00000101
237256175Sadrian#define	AR934X_PLL_VAL_10		0x00001616
238256175Sadrian
239253028Sadrian#endif	/* __AR934X_REG_H__ */
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