ar933x_chip.c revision 249126 
1/*-
2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar933x_chip.c 249126 2013-04-05 02:02:37Z adrian $");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar933xreg.h>
56
57#include <mips/atheros/ar71xx_cpudef.h>
58#include <mips/atheros/ar71xx_setup.h>
59
60#include <mips/atheros/ar71xx_chip.h>
61#include <mips/atheros/ar933x_chip.h>
62
63static void
64ar933x_chip_detect_mem_size(void)
65{
66}
67
68static void
69ar933x_chip_detect_sys_frequency(void)
70{
71	uint32_t clock_ctrl;
72	uint32_t cpu_config;
73	uint32_t freq;
74	uint32_t t;
75
76	t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
77	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
78		u_ar71xx_refclk = (40 * 1000 * 1000);
79	else
80		u_ar71xx_refclk = (25 * 1000 * 1000);
81
82	clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
83	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
84		u_ar71xx_cpu_freq = u_ar71xx_refclk;
85		u_ar71xx_ahb_freq = u_ar71xx_refclk;
86		u_ar71xx_ddr_freq = u_ar71xx_refclk;
87	} else {
88		cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
89
90		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
91		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
92		freq = u_ar71xx_refclk / t;
93
94		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
95		    AR933X_PLL_CPU_CONFIG_NINT_MASK;
96		freq *= t;
97
98		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
99		    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
100		if (t == 0)
101			t = 1;
102
103		freq >>= t;
104
105		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
106		     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
107		u_ar71xx_cpu_freq = freq / t;
108
109		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
110		      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
111		u_ar71xx_ddr_freq = freq / t;
112
113		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
114		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
115		u_ar71xx_ahb_freq = freq / t;
116	}
117}
118
119static void
120ar933x_chip_device_stop(uint32_t mask)
121{
122	uint32_t reg;
123
124	reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
125	ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
126}
127
128static void
129ar933x_chip_device_start(uint32_t mask)
130{
131	uint32_t reg;
132
133	reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
134	ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
135}
136
137static int
138ar933x_chip_device_stopped(uint32_t mask)
139{
140	uint32_t reg;
141
142	reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
143	return ((reg & mask) == mask);
144}
145
146static void
147ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
148{
149
150	/* XXX TODO */
151	return;
152}
153
154/*
155 * XXX TODO !!
156 */
157static void
158ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
159{
160
161	switch (unit) {
162	case 0:
163		/* XXX TODO */
164		break;
165	case 1:
166		/* XXX TODO */
167		break;
168	default:
169		printf("%s: invalid PLL set for arge unit: %d\n",
170		    __func__, unit);
171		return;
172	}
173}
174
175static void
176ar933x_chip_ddr_flush_ge(int unit)
177{
178
179	switch (unit) {
180	case 0:
181		ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
182		break;
183	case 1:
184		ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
185		break;
186	default:
187		printf("%s: invalid DDR flush for arge unit: %d\n",
188		    __func__, unit);
189		return;
190	}
191}
192
193static void
194ar933x_chip_ddr_flush_ip2(void)
195{
196
197	ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
198}
199
200static uint32_t
201ar933x_chip_get_eth_pll(unsigned int mac, int speed)
202{
203	uint32_t pll;
204
205	switch (speed) {
206	case 10:
207		pll = AR933X_PLL_VAL_10;
208		break;
209	case 100:
210		pll = AR933X_PLL_VAL_100;
211		break;
212	case 1000:
213		pll = AR933X_PLL_VAL_1000;
214		break;
215	default:
216		printf("%s%d: invalid speed %d\n", __func__, mac, speed);
217		pll = 0;
218	}
219	return (pll);
220}
221
222static void
223ar933x_chip_init_usb_peripheral(void)
224{
225	ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
226	DELAY(100);
227
228	ar71xx_device_start(AR933X_RESET_USB_HOST);
229	DELAY(100);
230
231	ar71xx_device_start(AR933X_RESET_USB_PHY);
232	DELAY(100);
233}
234
235struct ar71xx_cpu_def ar933x_chip_def = {
236	&ar933x_chip_detect_mem_size,
237	&ar933x_chip_detect_sys_frequency,
238	&ar933x_chip_device_stop,
239	&ar933x_chip_device_start,
240	&ar933x_chip_device_stopped,
241	&ar933x_chip_set_pll_ge,
242	&ar933x_chip_set_mii_speed,
243	&ar71xx_chip_set_mii_if,
244	&ar933x_chip_ddr_flush_ge,
245	&ar933x_chip_get_eth_pll,
246	&ar933x_chip_ddr_flush_ip2,
247	&ar933x_chip_init_usb_peripheral
248};
249