ar91xx_chip.c revision 234326 
1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar91xx_chip.c 234326 2012-04-15 22:34:22Z adrian $");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar71xx_cpudef.h>
56#include <mips/atheros/ar71xx_chip.h>
57#include <mips/atheros/ar91xxreg.h>
58#include <mips/atheros/ar91xx_chip.h>
59
60#include <mips/sentry5/s5reg.h>
61
62static void
63ar91xx_chip_detect_mem_size(void)
64{
65}
66
67static void
68ar91xx_chip_detect_sys_frequency(void)
69{
70	uint32_t pll;
71	uint32_t freq;
72	uint32_t div;
73
74	pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG);
75
76	div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
77	freq = div * AR91XX_BASE_FREQ;
78	u_ar71xx_cpu_freq = freq;
79
80	div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
81	u_ar71xx_ddr_freq = freq / div;
82
83	div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
84	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
85}
86
87static void
88ar91xx_chip_device_stop(uint32_t mask)
89{
90	uint32_t reg;
91
92	reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
93	ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg | mask);
94}
95
96static void
97ar91xx_chip_device_start(uint32_t mask)
98{
99	uint32_t reg;
100
101	reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
102	ATH_WRITE_REG(AR91XX_RESET_REG_RESET_MODULE, reg & ~mask);
103}
104
105static int
106ar91xx_chip_device_stopped(uint32_t mask)
107{
108	uint32_t reg;
109
110	reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE);
111	return ((reg & mask) == mask);
112}
113
114static void
115ar91xx_chip_set_pll_ge(int unit, int speed)
116{
117	uint32_t pll;
118
119	switch(speed) {
120	case 10:
121		pll = AR91XX_PLL_VAL_10;
122		break;
123	case 100:
124		pll = AR91XX_PLL_VAL_100;
125		break;
126	case 1000:
127		pll = AR91XX_PLL_VAL_1000;
128		break;
129	default:
130		printf("%s%d: invalid speed %d\n",
131		    __func__, unit, speed);
132		return;
133	}
134	switch (unit) {
135	case 0:
136		ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
137		    AR91XX_PLL_REG_ETH0_INT_CLOCK, pll,
138		    AR91XX_ETH0_PLL_SHIFT);
139		break;
140	case 1:
141		ar71xx_write_pll(AR91XX_PLL_REG_ETH_CONFIG,
142		    AR91XX_PLL_REG_ETH1_INT_CLOCK, pll,
143		    AR91XX_ETH1_PLL_SHIFT);
144		break;
145	default:
146		printf("%s: invalid PLL set for arge unit: %d\n",
147		    __func__, unit);
148		return;
149	}
150}
151
152static void
153ar91xx_chip_ddr_flush_ge(int unit)
154{
155
156	switch (unit) {
157	case 0:
158		ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
159		break;
160	case 1:
161		ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
162		break;
163	default:
164		printf("%s: invalid DDR flush for arge unit: %d\n",
165		    __func__, unit);
166		return;
167	}
168}
169
170static void
171ar91xx_chip_ddr_flush_ip2(void)
172{
173
174	ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC);
175}
176
177
178static uint32_t
179ar91xx_chip_get_eth_pll(unsigned int mac, int speed)
180{
181
182	return 0;
183}
184
185static void
186ar91xx_chip_init_usb_peripheral(void)
187{
188
189	ar71xx_device_stop(AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE);
190	DELAY(100);
191
192	ar71xx_device_start(RST_RESET_USB_HOST);
193	DELAY(100);
194
195	ar71xx_device_start(RST_RESET_USB_PHY);
196	DELAY(100);
197
198	/* Wireless */
199	ar71xx_device_stop(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
200	DELAY(1000);
201
202	ar71xx_device_start(AR91XX_RST_RESET_MODULE_AMBA2WMAC);
203	DELAY(1000);
204}
205
206struct ar71xx_cpu_def ar91xx_chip_def = {
207	&ar91xx_chip_detect_mem_size,
208	&ar91xx_chip_detect_sys_frequency,
209	&ar91xx_chip_device_stop,
210	&ar91xx_chip_device_start,
211	&ar91xx_chip_device_stopped,
212	&ar91xx_chip_set_pll_ge,
213	&ar71xx_chip_set_mii_speed,
214	&ar91xx_chip_ddr_flush_ge,
215	&ar91xx_chip_get_eth_pll,
216	&ar91xx_chip_ddr_flush_ip2,
217	&ar91xx_chip_init_usb_peripheral,
218};
219