ar724xreg.h revision 280313
138889Sjdp/*- 238889Sjdp * Copyright (c) 2010 Adrian Chadd 338889Sjdp * All rights reserved. 438889Sjdp * 538889Sjdp * Redistribution and use in source and binary forms, with or without 638889Sjdp * modification, are permitted provided that the following conditions 738889Sjdp * are met: 838889Sjdp * 1. Redistributions of source code must retain the above copyright 938889Sjdp * notice, this list of conditions and the following disclaimer. 1038889Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1138889Sjdp * notice, this list of conditions and the following disclaimer in the 1238889Sjdp * documentation and/or other materials provided with the distribution. 1333965Sjdp * 1433965Sjdp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1533965Sjdp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1633965Sjdp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1733965Sjdp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1838889Sjdp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1933965Sjdp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2033965Sjdp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2133965Sjdp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2233965Sjdp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2333965Sjdp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2433965Sjdp * SUCH DAMAGE. 2533965Sjdp */ 2633965Sjdp 2733965Sjdp/* $FreeBSD: head/sys/mips/atheros/ar724xreg.h 280313 2015-03-21 05:59:45Z adrian $ */ 2833965Sjdp 2933965Sjdp#ifndef __AR72XX_REG_H__ 3033965Sjdp#define __AR72XX_REG_H__ 3133965Sjdp 3233965Sjdp#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 3338889Sjdp#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 3438889Sjdp 3538889Sjdp#define AR724X_PLL_DIV_SHIFT 0 3638889Sjdp#define AR724X_PLL_DIV_MASK 0x3ff 3738889Sjdp#define AR724X_PLL_REF_DIV_SHIFT 10 3838889Sjdp#define AR724X_PLL_REF_DIV_MASK 0xf 3938889Sjdp#define AR724X_AHB_DIV_SHIFT 19 4038889Sjdp#define AR724X_AHB_DIV_MASK 0x1 4138889Sjdp#define AR724X_DDR_DIV_SHIFT 22 4238889Sjdp#define AR724X_DDR_DIV_MASK 0x3 4338889Sjdp 4438889Sjdp#define AR724X_PLL_VAL_1000 0x00110000 4538889Sjdp#define AR724X_PLL_VAL_100 0x00001099 4638889Sjdp#define AR724X_PLL_VAL_10 0x00991099 4738889Sjdp 4838889Sjdp#define AR724X_BASE_FREQ 5000000 4938889Sjdp 5038889Sjdp#define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c) 5138889Sjdp#define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80) 5233965Sjdp#define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84) 5333965Sjdp#define AR724X_DDR_REG_FLUSH_PCIE (AR71XX_DDR_CONFIG + 0x88) 5433965Sjdp 5533965Sjdp#define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c 5633965Sjdp#define AR724X_RESET_USB_HOST (1 << 5) 5733965Sjdp#define AR724X_RESET_USB_PHY (1 << 4) 5833965Sjdp#define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3) 5933965Sjdp 6033965Sjdp#define AR724X_RESET_GE1_MDIO (1 << 23) 6133965Sjdp#define AR724X_RESET_GE0_MDIO (1 << 22) 6233965Sjdp#define AR724X_RESET_PCIE_PHY_SERIAL (1 << 10) 6333965Sjdp#define AR724X_RESET_PCIE_PHY (1 << 7) 6433965Sjdp#define AR724X_RESET_PCIE (1 << 6) 6533965Sjdp#define AR724X_RESET_USB_HOST (1 << 5) 6633965Sjdp#define AR724X_RESET_USB_PHY (1 << 4) 6733965Sjdp#define AR724X_RESET_USBSUS_OVERRIDE (1 << 3) 6833965Sjdp 6933965Sjdp/* XXX so USB requires different init code? -adrian */ 7033965Sjdp#define AR7240_OHCI_BASE 0x1b000000 7133965Sjdp#define AR7240_OHCI_SIZE 0x01000000 7233965Sjdp 7333965Sjdp#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) 7433965Sjdp#define AR724X_PCI_CRP_SIZE 0x100 7533965Sjdp#define AR724X_PCI_CFG_BASE 0x14000000 7633965Sjdp#define AR724X_PCI_CFG_SIZE 0x1000 7733965Sjdp 7833965Sjdp#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) 7933965Sjdp#define AR724X_PCI_CTRL_SIZE 0x100 8038889Sjdp 8138889Sjdp/* PCI config registers - AR724X_PCI_CTRL_BASE */ 8238889Sjdp#define AR724X_PCI_APP 0x180f0000 8338889Sjdp#define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) 8438889Sjdp#define AR724X_PCI_RESET 0x180f0018 8538889Sjdp#define AR724X_PCI_RESET_LINK_UP (1 << 0) 8638889Sjdp#define AR724X_PCI_INTR_STATUS 0x180f004c 8738889Sjdp#define AR724X_PCI_INTR_MASK 0x180f0050 8838889Sjdp#define AR724X_PCI_INTR_DEV0 (1 << 14) 8938889Sjdp 9038889Sjdp#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 << 19) 9138889Sjdp#define AR724X_GPIO_FUNC_SPI_EN (1 << 18) 9238889Sjdp#define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 << 14) 9338889Sjdp#define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 << 13) 9438889Sjdp#define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 << 12) 9538889Sjdp#define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 << 11) 9638889Sjdp#define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 << 10) 9738889Sjdp#define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 << 9) 9838889Sjdp#define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 << 8) 9938889Sjdp#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 << 7) 10038889Sjdp#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 << 6) 10138889Sjdp#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 << 5) 10238889Sjdp#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 << 4) 10338889Sjdp#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 << 3) 10438889Sjdp#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 << 2) 10538889Sjdp#define AR724X_GPIO_FUNC_UART_EN (1 << 1) 10638889Sjdp#define AR724X_GPIO_FUNC_JTAG_DISABLE (1 << 0) 10738889Sjdp 10838889Sjdp#endif 10938889Sjdp