ar724xreg.h revision 219591
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: head/sys/mips/atheros/ar724xreg.h 219591 2011-03-13 08:36:57Z adrian $ */ 28 29#ifndef __AR72XX_REG_H__ 30#define __AR72XX_REG_H__ 31 32#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 33#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 34 35#define AR724X_PLL_DIV_SHIFT 0 36#define AR724X_PLL_DIV_MASK 0x3ff 37#define AR724X_PLL_REF_DIV_SHIFT 10 38#define AR724X_PLL_REF_DIV_MASK 0xf 39#define AR724X_AHB_DIV_SHIFT 19 40#define AR724X_AHB_DIV_MASK 0x1 41#define AR724X_DDR_DIV_SHIFT 22 42#define AR724X_DDR_DIV_MASK 0x3 43 44#define AR724X_PLL_VAL_1000 0x00110000 45#define AR724X_PLL_VAL_100 0x00001099 46#define AR724X_PLL_VAL_10 0x00991099 47 48#define AR724X_BASE_FREQ 5000000 49 50#define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c) 51#define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80) 52 53#define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c 54#define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3) 55 56/* XXX so USB requires different init code? -adrian */ 57#define AR7240_OHCI_BASE 0x1b000000 58#define AR7240_OHCI_SIZE 0x01000000 59#define AR724X_DDR_REG_FLUSH_USB (AR71XX_DDR_CONFIG + 0x84) 60 61#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) 62#define AR724X_PCI_CRP_SIZE 0x100 63 64#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) 65#define AR724X_PCI_CTRL_SIZE 0x100 66 67#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN (1 >> 19) 68#define AR724X_GPIO_FUNC_SPI_EN (1 >> 18) 69#define AR724X_GPIO_FUNC_SPI_CS_EN2 (1 >> 14) 70#define AR724X_GPIO_FUNC_SPI_CS_EN1 (1 >> 13) 71#define AR724X_GPIO_FUNC_CLK_OBS5_EN (1 >> 12) 72#define AR724X_GPIO_FUNC_CLK_OBS4_EN (1 >> 11) 73#define AR724X_GPIO_FUNC_CLK_OBS3_EN (1 >> 10) 74#define AR724X_GPIO_FUNC_CLK_OBS2_EN (1 >> 9) 75#define AR724X_GPIO_FUNC_CLK_OBS1_EN (1 >> 8) 76#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN (1 >> 7) 77#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN (1 >> 6) 78#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN (1 >> 5) 79#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN (1 >> 4) 80#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN (1 >> 3) 81#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN (1 >> 2) 82#define AR724X_GPIO_FUNC_UART_EN (1 >> 1) 83#define AR724X_GPIO_FUNC_JTAG_DISABLE (1 >> 0) 84 85#define AR724X_GPIO_COUNT 18 86 87#endif 88