ar71xx_pci_bus_space.c revision 302408
1226031Sstas/*-
2226031Sstas * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3226031Sstas * All rights reserved.
4226031Sstas *
5226031Sstas * Redistribution and use in source and binary forms, with or without
6226031Sstas * modification, are permitted provided that the following conditions
7226031Sstas * are met:
8226031Sstas * 1. Redistributions of source code must retain the above copyright
9226031Sstas *    notice unmodified, this list of conditions, and the following
10226031Sstas *    disclaimer.
11226031Sstas * 2. Redistributions in binary form must reproduce the above copyright
12226031Sstas *    notice, this list of conditions and the following disclaimer in the
13226031Sstas *    documentation and/or other materials provided with the distribution.
14226031Sstas *
15226031Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16226031Sstas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17226031Sstas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18226031Sstas * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19226031Sstas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20226031Sstas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21226031Sstas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22226031Sstas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23226031Sstas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24226031Sstas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25226031Sstas * SUCH DAMAGE.
26226031Sstas */
27226031Sstas#include <sys/cdefs.h>
28226031Sstas__FBSDID("$FreeBSD: stable/11/sys/mips/atheros/ar71xx_pci_bus_space.c 202175 2010-01-12 21:36:08Z imp $");
29226031Sstas
30226031Sstas#include <sys/param.h>
31226031Sstas#include <sys/systm.h>
32226031Sstas#include <sys/bus.h>
33226031Sstas#include <sys/endian.h>
34226031Sstas
35226031Sstas#include <machine/bus.h>
36226031Sstas#include <mips/atheros/ar71xx_pci_bus_space.h>
37226031Sstas
38226031Sstasstatic bs_r_1_s_proto(pcimem);
39226031Sstasstatic bs_r_2_s_proto(pcimem);
40226031Sstasstatic bs_r_4_s_proto(pcimem);
41226031Sstasstatic bs_w_1_s_proto(pcimem);
42226031Sstasstatic bs_w_2_s_proto(pcimem);
43226031Sstasstatic bs_w_4_s_proto(pcimem);
44226031Sstas
45226031Sstas/*
46226031Sstas * Bus space that handles offsets in word for 1/2 bytes read/write access.
47226031Sstas * Byte order of values is handled by device drivers itself.
48226031Sstas */
49226031Sstasstatic struct bus_space bus_space_pcimem = {
50226031Sstas	/* cookie */
51226031Sstas	(void *) 0,
52226031Sstas
53226031Sstas	/* mapping/unmapping */
54226031Sstas	generic_bs_map,
55226031Sstas	generic_bs_unmap,
56226031Sstas	generic_bs_subregion,
57226031Sstas
58226031Sstas	/* allocation/deallocation */
59226031Sstas	NULL,
60226031Sstas	NULL,
61226031Sstas
62226031Sstas	/* barrier */
63226031Sstas	generic_bs_barrier,
64226031Sstas
65226031Sstas	/* read (single) */
66226031Sstas	generic_bs_r_1,
67226031Sstas	generic_bs_r_2,
68226031Sstas	generic_bs_r_4,
69226031Sstas	NULL,
70226031Sstas
71226031Sstas	/* read multiple */
72226031Sstas	generic_bs_rm_1,
73226031Sstas	generic_bs_rm_2,
74226031Sstas	generic_bs_rm_4,
75226031Sstas	NULL,
76226031Sstas
77226031Sstas	/* read region */
78226031Sstas	generic_bs_rr_1,
79226031Sstas	generic_bs_rr_2,
80226031Sstas	generic_bs_rr_4,
81226031Sstas	NULL,
82226031Sstas
83226031Sstas	/* write (single) */
84226031Sstas	generic_bs_w_1,
85226031Sstas	generic_bs_w_2,
86226031Sstas	generic_bs_w_4,
87226031Sstas	NULL,
88226031Sstas
89226031Sstas	/* write multiple */
90226031Sstas	generic_bs_wm_1,
91226031Sstas	generic_bs_wm_2,
92226031Sstas	generic_bs_wm_4,
93226031Sstas	NULL,
94226031Sstas
95226031Sstas	/* write region */
96226031Sstas	NULL,
97226031Sstas	generic_bs_wr_2,
98226031Sstas	generic_bs_wr_4,
99226031Sstas	NULL,
100226031Sstas
101226031Sstas	/* set multiple */
102226031Sstas	NULL,
103226031Sstas	NULL,
104226031Sstas	NULL,
105226031Sstas	NULL,
106226031Sstas
107226031Sstas	/* set region */
108226031Sstas	NULL,
109226031Sstas	generic_bs_sr_2,
110226031Sstas	generic_bs_sr_4,
111226031Sstas	NULL,
112226031Sstas
113226031Sstas	/* copy */
114226031Sstas	NULL,
115226031Sstas	generic_bs_c_2,
116226031Sstas	NULL,
117226031Sstas	NULL,
118226031Sstas
119226031Sstas	/* read (single) stream */
120226031Sstas	pcimem_bs_r_1_s,
121226031Sstas	pcimem_bs_r_2_s,
122226031Sstas	pcimem_bs_r_4_s,
123226031Sstas	NULL,
124226031Sstas
125226031Sstas	/* read multiple stream */
126226031Sstas	generic_bs_rm_1,
127226031Sstas	generic_bs_rm_2,
128226031Sstas	generic_bs_rm_4,
129226031Sstas	NULL,
130226031Sstas
131226031Sstas	/* read region stream */
132226031Sstas	generic_bs_rr_1,
133226031Sstas	generic_bs_rr_2,
134226031Sstas	generic_bs_rr_4,
135226031Sstas	NULL,
136226031Sstas
137226031Sstas	/* write (single) stream */
138226031Sstas	pcimem_bs_w_1_s,
139226031Sstas	pcimem_bs_w_2_s,
140226031Sstas	pcimem_bs_w_4_s,
141226031Sstas	NULL,
142226031Sstas
143226031Sstas	/* write multiple stream */
144226031Sstas	generic_bs_wm_1,
145226031Sstas	generic_bs_wm_2,
146226031Sstas	generic_bs_wm_4,
147226031Sstas	NULL,
148226031Sstas
149226031Sstas	/* write region stream */
150226031Sstas	NULL,
151226031Sstas	generic_bs_wr_2,
152226031Sstas	generic_bs_wr_4,
153226031Sstas	NULL,
154226031Sstas};
155226031Sstas
156226031Sstasbus_space_tag_t ar71xx_bus_space_pcimem = &bus_space_pcimem;
157226031Sstas
158226031Sstasstatic uint8_t
159226031Sstaspcimem_bs_r_1_s(void *t, bus_space_handle_t h, bus_size_t o)
160226031Sstas{
161226031Sstas
162226031Sstas	return readb(h + (o &~ 3) + (3 - (o & 3)));
163226031Sstas}
164226031Sstas
165226031Sstasstatic void
166226031Sstaspcimem_bs_w_1_s(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
167226031Sstas{
168226031Sstas
169226031Sstas	writeb(h + (o &~ 3) + (3 - (o & 3)), v);
170226031Sstas}
171226031Sstas
172226031Sstasstatic uint16_t
173226031Sstaspcimem_bs_r_2_s(void *t, bus_space_handle_t h, bus_size_t o)
174226031Sstas{
175226031Sstas
176226031Sstas	return readw(h + (o &~ 3) + (2 - (o & 3)));
177226031Sstas}
178226031Sstas
179226031Sstasstatic void
180226031Sstaspcimem_bs_w_2_s(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
181226031Sstas{
182226031Sstas
183226031Sstas	writew(h + (o &~ 3) + (2 - (o & 3)), v);
184226031Sstas}
185226031Sstas
186226031Sstasstatic uint32_t
187226031Sstaspcimem_bs_r_4_s(void *t, bus_space_handle_t h, bus_size_t o)
188226031Sstas{
189226031Sstas
190226031Sstas	return le32toh(readl(h + o));
191226031Sstas}
192226031Sstas
193226031Sstasstatic void
194226031Sstaspcimem_bs_w_4_s(void *t, bus_space_handle_t h, bus_size_t o, uint32_t v)
195226031Sstas{
196226031Sstas
197226031Sstas	writel(h + o, htole32(v));
198226031Sstas}
199226031Sstas