ar71xx_pci.c revision 287882
1187706Sgonzo/*- 2187706Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3187706Sgonzo * All rights reserved. 4187706Sgonzo * 5187706Sgonzo * Redistribution and use in source and binary forms, with or without 6187706Sgonzo * modification, are permitted provided that the following conditions 7187706Sgonzo * are met: 8187706Sgonzo * 1. Redistributions of source code must retain the above copyright 9187706Sgonzo * notice unmodified, this list of conditions, and the following 10187706Sgonzo * disclaimer. 11187706Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12187706Sgonzo * notice, this list of conditions and the following disclaimer in the 13187706Sgonzo * documentation and/or other materials provided with the distribution. 14187706Sgonzo * 15187706Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16187706Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17187706Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18187706Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19187706Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20187706Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21187706Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22187706Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23187706Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24187706Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25187706Sgonzo * SUCH DAMAGE. 26187706Sgonzo */ 27187706Sgonzo 28187706Sgonzo#include <sys/cdefs.h> 29187706Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_pci.c 287882 2015-09-16 23:34:51Z zbb $"); 30187706Sgonzo 31230195Sadrian#include "opt_ar71xx.h" 32230195Sadrian 33187706Sgonzo#include <sys/param.h> 34187706Sgonzo#include <sys/systm.h> 35187706Sgonzo 36187706Sgonzo#include <sys/bus.h> 37187706Sgonzo#include <sys/interrupt.h> 38187706Sgonzo#include <sys/malloc.h> 39187706Sgonzo#include <sys/kernel.h> 40187706Sgonzo#include <sys/module.h> 41187706Sgonzo#include <sys/rman.h> 42234365Sadrian#include <sys/lock.h> 43234365Sadrian#include <sys/mutex.h> 44187706Sgonzo 45187706Sgonzo#include <vm/vm.h> 46187706Sgonzo#include <vm/pmap.h> 47187706Sgonzo#include <vm/vm_extern.h> 48187706Sgonzo 49187706Sgonzo#include <machine/bus.h> 50187706Sgonzo#include <machine/cpu.h> 51210900Sgonzo#include <machine/intr_machdep.h> 52187706Sgonzo#include <machine/pmap.h> 53187706Sgonzo 54187706Sgonzo#include <dev/pci/pcivar.h> 55187706Sgonzo#include <dev/pci/pcireg.h> 56187706Sgonzo 57187706Sgonzo#include <dev/pci/pcib_private.h> 58187706Sgonzo#include "pcib_if.h" 59187706Sgonzo 60192161Sgonzo#include <mips/atheros/ar71xxreg.h> 61192161Sgonzo#include <mips/atheros/ar71xx_pci_bus_space.h> 62187706Sgonzo 63211478Sadrian#include <mips/atheros/ar71xx_cpudef.h> 64211478Sadrian 65234217Sadrian#ifdef AR71XX_ATH_EEPROM 66234485Sadrian#include <mips/atheros/ar71xx_fixup.h> 67234217Sadrian#endif /* AR71XX_ATH_EEPROM */ 68234217Sadrian 69234366Sadrian#undef AR71XX_PCI_DEBUG 70234366Sadrian#ifdef AR71XX_PCI_DEBUG 71234366Sadrian#define dprintf printf 72187706Sgonzo#else 73234366Sadrian#define dprintf(x, arg...) 74187706Sgonzo#endif 75187706Sgonzo 76234365Sadrianstruct mtx ar71xx_pci_mtx; 77234365SadrianMTX_SYSINIT(ar71xx_pci_mtx, &ar71xx_pci_mtx, "ar71xx PCI space mutex", 78234365Sadrian MTX_SPIN); 79234365Sadrian 80187706Sgonzostruct ar71xx_pci_softc { 81187706Sgonzo device_t sc_dev; 82187706Sgonzo 83187706Sgonzo int sc_busno; 84245112Smonthadar int sc_baseslot; 85187706Sgonzo struct rman sc_mem_rman; 86187706Sgonzo struct rman sc_irq_rman; 87187706Sgonzo 88191872Sgonzo struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 89210900Sgonzo mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS]; 90187706Sgonzo struct resource *sc_irq; 91187706Sgonzo void *sc_ih; 92187706Sgonzo}; 93187706Sgonzo 94191872Sgonzostatic int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 95191872Sgonzo driver_filter_t *, driver_intr_t *, void *, void **); 96191872Sgonzostatic int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *, 97191872Sgonzo void *); 98191872Sgonzostatic int ar71xx_pci_intr(void *); 99191872Sgonzo 100234366Sadrianstatic void 101192822Sgonzoar71xx_pci_mask_irq(void *source) 102191872Sgonzo{ 103191872Sgonzo uint32_t reg; 104192822Sgonzo unsigned int irq = (unsigned int)source; 105191872Sgonzo 106234365Sadrian /* XXX is the PCI lock required here? */ 107191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 108194273Sgonzo /* flush */ 109194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 110191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq)); 111191872Sgonzo} 112191872Sgonzo 113234366Sadrianstatic void 114192822Sgonzoar71xx_pci_unmask_irq(void *source) 115191872Sgonzo{ 116191872Sgonzo uint32_t reg; 117192822Sgonzo unsigned int irq = (unsigned int)source; 118191872Sgonzo 119234365Sadrian /* XXX is the PCI lock required here? */ 120191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 121191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); 122194273Sgonzo /* flush */ 123194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 124191872Sgonzo} 125191872Sgonzo 126234366Sadrian/* 127234366Sadrian * get bitmask for bytes of interest: 128234366Sadrian * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte 129187706Sgonzo * from register 7. Bitmask would be: 0111 130187706Sgonzo */ 131187706Sgonzostatic uint32_t 132187706Sgonzoar71xx_get_bytes_to_read(int reg, int bytes) 133187706Sgonzo{ 134187706Sgonzo uint32_t bytes_to_read = 0; 135234366Sadrian 136187706Sgonzo if ((bytes % 4) == 0) 137187706Sgonzo bytes_to_read = 0; 138187706Sgonzo else if ((bytes % 4) == 1) 139187706Sgonzo bytes_to_read = (~(1 << (reg % 4))) & 0xf; 140187706Sgonzo else if ((bytes % 4) == 2) 141187706Sgonzo bytes_to_read = (~(3 << (reg % 4))) & 0xf; 142187706Sgonzo else 143187706Sgonzo panic("%s: wrong combination", __func__); 144187706Sgonzo 145187706Sgonzo return (bytes_to_read); 146187706Sgonzo} 147187706Sgonzo 148234366Sadrianstatic int 149187706Sgonzoar71xx_pci_check_bus_error(void) 150187706Sgonzo{ 151187706Sgonzo uint32_t error, addr, has_errors = 0; 152234365Sadrian 153234365Sadrian mtx_assert(&ar71xx_pci_mtx, MA_OWNED); 154234365Sadrian 155187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; 156187706Sgonzo dprintf("%s: PCI error = %02x\n", __func__, error); 157187706Sgonzo if (error) { 158187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); 159187706Sgonzo 160187706Sgonzo /* Do not report it yet */ 161187706Sgonzo#if 0 162187706Sgonzo printf("PCI bus error %d at addr 0x%08x\n", error, addr); 163187706Sgonzo#endif 164187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_ERROR, error); 165187706Sgonzo has_errors = 1; 166187706Sgonzo } 167187706Sgonzo 168187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; 169187706Sgonzo dprintf("%s: AHB error = %02x\n", __func__, error); 170187706Sgonzo if (error) { 171187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); 172187706Sgonzo /* Do not report it yet */ 173187706Sgonzo#if 0 174187706Sgonzo printf("AHB bus error %d at addr 0x%08x\n", error, addr); 175187706Sgonzo#endif 176187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); 177187706Sgonzo has_errors = 1; 178187706Sgonzo } 179187706Sgonzo 180187706Sgonzo return (has_errors); 181187706Sgonzo} 182187706Sgonzo 183187706Sgonzostatic uint32_t 184187706Sgonzoar71xx_pci_make_addr(int bus, int slot, int func, int reg) 185187706Sgonzo{ 186187706Sgonzo if (bus == 0) { 187187706Sgonzo return ((1 << slot) | (func << 8) | (reg & ~3)); 188187706Sgonzo } else { 189234366Sadrian return ((bus << 16) | (slot << 11) | (func << 8) 190187706Sgonzo | (reg & ~3) | 1); 191187706Sgonzo } 192187706Sgonzo} 193187706Sgonzo 194187706Sgonzostatic int 195234366Sadrianar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes, 196187706Sgonzo uint32_t cmd) 197187706Sgonzo{ 198187706Sgonzo uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3)); 199234365Sadrian 200234365Sadrian mtx_assert(&ar71xx_pci_mtx, MA_OWNED); 201234365Sadrian 202234366Sadrian cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4); 203187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); 204187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); 205187706Sgonzo 206187706Sgonzo dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 207187706Sgonzo bus, slot, func, reg, bytes, addr, cmd); 208187706Sgonzo 209187706Sgonzo return ar71xx_pci_check_bus_error(); 210187706Sgonzo} 211187706Sgonzo 212187706Sgonzostatic uint32_t 213234366Sadrianar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 214194059Sgonzo u_int reg, int bytes) 215187706Sgonzo{ 216187706Sgonzo uint32_t data; 217234205Sadrian uint32_t shift, mask; 218187706Sgonzo 219187706Sgonzo /* register access is 32-bit aligned */ 220187706Sgonzo shift = (reg & 3) * 8; 221234306Sadrian 222234306Sadrian /* Create a mask based on the width, post-shift */ 223234306Sadrian if (bytes == 2) 224234306Sadrian mask = 0xffff; 225234306Sadrian else if (bytes == 1) 226234306Sadrian mask = 0xff; 227187706Sgonzo else 228187706Sgonzo mask = 0xffffffff; 229187706Sgonzo 230187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 231187706Sgonzo func, reg, bytes); 232187706Sgonzo 233234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 234234204Sadrian if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 235234204Sadrian PCI_CONF_CMD_READ) == 0) 236234204Sadrian data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); 237234204Sadrian else 238234204Sadrian data = -1; 239234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 240187706Sgonzo 241187706Sgonzo /* get request bytes from 32-bit word */ 242187706Sgonzo data = (data >> shift) & mask; 243187706Sgonzo 244234366Sadrian dprintf("%s: read 0x%x\n", __func__, data); 245187706Sgonzo 246187706Sgonzo return (data); 247187706Sgonzo} 248187706Sgonzo 249187706Sgonzostatic void 250234204Sadrianar71xx_pci_local_write(device_t dev, uint32_t reg, uint32_t data, int bytes) 251187706Sgonzo{ 252187706Sgonzo uint32_t cmd; 253187706Sgonzo 254234204Sadrian dprintf("%s: local write reg %d(%d)\n", __func__, reg, bytes); 255234204Sadrian 256234204Sadrian data = data << (8*(reg % 4)); 257234204Sadrian cmd = PCI_LCONF_CMD_WRITE | (reg & ~3); 258234204Sadrian cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 20); 259234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 260234204Sadrian ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 261234204Sadrian ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); 262234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 263234204Sadrian} 264234204Sadrian 265234204Sadrianstatic void 266234204Sadrianar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 267234204Sadrian u_int reg, uint32_t data, int bytes) 268234204Sadrian{ 269234204Sadrian 270234204Sadrian dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 271187706Sgonzo func, reg, bytes); 272187706Sgonzo 273187706Sgonzo data = data << (8*(reg % 4)); 274234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 275234204Sadrian if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 276234204Sadrian PCI_CONF_CMD_WRITE) == 0) 277234204Sadrian ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); 278234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 279187706Sgonzo} 280187706Sgonzo 281230148Sadrian#ifdef AR71XX_ATH_EEPROM 282230148Sadrian/* 283230148Sadrian * Some embedded boards (eg AP94) have the MAC attached via PCI but they 284230148Sadrian * don't have the MAC-attached EEPROM. The register initialisation 285230148Sadrian * values and calibration data are stored in the on-board flash. 286230148Sadrian * This routine initialises the NIC via the EEPROM register contents 287230148Sadrian * before the probe/attach routines get a go at things. 288230148Sadrian */ 289230148Sadrianstatic void 290230148Sadrianar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func, 291234485Sadrian long flash_addr, int len) 292230148Sadrian{ 293230148Sadrian uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr); 294230148Sadrian uint32_t reg, val, bar0; 295230148Sadrian 296234217Sadrian if (bootverbose) 297234217Sadrian device_printf(dev, "%s: flash_addr=%lx, cal_data=%p\n", 298234217Sadrian __func__, flash_addr, cal_data); 299230148Sadrian 300230148Sadrian /* XXX check 0xa55a */ 301230148Sadrian /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */ 302230148Sadrian bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4); 303230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), 304230148Sadrian AR71XX_PCI_MEM_BASE, 4); 305230148Sadrian 306230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 307230148Sadrian val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 308230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 309230148Sadrian 310230148Sadrian cal_data += 3; 311230148Sadrian while (*cal_data != 0xffff) { 312230148Sadrian reg = *cal_data++; 313230148Sadrian val = *cal_data++; 314230148Sadrian val |= (*cal_data++) << 16; 315234217Sadrian if (bootverbose) 316234217Sadrian printf(" reg: %x, val=%x\n", reg, val); 317230148Sadrian 318230148Sadrian /* Write eeprom fixup data to device memory */ 319230148Sadrian ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val); 320230148Sadrian DELAY(100); 321230148Sadrian } 322230148Sadrian 323230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 324230148Sadrian val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 325230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 326230148Sadrian 327230148Sadrian /* Write the saved bar(0) address */ 328230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4); 329230148Sadrian} 330230148Sadrian 331230148Sadrianstatic void 332230148Sadrianar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func) 333230148Sadrian{ 334230148Sadrian long int flash_addr; 335234485Sadrian char buf[64]; 336234485Sadrian int size; 337230148Sadrian 338230148Sadrian /* 339230148Sadrian * Check whether the given slot has a hint to poke. 340230148Sadrian */ 341234217Sadrian if (bootverbose) 342234217Sadrian device_printf(dev, "%s: checking dev %s, %d/%d/%d\n", 343230148Sadrian __func__, device_get_nameunit(dev), bus, slot, func); 344234485Sadrian 345230148Sadrian snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr", 346230148Sadrian bus, slot, func); 347230148Sadrian 348230148Sadrian if (resource_long_value(device_get_name(dev), device_get_unit(dev), 349230148Sadrian buf, &flash_addr) == 0) { 350234485Sadrian snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size", 351234485Sadrian bus, slot, func); 352234485Sadrian if (resource_int_value(device_get_name(dev), 353234485Sadrian device_get_unit(dev), buf, &size) != 0) { 354234485Sadrian device_printf(dev, 355234485Sadrian "%s: missing hint '%s', aborting EEPROM\n", 356234485Sadrian __func__, buf); 357234485Sadrian return; 358234485Sadrian } 359234485Sadrian 360234485Sadrian 361234217Sadrian device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n", 362234217Sadrian flash_addr, bus, slot, func); 363234485Sadrian ar71xx_pci_fixup(dev, bus, slot, func, flash_addr, size); 364234217Sadrian ar71xx_pci_slot_create_eeprom_firmware(dev, bus, slot, func, 365234485Sadrian flash_addr, size); 366230148Sadrian } 367230148Sadrian} 368230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 369230148Sadrian 370187706Sgonzostatic int 371187706Sgonzoar71xx_pci_probe(device_t dev) 372187706Sgonzo{ 373187706Sgonzo 374257338Snwhitehorn return (BUS_PROBE_NOWILDCARD); 375187706Sgonzo} 376187706Sgonzo 377187706Sgonzostatic int 378187706Sgonzoar71xx_pci_attach(device_t dev) 379187706Sgonzo{ 380187706Sgonzo int busno = 0; 381187706Sgonzo int rid = 0; 382187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 383187706Sgonzo 384187706Sgonzo sc->sc_mem_rman.rm_type = RMAN_ARRAY; 385187706Sgonzo sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window"; 386187706Sgonzo if (rman_init(&sc->sc_mem_rman) != 0 || 387187706Sgonzo rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 388187706Sgonzo AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) { 389187706Sgonzo panic("ar71xx_pci_attach: failed to set up I/O rman"); 390187706Sgonzo } 391187706Sgonzo 392187706Sgonzo sc->sc_irq_rman.rm_type = RMAN_ARRAY; 393187706Sgonzo sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs"; 394187706Sgonzo if (rman_init(&sc->sc_irq_rman) != 0 || 395187706Sgonzo rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 396187706Sgonzo AR71XX_PCI_IRQ_END) != 0) 397187706Sgonzo panic("ar71xx_pci_attach: failed to set up IRQ rman"); 398187706Sgonzo 399245112Smonthadar /* 400245112Smonthadar * Check if there is a base slot hint. Otherwise use default value. 401245112Smonthadar */ 402245112Smonthadar if (resource_int_value(device_get_name(dev), 403245112Smonthadar device_get_unit(dev), "baseslot", &sc->sc_baseslot) != 0) { 404245112Smonthadar device_printf(dev, 405245112Smonthadar "%s: missing hint '%s', default to AR71XX_PCI_BASE_SLOT\n", 406245112Smonthadar __func__, "baseslot"); 407245112Smonthadar sc->sc_baseslot = AR71XX_PCI_BASE_SLOT; 408245112Smonthadar } 409187706Sgonzo 410187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); 411187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0); 412187706Sgonzo 413187706Sgonzo /* Hook up our interrupt handler. */ 414187706Sgonzo if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 415187706Sgonzo RF_SHAREABLE | RF_ACTIVE)) == NULL) { 416187706Sgonzo device_printf(dev, "unable to allocate IRQ resource\n"); 417187706Sgonzo return ENXIO; 418187706Sgonzo } 419187706Sgonzo 420187706Sgonzo if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 421191872Sgonzo ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) { 422234366Sadrian device_printf(dev, 423187706Sgonzo "WARNING: unable to register interrupt handler\n"); 424187706Sgonzo return ENXIO; 425187706Sgonzo } 426187706Sgonzo 427187706Sgonzo /* reset PCI core and PCI bus */ 428211478Sadrian ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 429203132Sgonzo DELAY(100000); 430187706Sgonzo 431211478Sadrian ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 432203132Sgonzo DELAY(100000); 433187706Sgonzo 434187706Sgonzo /* Init PCI windows */ 435187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); 436187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR); 437187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR); 438187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR); 439187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR); 440187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); 441187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); 442187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); 443203132Sgonzo DELAY(100000); 444187706Sgonzo 445234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 446187706Sgonzo ar71xx_pci_check_bus_error(); 447234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 448187706Sgonzo 449187706Sgonzo /* Fixup internal PCI bridge */ 450234204Sadrian ar71xx_pci_local_write(dev, PCIR_COMMAND, 451234204Sadrian PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 452187706Sgonzo | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 453234204Sadrian | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 4); 454187706Sgonzo 455230148Sadrian#ifdef AR71XX_ATH_EEPROM 456230148Sadrian /* 457230148Sadrian * Hard-code a check for slot 17 and 18 - these are 458230148Sadrian * the two PCI slots which may have a PCI device that 459230148Sadrian * requires "fixing". 460230148Sadrian */ 461230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 17, 0); 462230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 18, 0); 463230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 464230148Sadrian 465287882Szbb device_add_child(dev, "pci", -1); 466187706Sgonzo return (bus_generic_attach(dev)); 467187706Sgonzo} 468187706Sgonzo 469187706Sgonzostatic int 470234366Sadrianar71xx_pci_read_ivar(device_t dev, device_t child, int which, 471234366Sadrian uintptr_t *result) 472187706Sgonzo{ 473187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 474187706Sgonzo 475187706Sgonzo switch (which) { 476187706Sgonzo case PCIB_IVAR_DOMAIN: 477187706Sgonzo *result = 0; 478187706Sgonzo return (0); 479187706Sgonzo case PCIB_IVAR_BUS: 480187706Sgonzo *result = sc->sc_busno; 481187706Sgonzo return (0); 482187706Sgonzo } 483187706Sgonzo 484187706Sgonzo return (ENOENT); 485187706Sgonzo} 486187706Sgonzo 487187706Sgonzostatic int 488234366Sadrianar71xx_pci_write_ivar(device_t dev, device_t child, int which, 489234366Sadrian uintptr_t result) 490187706Sgonzo{ 491187706Sgonzo struct ar71xx_pci_softc * sc = device_get_softc(dev); 492187706Sgonzo 493187706Sgonzo switch (which) { 494187706Sgonzo case PCIB_IVAR_BUS: 495187706Sgonzo sc->sc_busno = result; 496187706Sgonzo return (0); 497187706Sgonzo } 498187706Sgonzo 499187706Sgonzo return (ENOENT); 500187706Sgonzo} 501187706Sgonzo 502187706Sgonzostatic struct resource * 503187706Sgonzoar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 504187706Sgonzo u_long start, u_long end, u_long count, u_int flags) 505187706Sgonzo{ 506187706Sgonzo 507234366Sadrian struct ar71xx_pci_softc *sc = device_get_softc(bus); 508192161Sgonzo struct resource *rv; 509187706Sgonzo struct rman *rm; 510187706Sgonzo 511187706Sgonzo switch (type) { 512187706Sgonzo case SYS_RES_IRQ: 513187706Sgonzo rm = &sc->sc_irq_rman; 514187706Sgonzo break; 515187706Sgonzo case SYS_RES_MEMORY: 516187706Sgonzo rm = &sc->sc_mem_rman; 517187706Sgonzo break; 518187706Sgonzo default: 519187706Sgonzo return (NULL); 520187706Sgonzo } 521187706Sgonzo 522187706Sgonzo rv = rman_reserve_resource(rm, start, end, count, flags, child); 523187706Sgonzo 524187706Sgonzo if (rv == NULL) 525187706Sgonzo return (NULL); 526187706Sgonzo 527187706Sgonzo rman_set_rid(rv, *rid); 528187706Sgonzo 529187706Sgonzo if (flags & RF_ACTIVE) { 530187706Sgonzo if (bus_activate_resource(child, type, *rid, rv)) { 531187706Sgonzo rman_release_resource(rv); 532187706Sgonzo return (NULL); 533187706Sgonzo } 534234366Sadrian } 535187706Sgonzo return (rv); 536187706Sgonzo} 537187706Sgonzo 538187706Sgonzostatic int 539192161Sgonzoar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid, 540192161Sgonzo struct resource *r) 541192161Sgonzo{ 542192161Sgonzo int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 543192161Sgonzo child, type, rid, r)); 544192161Sgonzo 545192161Sgonzo if (!res) { 546192161Sgonzo switch(type) { 547192161Sgonzo case SYS_RES_MEMORY: 548192161Sgonzo case SYS_RES_IOPORT: 549192161Sgonzo rman_set_bustag(r, ar71xx_bus_space_pcimem); 550192161Sgonzo break; 551192161Sgonzo } 552192161Sgonzo } 553192161Sgonzo return (res); 554192161Sgonzo} 555192161Sgonzo 556192161Sgonzostatic int 557191872Sgonzoar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 558234366Sadrian int flags, driver_filter_t *filt, driver_intr_t *handler, 559234366Sadrian void *arg, void **cookiep) 560191872Sgonzo{ 561191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 562191872Sgonzo struct intr_event *event; 563191872Sgonzo int irq, error; 564191872Sgonzo 565191872Sgonzo irq = rman_get_start(ires); 566191872Sgonzo 567191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 568191872Sgonzo panic("%s: bad irq %d", __func__, irq); 569191872Sgonzo 570191872Sgonzo event = sc->sc_eventstab[irq]; 571191872Sgonzo if (event == NULL) { 572191872Sgonzo error = intr_event_create(&event, (void *)irq, 0, irq, 573192822Sgonzo ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL, 574210900Sgonzo "pci intr%d:", irq); 575191872Sgonzo 576210900Sgonzo if (error == 0) { 577210900Sgonzo sc->sc_eventstab[irq] = event; 578210900Sgonzo sc->sc_intr_counter[irq] = 579210900Sgonzo mips_intrcnt_create(event->ie_name); 580210900Sgonzo } 581210900Sgonzo else 582234366Sadrian return (error); 583191872Sgonzo } 584191872Sgonzo 585191872Sgonzo intr_event_add_handler(event, device_get_nameunit(child), filt, 586191872Sgonzo handler, arg, intr_priority(flags), flags, cookiep); 587210900Sgonzo mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname); 588191872Sgonzo 589192822Sgonzo ar71xx_pci_unmask_irq((void*)irq); 590191872Sgonzo 591191872Sgonzo return (0); 592191872Sgonzo} 593191872Sgonzo 594191872Sgonzostatic int 595191872Sgonzoar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 596187706Sgonzo void *cookie) 597187706Sgonzo{ 598191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 599191872Sgonzo int irq, result; 600187706Sgonzo 601191872Sgonzo irq = rman_get_start(ires); 602191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 603191872Sgonzo panic("%s: bad irq %d", __func__, irq); 604191872Sgonzo 605191872Sgonzo if (sc->sc_eventstab[irq] == NULL) 606191872Sgonzo panic("Trying to teardown unoccupied IRQ"); 607191872Sgonzo 608192822Sgonzo ar71xx_pci_mask_irq((void*)irq); 609191872Sgonzo 610191872Sgonzo result = intr_event_remove_handler(cookie); 611191872Sgonzo if (!result) 612191872Sgonzo sc->sc_eventstab[irq] = NULL; 613191872Sgonzo 614191872Sgonzo return (result); 615187706Sgonzo} 616187706Sgonzo 617187706Sgonzostatic int 618191872Sgonzoar71xx_pci_intr(void *arg) 619191872Sgonzo{ 620191872Sgonzo struct ar71xx_pci_softc *sc = arg; 621191872Sgonzo struct intr_event *event; 622194273Sgonzo uint32_t reg, irq, mask; 623191872Sgonzo 624191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); 625194273Sgonzo mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 626194273Sgonzo /* 627194273Sgonzo * Handle only unmasked interrupts 628194273Sgonzo */ 629194273Sgonzo reg &= mask; 630191872Sgonzo for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) { 631191872Sgonzo if (reg & (1 << irq)) { 632191872Sgonzo event = sc->sc_eventstab[irq]; 633191872Sgonzo if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 634191872Sgonzo /* Ignore timer interrupts */ 635191872Sgonzo if (irq != 0) 636191872Sgonzo printf("Stray IRQ %d\n", irq); 637191872Sgonzo continue; 638191872Sgonzo } 639191872Sgonzo 640285121Sadrian /* Flush DDR FIFO for PCI/PCIe */ 641285121Sadrian ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE); 642221256Sadrian 643191872Sgonzo /* TODO: frame instead of NULL? */ 644191872Sgonzo intr_event_handle(event, NULL); 645210900Sgonzo mips_intrcnt_inc(sc->sc_intr_counter[irq]); 646191872Sgonzo } 647191872Sgonzo } 648191872Sgonzo 649191872Sgonzo return (FILTER_HANDLED); 650191872Sgonzo} 651191872Sgonzo 652191872Sgonzostatic int 653187706Sgonzoar71xx_pci_maxslots(device_t dev) 654187706Sgonzo{ 655187706Sgonzo 656187706Sgonzo return (PCI_SLOTMAX); 657187706Sgonzo} 658187706Sgonzo 659187706Sgonzostatic int 660187706Sgonzoar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin) 661187706Sgonzo{ 662245112Smonthadar struct ar71xx_pci_softc *sc = device_get_softc(pcib); 663245112Smonthadar 664245112Smonthadar if (pci_get_slot(device) < sc->sc_baseslot) 665195474Sgonzo panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT", 666195474Sgonzo __func__, pci_get_slot(device)); 667187706Sgonzo 668245112Smonthadar return (pci_get_slot(device) - sc->sc_baseslot); 669187706Sgonzo} 670187706Sgonzo 671187706Sgonzostatic device_method_t ar71xx_pci_methods[] = { 672187706Sgonzo /* Device interface */ 673187706Sgonzo DEVMETHOD(device_probe, ar71xx_pci_probe), 674187706Sgonzo DEVMETHOD(device_attach, ar71xx_pci_attach), 675187706Sgonzo DEVMETHOD(device_shutdown, bus_generic_shutdown), 676187706Sgonzo DEVMETHOD(device_suspend, bus_generic_suspend), 677187706Sgonzo DEVMETHOD(device_resume, bus_generic_resume), 678187706Sgonzo 679187706Sgonzo /* Bus interface */ 680187706Sgonzo DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar), 681187706Sgonzo DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar), 682187706Sgonzo DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource), 683187706Sgonzo DEVMETHOD(bus_release_resource, bus_generic_release_resource), 684192161Sgonzo DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource), 685187706Sgonzo DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 686191872Sgonzo DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr), 687187706Sgonzo DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr), 688187706Sgonzo 689187706Sgonzo /* pcib interface */ 690187706Sgonzo DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots), 691187706Sgonzo DEVMETHOD(pcib_read_config, ar71xx_pci_read_config), 692187706Sgonzo DEVMETHOD(pcib_write_config, ar71xx_pci_write_config), 693187706Sgonzo DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt), 694187706Sgonzo 695227843Smarius DEVMETHOD_END 696187706Sgonzo}; 697187706Sgonzo 698187706Sgonzostatic driver_t ar71xx_pci_driver = { 699187706Sgonzo "pcib", 700187706Sgonzo ar71xx_pci_methods, 701187706Sgonzo sizeof(struct ar71xx_pci_softc), 702187706Sgonzo}; 703187706Sgonzo 704187706Sgonzostatic devclass_t ar71xx_pci_devclass; 705187706Sgonzo 706187706SgonzoDRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0); 707