ar71xx_pci.c revision 234365
1187706Sgonzo/*- 2187706Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3187706Sgonzo * All rights reserved. 4187706Sgonzo * 5187706Sgonzo * Redistribution and use in source and binary forms, with or without 6187706Sgonzo * modification, are permitted provided that the following conditions 7187706Sgonzo * are met: 8187706Sgonzo * 1. Redistributions of source code must retain the above copyright 9187706Sgonzo * notice unmodified, this list of conditions, and the following 10187706Sgonzo * disclaimer. 11187706Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12187706Sgonzo * notice, this list of conditions and the following disclaimer in the 13187706Sgonzo * documentation and/or other materials provided with the distribution. 14187706Sgonzo * 15187706Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16187706Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17187706Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18187706Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19187706Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20187706Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21187706Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22187706Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23187706Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24187706Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25187706Sgonzo * SUCH DAMAGE. 26187706Sgonzo */ 27187706Sgonzo 28187706Sgonzo#include <sys/cdefs.h> 29187706Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_pci.c 234365 2012-04-17 01:22:59Z adrian $"); 30187706Sgonzo 31230195Sadrian#include "opt_ar71xx.h" 32230195Sadrian 33187706Sgonzo#include <sys/param.h> 34187706Sgonzo#include <sys/systm.h> 35187706Sgonzo 36187706Sgonzo#include <sys/bus.h> 37187706Sgonzo#include <sys/interrupt.h> 38187706Sgonzo#include <sys/malloc.h> 39187706Sgonzo#include <sys/kernel.h> 40187706Sgonzo#include <sys/module.h> 41187706Sgonzo#include <sys/rman.h> 42234365Sadrian#include <sys/lock.h> 43234365Sadrian#include <sys/mutex.h> 44187706Sgonzo 45187706Sgonzo#include <vm/vm.h> 46187706Sgonzo#include <vm/pmap.h> 47187706Sgonzo#include <vm/vm_extern.h> 48187706Sgonzo 49187706Sgonzo#include <machine/bus.h> 50187706Sgonzo#include <machine/cpu.h> 51210900Sgonzo#include <machine/intr_machdep.h> 52187706Sgonzo#include <machine/pmap.h> 53187706Sgonzo 54187706Sgonzo#include <dev/pci/pcivar.h> 55187706Sgonzo#include <dev/pci/pcireg.h> 56187706Sgonzo 57187706Sgonzo#include <dev/pci/pcib_private.h> 58187706Sgonzo#include "pcib_if.h" 59187706Sgonzo 60192161Sgonzo#include <mips/atheros/ar71xxreg.h> 61192161Sgonzo#include <mips/atheros/ar71xx_pci_bus_space.h> 62187706Sgonzo 63211478Sadrian#include <mips/atheros/ar71xx_cpudef.h> 64211478Sadrian 65234217Sadrian#ifdef AR71XX_ATH_EEPROM 66234217Sadrian#include <sys/linker.h> 67234217Sadrian#include <sys/firmware.h> 68234217Sadrian#endif /* AR71XX_ATH_EEPROM */ 69234217Sadrian 70187706Sgonzo#undef AR71XX_PCI_DEBUG 71187706Sgonzo#ifdef AR71XX_PCI_DEBUG 72187706Sgonzo#define dprintf printf 73187706Sgonzo#else 74187706Sgonzo#define dprintf(x, arg...) 75187706Sgonzo#endif 76187706Sgonzo 77234365Sadrianstruct mtx ar71xx_pci_mtx; 78234365SadrianMTX_SYSINIT(ar71xx_pci_mtx, &ar71xx_pci_mtx, "ar71xx PCI space mutex", 79234365Sadrian MTX_SPIN); 80234365Sadrian 81187706Sgonzostruct ar71xx_pci_softc { 82187706Sgonzo device_t sc_dev; 83187706Sgonzo 84187706Sgonzo int sc_busno; 85187706Sgonzo struct rman sc_mem_rman; 86187706Sgonzo struct rman sc_irq_rman; 87187706Sgonzo 88191872Sgonzo struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 89210900Sgonzo mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS]; 90187706Sgonzo struct resource *sc_irq; 91187706Sgonzo void *sc_ih; 92187706Sgonzo}; 93187706Sgonzo 94191872Sgonzostatic int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 95191872Sgonzo driver_filter_t *, driver_intr_t *, void *, void **); 96191872Sgonzostatic int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *, 97191872Sgonzo void *); 98191872Sgonzostatic int ar71xx_pci_intr(void *); 99191872Sgonzo 100192822Sgonzostatic void 101192822Sgonzoar71xx_pci_mask_irq(void *source) 102191872Sgonzo{ 103191872Sgonzo uint32_t reg; 104192822Sgonzo unsigned int irq = (unsigned int)source; 105191872Sgonzo 106234365Sadrian /* XXX is the PCI lock required here? */ 107191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 108194273Sgonzo /* flush */ 109194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 110191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq)); 111191872Sgonzo} 112191872Sgonzo 113192822Sgonzostatic void 114192822Sgonzoar71xx_pci_unmask_irq(void *source) 115191872Sgonzo{ 116191872Sgonzo uint32_t reg; 117192822Sgonzo unsigned int irq = (unsigned int)source; 118191872Sgonzo 119234365Sadrian /* XXX is the PCI lock required here? */ 120191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 121191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); 122194273Sgonzo /* flush */ 123194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 124191872Sgonzo} 125191872Sgonzo 126187706Sgonzo/* 127187706Sgonzo * get bitmask for bytes of interest: 128187706Sgonzo * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte 129187706Sgonzo * from register 7. Bitmask would be: 0111 130187706Sgonzo */ 131187706Sgonzostatic uint32_t 132187706Sgonzoar71xx_get_bytes_to_read(int reg, int bytes) 133187706Sgonzo{ 134187706Sgonzo uint32_t bytes_to_read = 0; 135187706Sgonzo if ((bytes % 4) == 0) 136187706Sgonzo bytes_to_read = 0; 137187706Sgonzo else if ((bytes % 4) == 1) 138187706Sgonzo bytes_to_read = (~(1 << (reg % 4))) & 0xf; 139187706Sgonzo else if ((bytes % 4) == 2) 140187706Sgonzo bytes_to_read = (~(3 << (reg % 4))) & 0xf; 141187706Sgonzo else 142187706Sgonzo panic("%s: wrong combination", __func__); 143187706Sgonzo 144187706Sgonzo return (bytes_to_read); 145187706Sgonzo} 146187706Sgonzo 147187706Sgonzostatic int 148187706Sgonzoar71xx_pci_check_bus_error(void) 149187706Sgonzo{ 150187706Sgonzo uint32_t error, addr, has_errors = 0; 151234365Sadrian 152234365Sadrian mtx_assert(&ar71xx_pci_mtx, MA_OWNED); 153234365Sadrian 154187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; 155187706Sgonzo dprintf("%s: PCI error = %02x\n", __func__, error); 156187706Sgonzo if (error) { 157187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); 158187706Sgonzo 159187706Sgonzo /* Do not report it yet */ 160187706Sgonzo#if 0 161187706Sgonzo printf("PCI bus error %d at addr 0x%08x\n", error, addr); 162187706Sgonzo#endif 163187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_ERROR, error); 164187706Sgonzo has_errors = 1; 165187706Sgonzo } 166187706Sgonzo 167187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; 168187706Sgonzo dprintf("%s: AHB error = %02x\n", __func__, error); 169187706Sgonzo if (error) { 170187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); 171187706Sgonzo /* Do not report it yet */ 172187706Sgonzo#if 0 173187706Sgonzo printf("AHB bus error %d at addr 0x%08x\n", error, addr); 174187706Sgonzo#endif 175187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); 176187706Sgonzo has_errors = 1; 177187706Sgonzo } 178187706Sgonzo 179187706Sgonzo return (has_errors); 180187706Sgonzo} 181187706Sgonzo 182187706Sgonzostatic uint32_t 183187706Sgonzoar71xx_pci_make_addr(int bus, int slot, int func, int reg) 184187706Sgonzo{ 185187706Sgonzo if (bus == 0) { 186187706Sgonzo return ((1 << slot) | (func << 8) | (reg & ~3)); 187187706Sgonzo } else { 188187706Sgonzo return ((bus << 16) | (slot << 11) | (func << 8) 189187706Sgonzo | (reg & ~3) | 1); 190187706Sgonzo } 191187706Sgonzo} 192187706Sgonzo 193187706Sgonzostatic int 194187706Sgonzoar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes, 195187706Sgonzo uint32_t cmd) 196187706Sgonzo{ 197187706Sgonzo uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3)); 198187706Sgonzo cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4); 199234365Sadrian 200234365Sadrian mtx_assert(&ar71xx_pci_mtx, MA_OWNED); 201234365Sadrian 202187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); 203187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); 204187706Sgonzo 205187706Sgonzo dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 206187706Sgonzo bus, slot, func, reg, bytes, addr, cmd); 207187706Sgonzo 208187706Sgonzo return ar71xx_pci_check_bus_error(); 209187706Sgonzo} 210187706Sgonzo 211187706Sgonzostatic uint32_t 212194059Sgonzoar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 213194059Sgonzo u_int reg, int bytes) 214187706Sgonzo{ 215187706Sgonzo uint32_t data; 216234205Sadrian uint32_t shift, mask; 217187706Sgonzo 218187706Sgonzo /* register access is 32-bit aligned */ 219187706Sgonzo shift = (reg & 3) * 8; 220234306Sadrian 221234306Sadrian /* Create a mask based on the width, post-shift */ 222234306Sadrian if (bytes == 2) 223234306Sadrian mask = 0xffff; 224234306Sadrian else if (bytes == 1) 225234306Sadrian mask = 0xff; 226187706Sgonzo else 227187706Sgonzo mask = 0xffffffff; 228187706Sgonzo 229187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 230187706Sgonzo func, reg, bytes); 231187706Sgonzo 232234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 233234204Sadrian if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 234234204Sadrian PCI_CONF_CMD_READ) == 0) 235234204Sadrian data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); 236234204Sadrian else 237234204Sadrian data = -1; 238234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 239187706Sgonzo 240187706Sgonzo /* get request bytes from 32-bit word */ 241187706Sgonzo data = (data >> shift) & mask; 242187706Sgonzo 243187706Sgonzo dprintf("%s: read 0x%x\n", __func__, data); 244187706Sgonzo 245187706Sgonzo return (data); 246187706Sgonzo} 247187706Sgonzo 248187706Sgonzostatic void 249234204Sadrianar71xx_pci_local_write(device_t dev, uint32_t reg, uint32_t data, int bytes) 250187706Sgonzo{ 251187706Sgonzo uint32_t cmd; 252187706Sgonzo 253234204Sadrian dprintf("%s: local write reg %d(%d)\n", __func__, reg, bytes); 254234204Sadrian 255234204Sadrian data = data << (8*(reg % 4)); 256234204Sadrian 257234204Sadrian cmd = PCI_LCONF_CMD_WRITE | (reg & ~3); 258234204Sadrian cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 20); 259234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 260234204Sadrian ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 261234204Sadrian ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); 262234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 263234204Sadrian} 264234204Sadrian 265234204Sadrianstatic void 266234204Sadrianar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 267234204Sadrian u_int reg, uint32_t data, int bytes) 268234204Sadrian{ 269234204Sadrian 270234204Sadrian dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 271187706Sgonzo func, reg, bytes); 272187706Sgonzo 273187706Sgonzo data = data << (8*(reg % 4)); 274187706Sgonzo 275234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 276234204Sadrian if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 277234204Sadrian PCI_CONF_CMD_WRITE) == 0) 278234204Sadrian ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); 279234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 280187706Sgonzo} 281187706Sgonzo 282230148Sadrian#ifdef AR71XX_ATH_EEPROM 283230148Sadrian/* 284230148Sadrian * Some embedded boards (eg AP94) have the MAC attached via PCI but they 285230148Sadrian * don't have the MAC-attached EEPROM. The register initialisation 286230148Sadrian * values and calibration data are stored in the on-board flash. 287230148Sadrian * This routine initialises the NIC via the EEPROM register contents 288230148Sadrian * before the probe/attach routines get a go at things. 289230148Sadrian */ 290230148Sadrianstatic void 291230148Sadrianar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func, 292230148Sadrian long flash_addr) 293230148Sadrian{ 294230148Sadrian uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr); 295230148Sadrian uint32_t reg, val, bar0; 296230148Sadrian 297234217Sadrian if (bootverbose) 298234217Sadrian device_printf(dev, "%s: flash_addr=%lx, cal_data=%p\n", 299234217Sadrian __func__, flash_addr, cal_data); 300230148Sadrian 301230148Sadrian /* XXX check 0xa55a */ 302230148Sadrian /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */ 303230148Sadrian bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4); 304230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), 305230148Sadrian AR71XX_PCI_MEM_BASE, 4); 306230148Sadrian 307230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 308230148Sadrian val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 309230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 310230148Sadrian 311230148Sadrian cal_data += 3; 312230148Sadrian while (*cal_data != 0xffff) { 313230148Sadrian reg = *cal_data++; 314230148Sadrian val = *cal_data++; 315230148Sadrian val |= (*cal_data++) << 16; 316234217Sadrian if (bootverbose) 317234217Sadrian printf(" reg: %x, val=%x\n", reg, val); 318230148Sadrian 319230148Sadrian /* Write eeprom fixup data to device memory */ 320230148Sadrian ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val); 321230148Sadrian DELAY(100); 322230148Sadrian } 323230148Sadrian 324230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 325230148Sadrian val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 326230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 327230148Sadrian 328230148Sadrian /* Write the saved bar(0) address */ 329230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4); 330230148Sadrian} 331230148Sadrian 332234217Sadrian/* 333234217Sadrian * Take a copy of the EEPROM contents and squirrel it away in a firmware. 334234217Sadrian * The SPI flash will eventually cease to be memory-mapped, so we need 335234217Sadrian * to take a copy of this before the SPI driver initialises. 336234217Sadrian */ 337230148Sadrianstatic void 338234217Sadrianar71xx_pci_slot_create_eeprom_firmware(device_t dev, u_int bus, u_int slot, 339234217Sadrian u_int func, long int flash_addr) 340234217Sadrian{ 341234217Sadrian char buf[64]; 342234217Sadrian uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr); 343234217Sadrian void *eeprom = NULL; 344234217Sadrian const struct firmware *fw = NULL; 345234217Sadrian int len; 346234217Sadrian 347234217Sadrian snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_size", 348234217Sadrian bus, slot, func); 349234217Sadrian 350234217Sadrian if (resource_int_value(device_get_name(dev), device_get_unit(dev), 351234217Sadrian buf, &len) != 0) { 352234217Sadrian device_printf(dev, "%s: missing hint '%s', aborting EEPROM\n", 353234217Sadrian __func__, buf); 354234217Sadrian return; 355234217Sadrian } 356234217Sadrian 357234217Sadrian device_printf(dev, "EEPROM firmware: 0x%lx @ %d bytes\n", 358234217Sadrian flash_addr, len); 359234217Sadrian 360234217Sadrian eeprom = malloc(len, M_DEVBUF, M_WAITOK | M_ZERO); 361234217Sadrian if (! eeprom) { 362234217Sadrian device_printf(dev, 363234217Sadrian "%s: malloc failed for '%s', aborting EEPROM\n", 364234217Sadrian __func__, buf); 365234217Sadrian return; 366234217Sadrian } 367234217Sadrian 368234217Sadrian memcpy(eeprom, cal_data, len); 369234217Sadrian 370234217Sadrian /* 371234217Sadrian * Generate a flash EEPROM 'firmware' from the given memory 372234217Sadrian * region. Since the SPI controller will eventually 373234217Sadrian * go into port-IO mode instead of memory-mapped IO 374234217Sadrian * mode, a copy of the EEPROM contents is required. 375234217Sadrian */ 376234217Sadrian snprintf(buf, sizeof(buf), "%s.%d.bus.%d.%d.%d.eeprom_firmware", 377234217Sadrian device_get_name(dev), device_get_unit(dev), bus, slot, func); 378234217Sadrian fw = firmware_register(buf, eeprom, len, 1, NULL); 379234217Sadrian if (fw == NULL) { 380234217Sadrian device_printf(dev, "%s: firmware_register (%s) failed\n", 381234217Sadrian __func__, buf); 382234217Sadrian free(eeprom, M_DEVBUF); 383234217Sadrian return; 384234217Sadrian } 385234217Sadrian device_printf(dev, "device EEPROM '%s' registered\n", buf); 386234217Sadrian} 387234217Sadrian 388234217Sadrianstatic void 389230148Sadrianar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func) 390230148Sadrian{ 391230148Sadrian long int flash_addr; 392230148Sadrian char buf[32]; 393230148Sadrian 394230148Sadrian /* 395230148Sadrian * Check whether the given slot has a hint to poke. 396230148Sadrian */ 397234217Sadrian if (bootverbose) 398234217Sadrian device_printf(dev, "%s: checking dev %s, %d/%d/%d\n", 399230148Sadrian __func__, device_get_nameunit(dev), bus, slot, func); 400230148Sadrian snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr", 401230148Sadrian bus, slot, func); 402230148Sadrian 403230148Sadrian if (resource_long_value(device_get_name(dev), device_get_unit(dev), 404230148Sadrian buf, &flash_addr) == 0) { 405234217Sadrian device_printf(dev, "found EEPROM at 0x%lx on %d.%d.%d\n", 406234217Sadrian flash_addr, bus, slot, func); 407230148Sadrian ar71xx_pci_fixup(dev, bus, slot, func, flash_addr); 408234217Sadrian ar71xx_pci_slot_create_eeprom_firmware(dev, bus, slot, func, 409234217Sadrian flash_addr); 410230148Sadrian } 411230148Sadrian} 412230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 413230148Sadrian 414187706Sgonzostatic int 415187706Sgonzoar71xx_pci_probe(device_t dev) 416187706Sgonzo{ 417187706Sgonzo 418187706Sgonzo return (0); 419187706Sgonzo} 420187706Sgonzo 421187706Sgonzostatic int 422187706Sgonzoar71xx_pci_attach(device_t dev) 423187706Sgonzo{ 424187706Sgonzo int busno = 0; 425187706Sgonzo int rid = 0; 426187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 427187706Sgonzo 428187706Sgonzo sc->sc_mem_rman.rm_type = RMAN_ARRAY; 429187706Sgonzo sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window"; 430187706Sgonzo if (rman_init(&sc->sc_mem_rman) != 0 || 431187706Sgonzo rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 432187706Sgonzo AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) { 433187706Sgonzo panic("ar71xx_pci_attach: failed to set up I/O rman"); 434187706Sgonzo } 435187706Sgonzo 436187706Sgonzo sc->sc_irq_rman.rm_type = RMAN_ARRAY; 437187706Sgonzo sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs"; 438187706Sgonzo if (rman_init(&sc->sc_irq_rman) != 0 || 439187706Sgonzo rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 440187706Sgonzo AR71XX_PCI_IRQ_END) != 0) 441187706Sgonzo panic("ar71xx_pci_attach: failed to set up IRQ rman"); 442187706Sgonzo 443187706Sgonzo 444187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); 445187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0); 446187706Sgonzo 447187706Sgonzo /* Hook up our interrupt handler. */ 448187706Sgonzo if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 449187706Sgonzo RF_SHAREABLE | RF_ACTIVE)) == NULL) { 450187706Sgonzo device_printf(dev, "unable to allocate IRQ resource\n"); 451187706Sgonzo return ENXIO; 452187706Sgonzo } 453187706Sgonzo 454187706Sgonzo if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 455191872Sgonzo ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) { 456187706Sgonzo device_printf(dev, 457187706Sgonzo "WARNING: unable to register interrupt handler\n"); 458187706Sgonzo return ENXIO; 459187706Sgonzo } 460187706Sgonzo 461187706Sgonzo /* reset PCI core and PCI bus */ 462211478Sadrian ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 463203132Sgonzo DELAY(100000); 464187706Sgonzo 465211478Sadrian ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 466203132Sgonzo DELAY(100000); 467187706Sgonzo 468187706Sgonzo /* Init PCI windows */ 469187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); 470187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR); 471187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR); 472187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR); 473187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR); 474187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); 475187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); 476187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); 477203132Sgonzo DELAY(100000); 478187706Sgonzo 479234365Sadrian mtx_lock_spin(&ar71xx_pci_mtx); 480187706Sgonzo ar71xx_pci_check_bus_error(); 481234365Sadrian mtx_unlock_spin(&ar71xx_pci_mtx); 482187706Sgonzo 483187706Sgonzo /* Fixup internal PCI bridge */ 484234204Sadrian ar71xx_pci_local_write(dev, PCIR_COMMAND, 485234204Sadrian PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 486187706Sgonzo | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 487234204Sadrian | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 4); 488187706Sgonzo 489230148Sadrian#ifdef AR71XX_ATH_EEPROM 490230148Sadrian /* 491230148Sadrian * Hard-code a check for slot 17 and 18 - these are 492230148Sadrian * the two PCI slots which may have a PCI device that 493230148Sadrian * requires "fixing". 494230148Sadrian */ 495230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 17, 0); 496230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 18, 0); 497230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 498230148Sadrian 499187706Sgonzo device_add_child(dev, "pci", busno); 500187706Sgonzo return (bus_generic_attach(dev)); 501187706Sgonzo} 502187706Sgonzo 503187706Sgonzostatic int 504187706Sgonzoar71xx_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 505187706Sgonzo{ 506187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 507187706Sgonzo 508187706Sgonzo switch (which) { 509187706Sgonzo case PCIB_IVAR_DOMAIN: 510187706Sgonzo *result = 0; 511187706Sgonzo return (0); 512187706Sgonzo case PCIB_IVAR_BUS: 513187706Sgonzo *result = sc->sc_busno; 514187706Sgonzo return (0); 515187706Sgonzo } 516187706Sgonzo 517187706Sgonzo return (ENOENT); 518187706Sgonzo} 519187706Sgonzo 520187706Sgonzostatic int 521187706Sgonzoar71xx_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 522187706Sgonzo{ 523187706Sgonzo struct ar71xx_pci_softc * sc = device_get_softc(dev); 524187706Sgonzo 525187706Sgonzo switch (which) { 526187706Sgonzo case PCIB_IVAR_BUS: 527187706Sgonzo sc->sc_busno = result; 528187706Sgonzo return (0); 529187706Sgonzo } 530187706Sgonzo 531187706Sgonzo return (ENOENT); 532187706Sgonzo} 533187706Sgonzo 534187706Sgonzostatic struct resource * 535187706Sgonzoar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 536187706Sgonzo u_long start, u_long end, u_long count, u_int flags) 537187706Sgonzo{ 538187706Sgonzo 539187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 540192161Sgonzo struct resource *rv; 541187706Sgonzo struct rman *rm; 542187706Sgonzo 543187706Sgonzo switch (type) { 544187706Sgonzo case SYS_RES_IRQ: 545187706Sgonzo rm = &sc->sc_irq_rman; 546187706Sgonzo break; 547187706Sgonzo case SYS_RES_MEMORY: 548187706Sgonzo rm = &sc->sc_mem_rman; 549187706Sgonzo break; 550187706Sgonzo default: 551187706Sgonzo return (NULL); 552187706Sgonzo } 553187706Sgonzo 554187706Sgonzo rv = rman_reserve_resource(rm, start, end, count, flags, child); 555187706Sgonzo 556187706Sgonzo if (rv == NULL) 557187706Sgonzo return (NULL); 558187706Sgonzo 559187706Sgonzo rman_set_rid(rv, *rid); 560187706Sgonzo 561187706Sgonzo if (flags & RF_ACTIVE) { 562187706Sgonzo if (bus_activate_resource(child, type, *rid, rv)) { 563187706Sgonzo rman_release_resource(rv); 564187706Sgonzo return (NULL); 565187706Sgonzo } 566187706Sgonzo } 567187706Sgonzo 568192161Sgonzo 569187706Sgonzo return (rv); 570187706Sgonzo} 571187706Sgonzo 572192161Sgonzo 573187706Sgonzostatic int 574192161Sgonzoar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid, 575192161Sgonzo struct resource *r) 576192161Sgonzo{ 577192161Sgonzo int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 578192161Sgonzo child, type, rid, r)); 579192161Sgonzo 580192161Sgonzo if (!res) { 581192161Sgonzo switch(type) { 582192161Sgonzo case SYS_RES_MEMORY: 583192161Sgonzo case SYS_RES_IOPORT: 584192161Sgonzo rman_set_bustag(r, ar71xx_bus_space_pcimem); 585192161Sgonzo break; 586192161Sgonzo } 587192161Sgonzo } 588192161Sgonzo 589192161Sgonzo return (res); 590192161Sgonzo} 591192161Sgonzo 592192161Sgonzo 593192161Sgonzo 594192161Sgonzostatic int 595191872Sgonzoar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 596191872Sgonzo int flags, driver_filter_t *filt, driver_intr_t *handler, 597191872Sgonzo void *arg, void **cookiep) 598191872Sgonzo{ 599191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 600191872Sgonzo struct intr_event *event; 601191872Sgonzo int irq, error; 602191872Sgonzo 603191872Sgonzo irq = rman_get_start(ires); 604191872Sgonzo 605191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 606191872Sgonzo panic("%s: bad irq %d", __func__, irq); 607191872Sgonzo 608191872Sgonzo event = sc->sc_eventstab[irq]; 609191872Sgonzo if (event == NULL) { 610191872Sgonzo error = intr_event_create(&event, (void *)irq, 0, irq, 611192822Sgonzo ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL, 612210900Sgonzo "pci intr%d:", irq); 613191872Sgonzo 614210900Sgonzo if (error == 0) { 615210900Sgonzo sc->sc_eventstab[irq] = event; 616210900Sgonzo sc->sc_intr_counter[irq] = 617210900Sgonzo mips_intrcnt_create(event->ie_name); 618210900Sgonzo } 619210900Sgonzo else 620210900Sgonzo return error; 621191872Sgonzo } 622191872Sgonzo 623191872Sgonzo intr_event_add_handler(event, device_get_nameunit(child), filt, 624191872Sgonzo handler, arg, intr_priority(flags), flags, cookiep); 625210900Sgonzo mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname); 626191872Sgonzo 627192822Sgonzo ar71xx_pci_unmask_irq((void*)irq); 628191872Sgonzo 629191872Sgonzo return (0); 630191872Sgonzo} 631191872Sgonzo 632191872Sgonzostatic int 633191872Sgonzoar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 634187706Sgonzo void *cookie) 635187706Sgonzo{ 636191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 637191872Sgonzo int irq, result; 638187706Sgonzo 639191872Sgonzo irq = rman_get_start(ires); 640191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 641191872Sgonzo panic("%s: bad irq %d", __func__, irq); 642191872Sgonzo 643191872Sgonzo if (sc->sc_eventstab[irq] == NULL) 644191872Sgonzo panic("Trying to teardown unoccupied IRQ"); 645191872Sgonzo 646192822Sgonzo ar71xx_pci_mask_irq((void*)irq); 647191872Sgonzo 648191872Sgonzo result = intr_event_remove_handler(cookie); 649191872Sgonzo if (!result) 650191872Sgonzo sc->sc_eventstab[irq] = NULL; 651191872Sgonzo 652191872Sgonzo return (result); 653187706Sgonzo} 654187706Sgonzo 655187706Sgonzostatic int 656191872Sgonzoar71xx_pci_intr(void *arg) 657191872Sgonzo{ 658191872Sgonzo struct ar71xx_pci_softc *sc = arg; 659191872Sgonzo struct intr_event *event; 660194273Sgonzo uint32_t reg, irq, mask; 661191872Sgonzo 662191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); 663194273Sgonzo mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 664194273Sgonzo /* 665194273Sgonzo * Handle only unmasked interrupts 666194273Sgonzo */ 667194273Sgonzo reg &= mask; 668191872Sgonzo for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) { 669191872Sgonzo if (reg & (1 << irq)) { 670191872Sgonzo event = sc->sc_eventstab[irq]; 671191872Sgonzo if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 672191872Sgonzo /* Ignore timer interrupts */ 673191872Sgonzo if (irq != 0) 674191872Sgonzo printf("Stray IRQ %d\n", irq); 675191872Sgonzo continue; 676191872Sgonzo } 677191872Sgonzo 678221256Sadrian /* Flush DDR FIFO for IP2 */ 679221256Sadrian ar71xx_device_ddr_flush_ip2(); 680221256Sadrian 681191872Sgonzo /* TODO: frame instead of NULL? */ 682191872Sgonzo intr_event_handle(event, NULL); 683210900Sgonzo mips_intrcnt_inc(sc->sc_intr_counter[irq]); 684191872Sgonzo } 685191872Sgonzo } 686191872Sgonzo 687191872Sgonzo return (FILTER_HANDLED); 688191872Sgonzo} 689191872Sgonzo 690191872Sgonzostatic int 691187706Sgonzoar71xx_pci_maxslots(device_t dev) 692187706Sgonzo{ 693187706Sgonzo 694187706Sgonzo return (PCI_SLOTMAX); 695187706Sgonzo} 696187706Sgonzo 697187706Sgonzostatic int 698187706Sgonzoar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin) 699187706Sgonzo{ 700195474Sgonzo if (pci_get_slot(device) < AR71XX_PCI_BASE_SLOT) 701195474Sgonzo panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT", 702195474Sgonzo __func__, pci_get_slot(device)); 703187706Sgonzo 704195474Sgonzo return (pci_get_slot(device) - AR71XX_PCI_BASE_SLOT); 705187706Sgonzo} 706187706Sgonzo 707187706Sgonzostatic device_method_t ar71xx_pci_methods[] = { 708187706Sgonzo /* Device interface */ 709187706Sgonzo DEVMETHOD(device_probe, ar71xx_pci_probe), 710187706Sgonzo DEVMETHOD(device_attach, ar71xx_pci_attach), 711187706Sgonzo DEVMETHOD(device_shutdown, bus_generic_shutdown), 712187706Sgonzo DEVMETHOD(device_suspend, bus_generic_suspend), 713187706Sgonzo DEVMETHOD(device_resume, bus_generic_resume), 714187706Sgonzo 715187706Sgonzo /* Bus interface */ 716187706Sgonzo DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar), 717187706Sgonzo DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar), 718187706Sgonzo DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource), 719187706Sgonzo DEVMETHOD(bus_release_resource, bus_generic_release_resource), 720192161Sgonzo DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource), 721187706Sgonzo DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 722191872Sgonzo DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr), 723187706Sgonzo DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr), 724187706Sgonzo 725187706Sgonzo /* pcib interface */ 726187706Sgonzo DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots), 727187706Sgonzo DEVMETHOD(pcib_read_config, ar71xx_pci_read_config), 728187706Sgonzo DEVMETHOD(pcib_write_config, ar71xx_pci_write_config), 729187706Sgonzo DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt), 730187706Sgonzo 731227843Smarius DEVMETHOD_END 732187706Sgonzo}; 733187706Sgonzo 734187706Sgonzostatic driver_t ar71xx_pci_driver = { 735187706Sgonzo "pcib", 736187706Sgonzo ar71xx_pci_methods, 737187706Sgonzo sizeof(struct ar71xx_pci_softc), 738187706Sgonzo}; 739187706Sgonzo 740187706Sgonzostatic devclass_t ar71xx_pci_devclass; 741187706Sgonzo 742187706SgonzoDRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0); 743