ar71xx_pci.c revision 230148
1187706Sgonzo/*- 2187706Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3187706Sgonzo * All rights reserved. 4187706Sgonzo * 5187706Sgonzo * Redistribution and use in source and binary forms, with or without 6187706Sgonzo * modification, are permitted provided that the following conditions 7187706Sgonzo * are met: 8187706Sgonzo * 1. Redistributions of source code must retain the above copyright 9187706Sgonzo * notice unmodified, this list of conditions, and the following 10187706Sgonzo * disclaimer. 11187706Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12187706Sgonzo * notice, this list of conditions and the following disclaimer in the 13187706Sgonzo * documentation and/or other materials provided with the distribution. 14187706Sgonzo * 15187706Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16187706Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17187706Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18187706Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19187706Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20187706Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21187706Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22187706Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23187706Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24187706Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25187706Sgonzo * SUCH DAMAGE. 26187706Sgonzo */ 27187706Sgonzo 28187706Sgonzo#include <sys/cdefs.h> 29187706Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_pci.c 230148 2012-01-15 19:29:33Z adrian $"); 30187706Sgonzo 31187706Sgonzo#include <sys/param.h> 32187706Sgonzo#include <sys/systm.h> 33187706Sgonzo 34187706Sgonzo#include <sys/bus.h> 35187706Sgonzo#include <sys/interrupt.h> 36187706Sgonzo#include <sys/malloc.h> 37187706Sgonzo#include <sys/kernel.h> 38187706Sgonzo#include <sys/module.h> 39187706Sgonzo#include <sys/rman.h> 40187706Sgonzo 41187706Sgonzo#include <vm/vm.h> 42187706Sgonzo#include <vm/pmap.h> 43187706Sgonzo#include <vm/vm_extern.h> 44187706Sgonzo 45187706Sgonzo#include <machine/bus.h> 46187706Sgonzo#include <machine/cpu.h> 47210900Sgonzo#include <machine/intr_machdep.h> 48187706Sgonzo#include <machine/pmap.h> 49187706Sgonzo 50187706Sgonzo#include <dev/pci/pcivar.h> 51187706Sgonzo#include <dev/pci/pcireg.h> 52187706Sgonzo 53187706Sgonzo#include <dev/pci/pcib_private.h> 54187706Sgonzo#include "pcib_if.h" 55187706Sgonzo 56192161Sgonzo#include <mips/atheros/ar71xxreg.h> 57192161Sgonzo#include <mips/atheros/ar71xx_pci_bus_space.h> 58187706Sgonzo 59211478Sadrian#include <mips/atheros/ar71xx_cpudef.h> 60211478Sadrian 61187706Sgonzo#undef AR71XX_PCI_DEBUG 62187706Sgonzo#ifdef AR71XX_PCI_DEBUG 63187706Sgonzo#define dprintf printf 64187706Sgonzo#else 65187706Sgonzo#define dprintf(x, arg...) 66187706Sgonzo#endif 67187706Sgonzo 68187706Sgonzostruct ar71xx_pci_softc { 69187706Sgonzo device_t sc_dev; 70187706Sgonzo 71187706Sgonzo int sc_busno; 72187706Sgonzo struct rman sc_mem_rman; 73187706Sgonzo struct rman sc_irq_rman; 74187706Sgonzo 75191872Sgonzo struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 76210900Sgonzo mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS]; 77187706Sgonzo struct resource *sc_irq; 78187706Sgonzo void *sc_ih; 79187706Sgonzo}; 80187706Sgonzo 81191872Sgonzostatic int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 82191872Sgonzo driver_filter_t *, driver_intr_t *, void *, void **); 83191872Sgonzostatic int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *, 84191872Sgonzo void *); 85191872Sgonzostatic int ar71xx_pci_intr(void *); 86191872Sgonzo 87192822Sgonzostatic void 88192822Sgonzoar71xx_pci_mask_irq(void *source) 89191872Sgonzo{ 90191872Sgonzo uint32_t reg; 91192822Sgonzo unsigned int irq = (unsigned int)source; 92191872Sgonzo 93191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 94194273Sgonzo /* flush */ 95194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 96191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq)); 97191872Sgonzo} 98191872Sgonzo 99192822Sgonzostatic void 100192822Sgonzoar71xx_pci_unmask_irq(void *source) 101191872Sgonzo{ 102191872Sgonzo uint32_t reg; 103192822Sgonzo unsigned int irq = (unsigned int)source; 104191872Sgonzo 105191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 106191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); 107194273Sgonzo /* flush */ 108194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 109191872Sgonzo} 110191872Sgonzo 111187706Sgonzo/* 112187706Sgonzo * get bitmask for bytes of interest: 113187706Sgonzo * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte 114187706Sgonzo * from register 7. Bitmask would be: 0111 115187706Sgonzo */ 116187706Sgonzostatic uint32_t 117187706Sgonzoar71xx_get_bytes_to_read(int reg, int bytes) 118187706Sgonzo{ 119187706Sgonzo uint32_t bytes_to_read = 0; 120187706Sgonzo if ((bytes % 4) == 0) 121187706Sgonzo bytes_to_read = 0; 122187706Sgonzo else if ((bytes % 4) == 1) 123187706Sgonzo bytes_to_read = (~(1 << (reg % 4))) & 0xf; 124187706Sgonzo else if ((bytes % 4) == 2) 125187706Sgonzo bytes_to_read = (~(3 << (reg % 4))) & 0xf; 126187706Sgonzo else 127187706Sgonzo panic("%s: wrong combination", __func__); 128187706Sgonzo 129187706Sgonzo return (bytes_to_read); 130187706Sgonzo} 131187706Sgonzo 132187706Sgonzostatic int 133187706Sgonzoar71xx_pci_check_bus_error(void) 134187706Sgonzo{ 135187706Sgonzo uint32_t error, addr, has_errors = 0; 136187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; 137187706Sgonzo dprintf("%s: PCI error = %02x\n", __func__, error); 138187706Sgonzo if (error) { 139187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); 140187706Sgonzo 141187706Sgonzo /* Do not report it yet */ 142187706Sgonzo#if 0 143187706Sgonzo printf("PCI bus error %d at addr 0x%08x\n", error, addr); 144187706Sgonzo#endif 145187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_ERROR, error); 146187706Sgonzo has_errors = 1; 147187706Sgonzo } 148187706Sgonzo 149187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; 150187706Sgonzo dprintf("%s: AHB error = %02x\n", __func__, error); 151187706Sgonzo if (error) { 152187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); 153187706Sgonzo /* Do not report it yet */ 154187706Sgonzo#if 0 155187706Sgonzo printf("AHB bus error %d at addr 0x%08x\n", error, addr); 156187706Sgonzo#endif 157187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); 158187706Sgonzo has_errors = 1; 159187706Sgonzo } 160187706Sgonzo 161187706Sgonzo return (has_errors); 162187706Sgonzo} 163187706Sgonzo 164187706Sgonzostatic uint32_t 165187706Sgonzoar71xx_pci_make_addr(int bus, int slot, int func, int reg) 166187706Sgonzo{ 167187706Sgonzo if (bus == 0) { 168187706Sgonzo return ((1 << slot) | (func << 8) | (reg & ~3)); 169187706Sgonzo } else { 170187706Sgonzo return ((bus << 16) | (slot << 11) | (func << 8) 171187706Sgonzo | (reg & ~3) | 1); 172187706Sgonzo } 173187706Sgonzo} 174187706Sgonzo 175187706Sgonzostatic int 176187706Sgonzoar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes, 177187706Sgonzo uint32_t cmd) 178187706Sgonzo{ 179187706Sgonzo uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3)); 180187706Sgonzo cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4); 181187706Sgonzo 182187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); 183187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); 184187706Sgonzo 185187706Sgonzo dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 186187706Sgonzo bus, slot, func, reg, bytes, addr, cmd); 187187706Sgonzo 188187706Sgonzo return ar71xx_pci_check_bus_error(); 189187706Sgonzo} 190187706Sgonzo 191187706Sgonzostatic uint32_t 192194059Sgonzoar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 193194059Sgonzo u_int reg, int bytes) 194187706Sgonzo{ 195187706Sgonzo uint32_t data; 196187706Sgonzo uint32_t cmd, shift, mask; 197187706Sgonzo 198187706Sgonzo /* register access is 32-bit aligned */ 199187706Sgonzo shift = (reg & 3) * 8; 200187706Sgonzo if (shift) 201187706Sgonzo mask = (1 << shift) - 1; 202187706Sgonzo else 203187706Sgonzo mask = 0xffffffff; 204187706Sgonzo 205187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 206187706Sgonzo func, reg, bytes); 207187706Sgonzo 208187706Sgonzo if ((bus == 0) && (slot == 0) && (func == 0)) { 209187706Sgonzo cmd = PCI_LCONF_CMD_READ | (reg & ~3); 210187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 211187706Sgonzo data = ATH_READ_REG(AR71XX_PCI_LCONF_READ_DATA); 212187706Sgonzo } else { 213187706Sgonzo if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 214187706Sgonzo PCI_CONF_CMD_READ) == 0) 215187706Sgonzo data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); 216187706Sgonzo else 217187706Sgonzo data = -1; 218187706Sgonzo } 219187706Sgonzo 220187706Sgonzo /* get request bytes from 32-bit word */ 221187706Sgonzo data = (data >> shift) & mask; 222187706Sgonzo 223187706Sgonzo dprintf("%s: read 0x%x\n", __func__, data); 224187706Sgonzo 225187706Sgonzo return (data); 226187706Sgonzo} 227187706Sgonzo 228187706Sgonzostatic void 229194059Sgonzoar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 230194059Sgonzo u_int reg, uint32_t data, int bytes) 231187706Sgonzo{ 232187706Sgonzo uint32_t cmd; 233187706Sgonzo 234187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 235187706Sgonzo func, reg, bytes); 236187706Sgonzo 237187706Sgonzo data = data << (8*(reg % 4)); 238187706Sgonzo 239187706Sgonzo if ((bus == 0) && (slot == 0) && (func == 0)) { 240187706Sgonzo cmd = PCI_LCONF_CMD_WRITE | (reg & ~3); 241187706Sgonzo cmd |= ar71xx_get_bytes_to_read(reg, bytes) << 20; 242187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 243187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); 244187706Sgonzo } else { 245187706Sgonzo if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 246187706Sgonzo PCI_CONF_CMD_WRITE) == 0) 247187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); 248187706Sgonzo } 249187706Sgonzo} 250187706Sgonzo 251230148Sadrian#ifdef AR71XX_ATH_EEPROM 252230148Sadrian/* 253230148Sadrian * Some embedded boards (eg AP94) have the MAC attached via PCI but they 254230148Sadrian * don't have the MAC-attached EEPROM. The register initialisation 255230148Sadrian * values and calibration data are stored in the on-board flash. 256230148Sadrian * This routine initialises the NIC via the EEPROM register contents 257230148Sadrian * before the probe/attach routines get a go at things. 258230148Sadrian */ 259230148Sadrianstatic void 260230148Sadrianar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func, 261230148Sadrian long flash_addr) 262230148Sadrian{ 263230148Sadrian uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr); 264230148Sadrian uint32_t reg, val, bar0; 265230148Sadrian 266230148Sadrian printf("%s: flash_addr=%lx, cal_data=%p\n", 267230148Sadrian __func__, flash_addr, cal_data); 268230148Sadrian 269230148Sadrian /* XXX check 0xa55a */ 270230148Sadrian /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */ 271230148Sadrian bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4); 272230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), 273230148Sadrian AR71XX_PCI_MEM_BASE, 4); 274230148Sadrian 275230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 276230148Sadrian val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 277230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 278230148Sadrian 279230148Sadrian cal_data += 3; 280230148Sadrian while (*cal_data != 0xffff) { 281230148Sadrian reg = *cal_data++; 282230148Sadrian val = *cal_data++; 283230148Sadrian val |= (*cal_data++) << 16; 284230148Sadrian printf(" reg: %x, val=%x\n", reg, val); 285230148Sadrian 286230148Sadrian /* Write eeprom fixup data to device memory */ 287230148Sadrian ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val); 288230148Sadrian DELAY(100); 289230148Sadrian } 290230148Sadrian 291230148Sadrian val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2); 292230148Sadrian val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 293230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 294230148Sadrian 295230148Sadrian /* Write the saved bar(0) address */ 296230148Sadrian ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4); 297230148Sadrian} 298230148Sadrian 299230148Sadrianstatic void 300230148Sadrianar71xx_pci_slot_fixup(device_t dev, u_int bus, u_int slot, u_int func) 301230148Sadrian{ 302230148Sadrian long int flash_addr; 303230148Sadrian char buf[32]; 304230148Sadrian 305230148Sadrian /* 306230148Sadrian * Check whether the given slot has a hint to poke. 307230148Sadrian */ 308230148Sadrian printf("%s: checking dev %s, %d/%d/%d\n", 309230148Sadrian __func__, device_get_nameunit(dev), bus, slot, func); 310230148Sadrian snprintf(buf, sizeof(buf), "bus.%d.%d.%d.ath_fixup_addr", 311230148Sadrian bus, slot, func); 312230148Sadrian 313230148Sadrian if (resource_long_value(device_get_name(dev), device_get_unit(dev), 314230148Sadrian buf, &flash_addr) == 0) { 315230148Sadrian printf("%s: found fixupaddr at %lx: updating\n", 316230148Sadrian __func__, flash_addr); 317230148Sadrian ar71xx_pci_fixup(dev, bus, slot, func, flash_addr); 318230148Sadrian } 319230148Sadrian} 320230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 321230148Sadrian 322187706Sgonzostatic int 323187706Sgonzoar71xx_pci_probe(device_t dev) 324187706Sgonzo{ 325187706Sgonzo 326187706Sgonzo return (0); 327187706Sgonzo} 328187706Sgonzo 329187706Sgonzostatic int 330187706Sgonzoar71xx_pci_attach(device_t dev) 331187706Sgonzo{ 332187706Sgonzo int busno = 0; 333187706Sgonzo int rid = 0; 334187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 335187706Sgonzo 336187706Sgonzo sc->sc_mem_rman.rm_type = RMAN_ARRAY; 337187706Sgonzo sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window"; 338187706Sgonzo if (rman_init(&sc->sc_mem_rman) != 0 || 339187706Sgonzo rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 340187706Sgonzo AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) { 341187706Sgonzo panic("ar71xx_pci_attach: failed to set up I/O rman"); 342187706Sgonzo } 343187706Sgonzo 344187706Sgonzo sc->sc_irq_rman.rm_type = RMAN_ARRAY; 345187706Sgonzo sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs"; 346187706Sgonzo if (rman_init(&sc->sc_irq_rman) != 0 || 347187706Sgonzo rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 348187706Sgonzo AR71XX_PCI_IRQ_END) != 0) 349187706Sgonzo panic("ar71xx_pci_attach: failed to set up IRQ rman"); 350187706Sgonzo 351187706Sgonzo 352187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); 353187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0); 354187706Sgonzo 355187706Sgonzo /* Hook up our interrupt handler. */ 356187706Sgonzo if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 357187706Sgonzo RF_SHAREABLE | RF_ACTIVE)) == NULL) { 358187706Sgonzo device_printf(dev, "unable to allocate IRQ resource\n"); 359187706Sgonzo return ENXIO; 360187706Sgonzo } 361187706Sgonzo 362187706Sgonzo if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 363191872Sgonzo ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) { 364187706Sgonzo device_printf(dev, 365187706Sgonzo "WARNING: unable to register interrupt handler\n"); 366187706Sgonzo return ENXIO; 367187706Sgonzo } 368187706Sgonzo 369187706Sgonzo /* reset PCI core and PCI bus */ 370211478Sadrian ar71xx_device_stop(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 371203132Sgonzo DELAY(100000); 372187706Sgonzo 373211478Sadrian ar71xx_device_start(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 374203132Sgonzo DELAY(100000); 375187706Sgonzo 376187706Sgonzo /* Init PCI windows */ 377187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); 378187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR); 379187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR); 380187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR); 381187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR); 382187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); 383187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); 384187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); 385203132Sgonzo DELAY(100000); 386187706Sgonzo 387187706Sgonzo ar71xx_pci_check_bus_error(); 388187706Sgonzo 389187706Sgonzo /* Fixup internal PCI bridge */ 390187706Sgonzo ar71xx_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, 391187706Sgonzo PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 392187706Sgonzo | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 393187706Sgonzo | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2); 394187706Sgonzo 395230148Sadrian#ifdef AR71XX_ATH_EEPROM 396230148Sadrian /* 397230148Sadrian * Hard-code a check for slot 17 and 18 - these are 398230148Sadrian * the two PCI slots which may have a PCI device that 399230148Sadrian * requires "fixing". 400230148Sadrian */ 401230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 17, 0); 402230148Sadrian ar71xx_pci_slot_fixup(dev, 0, 18, 0); 403230148Sadrian#endif /* AR71XX_ATH_EEPROM */ 404230148Sadrian 405187706Sgonzo device_add_child(dev, "pci", busno); 406187706Sgonzo return (bus_generic_attach(dev)); 407187706Sgonzo} 408187706Sgonzo 409187706Sgonzostatic int 410187706Sgonzoar71xx_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 411187706Sgonzo{ 412187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 413187706Sgonzo 414187706Sgonzo switch (which) { 415187706Sgonzo case PCIB_IVAR_DOMAIN: 416187706Sgonzo *result = 0; 417187706Sgonzo return (0); 418187706Sgonzo case PCIB_IVAR_BUS: 419187706Sgonzo *result = sc->sc_busno; 420187706Sgonzo return (0); 421187706Sgonzo } 422187706Sgonzo 423187706Sgonzo return (ENOENT); 424187706Sgonzo} 425187706Sgonzo 426187706Sgonzostatic int 427187706Sgonzoar71xx_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 428187706Sgonzo{ 429187706Sgonzo struct ar71xx_pci_softc * sc = device_get_softc(dev); 430187706Sgonzo 431187706Sgonzo switch (which) { 432187706Sgonzo case PCIB_IVAR_BUS: 433187706Sgonzo sc->sc_busno = result; 434187706Sgonzo return (0); 435187706Sgonzo } 436187706Sgonzo 437187706Sgonzo return (ENOENT); 438187706Sgonzo} 439187706Sgonzo 440187706Sgonzostatic struct resource * 441187706Sgonzoar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 442187706Sgonzo u_long start, u_long end, u_long count, u_int flags) 443187706Sgonzo{ 444187706Sgonzo 445187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 446192161Sgonzo struct resource *rv; 447187706Sgonzo struct rman *rm; 448187706Sgonzo 449187706Sgonzo switch (type) { 450187706Sgonzo case SYS_RES_IRQ: 451187706Sgonzo rm = &sc->sc_irq_rman; 452187706Sgonzo break; 453187706Sgonzo case SYS_RES_MEMORY: 454187706Sgonzo rm = &sc->sc_mem_rman; 455187706Sgonzo break; 456187706Sgonzo default: 457187706Sgonzo return (NULL); 458187706Sgonzo } 459187706Sgonzo 460187706Sgonzo rv = rman_reserve_resource(rm, start, end, count, flags, child); 461187706Sgonzo 462187706Sgonzo if (rv == NULL) 463187706Sgonzo return (NULL); 464187706Sgonzo 465187706Sgonzo rman_set_rid(rv, *rid); 466187706Sgonzo 467187706Sgonzo if (flags & RF_ACTIVE) { 468187706Sgonzo if (bus_activate_resource(child, type, *rid, rv)) { 469187706Sgonzo rman_release_resource(rv); 470187706Sgonzo return (NULL); 471187706Sgonzo } 472187706Sgonzo } 473187706Sgonzo 474192161Sgonzo 475187706Sgonzo return (rv); 476187706Sgonzo} 477187706Sgonzo 478192161Sgonzo 479187706Sgonzostatic int 480192161Sgonzoar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid, 481192161Sgonzo struct resource *r) 482192161Sgonzo{ 483192161Sgonzo int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 484192161Sgonzo child, type, rid, r)); 485192161Sgonzo 486192161Sgonzo if (!res) { 487192161Sgonzo switch(type) { 488192161Sgonzo case SYS_RES_MEMORY: 489192161Sgonzo case SYS_RES_IOPORT: 490192161Sgonzo rman_set_bustag(r, ar71xx_bus_space_pcimem); 491192161Sgonzo break; 492192161Sgonzo } 493192161Sgonzo } 494192161Sgonzo 495192161Sgonzo return (res); 496192161Sgonzo} 497192161Sgonzo 498192161Sgonzo 499192161Sgonzo 500192161Sgonzostatic int 501191872Sgonzoar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 502191872Sgonzo int flags, driver_filter_t *filt, driver_intr_t *handler, 503191872Sgonzo void *arg, void **cookiep) 504191872Sgonzo{ 505191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 506191872Sgonzo struct intr_event *event; 507191872Sgonzo int irq, error; 508191872Sgonzo 509191872Sgonzo irq = rman_get_start(ires); 510191872Sgonzo 511191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 512191872Sgonzo panic("%s: bad irq %d", __func__, irq); 513191872Sgonzo 514191872Sgonzo event = sc->sc_eventstab[irq]; 515191872Sgonzo if (event == NULL) { 516191872Sgonzo error = intr_event_create(&event, (void *)irq, 0, irq, 517192822Sgonzo ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL, 518210900Sgonzo "pci intr%d:", irq); 519191872Sgonzo 520210900Sgonzo if (error == 0) { 521210900Sgonzo sc->sc_eventstab[irq] = event; 522210900Sgonzo sc->sc_intr_counter[irq] = 523210900Sgonzo mips_intrcnt_create(event->ie_name); 524210900Sgonzo } 525210900Sgonzo else 526210900Sgonzo return error; 527191872Sgonzo } 528191872Sgonzo 529191872Sgonzo intr_event_add_handler(event, device_get_nameunit(child), filt, 530191872Sgonzo handler, arg, intr_priority(flags), flags, cookiep); 531210900Sgonzo mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname); 532191872Sgonzo 533192822Sgonzo ar71xx_pci_unmask_irq((void*)irq); 534191872Sgonzo 535191872Sgonzo return (0); 536191872Sgonzo} 537191872Sgonzo 538191872Sgonzostatic int 539191872Sgonzoar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 540187706Sgonzo void *cookie) 541187706Sgonzo{ 542191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 543191872Sgonzo int irq, result; 544187706Sgonzo 545191872Sgonzo irq = rman_get_start(ires); 546191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 547191872Sgonzo panic("%s: bad irq %d", __func__, irq); 548191872Sgonzo 549191872Sgonzo if (sc->sc_eventstab[irq] == NULL) 550191872Sgonzo panic("Trying to teardown unoccupied IRQ"); 551191872Sgonzo 552192822Sgonzo ar71xx_pci_mask_irq((void*)irq); 553191872Sgonzo 554191872Sgonzo result = intr_event_remove_handler(cookie); 555191872Sgonzo if (!result) 556191872Sgonzo sc->sc_eventstab[irq] = NULL; 557191872Sgonzo 558191872Sgonzo return (result); 559187706Sgonzo} 560187706Sgonzo 561187706Sgonzostatic int 562191872Sgonzoar71xx_pci_intr(void *arg) 563191872Sgonzo{ 564191872Sgonzo struct ar71xx_pci_softc *sc = arg; 565191872Sgonzo struct intr_event *event; 566194273Sgonzo uint32_t reg, irq, mask; 567191872Sgonzo 568191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); 569194273Sgonzo mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 570194273Sgonzo /* 571194273Sgonzo * Handle only unmasked interrupts 572194273Sgonzo */ 573194273Sgonzo reg &= mask; 574191872Sgonzo for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) { 575191872Sgonzo if (reg & (1 << irq)) { 576191872Sgonzo event = sc->sc_eventstab[irq]; 577191872Sgonzo if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 578191872Sgonzo /* Ignore timer interrupts */ 579191872Sgonzo if (irq != 0) 580191872Sgonzo printf("Stray IRQ %d\n", irq); 581191872Sgonzo continue; 582191872Sgonzo } 583191872Sgonzo 584221256Sadrian /* Flush DDR FIFO for IP2 */ 585221256Sadrian ar71xx_device_ddr_flush_ip2(); 586221256Sadrian 587191872Sgonzo /* TODO: frame instead of NULL? */ 588191872Sgonzo intr_event_handle(event, NULL); 589210900Sgonzo mips_intrcnt_inc(sc->sc_intr_counter[irq]); 590191872Sgonzo } 591191872Sgonzo } 592191872Sgonzo 593191872Sgonzo return (FILTER_HANDLED); 594191872Sgonzo} 595191872Sgonzo 596191872Sgonzostatic int 597187706Sgonzoar71xx_pci_maxslots(device_t dev) 598187706Sgonzo{ 599187706Sgonzo 600187706Sgonzo return (PCI_SLOTMAX); 601187706Sgonzo} 602187706Sgonzo 603187706Sgonzostatic int 604187706Sgonzoar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin) 605187706Sgonzo{ 606195474Sgonzo if (pci_get_slot(device) < AR71XX_PCI_BASE_SLOT) 607195474Sgonzo panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT", 608195474Sgonzo __func__, pci_get_slot(device)); 609187706Sgonzo 610195474Sgonzo return (pci_get_slot(device) - AR71XX_PCI_BASE_SLOT); 611187706Sgonzo} 612187706Sgonzo 613187706Sgonzostatic device_method_t ar71xx_pci_methods[] = { 614187706Sgonzo /* Device interface */ 615187706Sgonzo DEVMETHOD(device_probe, ar71xx_pci_probe), 616187706Sgonzo DEVMETHOD(device_attach, ar71xx_pci_attach), 617187706Sgonzo DEVMETHOD(device_shutdown, bus_generic_shutdown), 618187706Sgonzo DEVMETHOD(device_suspend, bus_generic_suspend), 619187706Sgonzo DEVMETHOD(device_resume, bus_generic_resume), 620187706Sgonzo 621187706Sgonzo /* Bus interface */ 622187706Sgonzo DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar), 623187706Sgonzo DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar), 624187706Sgonzo DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource), 625187706Sgonzo DEVMETHOD(bus_release_resource, bus_generic_release_resource), 626192161Sgonzo DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource), 627187706Sgonzo DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 628191872Sgonzo DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr), 629187706Sgonzo DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr), 630187706Sgonzo 631187706Sgonzo /* pcib interface */ 632187706Sgonzo DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots), 633187706Sgonzo DEVMETHOD(pcib_read_config, ar71xx_pci_read_config), 634187706Sgonzo DEVMETHOD(pcib_write_config, ar71xx_pci_write_config), 635187706Sgonzo DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt), 636187706Sgonzo 637227843Smarius DEVMETHOD_END 638187706Sgonzo}; 639187706Sgonzo 640187706Sgonzostatic driver_t ar71xx_pci_driver = { 641187706Sgonzo "pcib", 642187706Sgonzo ar71xx_pci_methods, 643187706Sgonzo sizeof(struct ar71xx_pci_softc), 644187706Sgonzo}; 645187706Sgonzo 646187706Sgonzostatic devclass_t ar71xx_pci_devclass; 647187706Sgonzo 648187706SgonzoDRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0); 649