ar71xx_pci.c revision 195474
1/*- 2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33 34#include <sys/bus.h> 35#include <sys/interrupt.h> 36#include <sys/malloc.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/rman.h> 40 41#include <vm/vm.h> 42#include <vm/pmap.h> 43#include <vm/vm_extern.h> 44 45#include <machine/bus.h> 46#include <machine/cpu.h> 47#include <machine/pmap.h> 48 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51 52#include <dev/pci/pcib_private.h> 53#include "pcib_if.h" 54 55#include <mips/atheros/ar71xxreg.h> 56#include <mips/atheros/ar71xx_pci_bus_space.h> 57 58#undef AR71XX_PCI_DEBUG 59#ifdef AR71XX_PCI_DEBUG 60#define dprintf printf 61#else 62#define dprintf(x, arg...) 63#endif 64 65struct ar71xx_pci_softc { 66 device_t sc_dev; 67 68 int sc_busno; 69 struct rman sc_mem_rman; 70 struct rman sc_irq_rman; 71 72 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 73 struct resource *sc_irq; 74 void *sc_ih; 75}; 76 77static int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 78 driver_filter_t *, driver_intr_t *, void *, void **); 79static int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *, 80 void *); 81static int ar71xx_pci_intr(void *); 82 83static void 84ar71xx_pci_mask_irq(void *source) 85{ 86 uint32_t reg; 87 unsigned int irq = (unsigned int)source; 88 89 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 90 /* flush */ 91 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 92 ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq)); 93} 94 95static void 96ar71xx_pci_unmask_irq(void *source) 97{ 98 uint32_t reg; 99 unsigned int irq = (unsigned int)source; 100 101 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 102 ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); 103 /* flush */ 104 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 105} 106 107/* 108 * get bitmask for bytes of interest: 109 * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte 110 * from register 7. Bitmask would be: 0111 111 */ 112static uint32_t 113ar71xx_get_bytes_to_read(int reg, int bytes) 114{ 115 uint32_t bytes_to_read = 0; 116 if ((bytes % 4) == 0) 117 bytes_to_read = 0; 118 else if ((bytes % 4) == 1) 119 bytes_to_read = (~(1 << (reg % 4))) & 0xf; 120 else if ((bytes % 4) == 2) 121 bytes_to_read = (~(3 << (reg % 4))) & 0xf; 122 else 123 panic("%s: wrong combination", __func__); 124 125 return (bytes_to_read); 126} 127 128static int 129ar71xx_pci_check_bus_error(void) 130{ 131 uint32_t error, addr, has_errors = 0; 132 error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; 133 dprintf("%s: PCI error = %02x\n", __func__, error); 134 if (error) { 135 addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); 136 137 /* Do not report it yet */ 138#if 0 139 printf("PCI bus error %d at addr 0x%08x\n", error, addr); 140#endif 141 ATH_WRITE_REG(AR71XX_PCI_ERROR, error); 142 has_errors = 1; 143 } 144 145 error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; 146 dprintf("%s: AHB error = %02x\n", __func__, error); 147 if (error) { 148 addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); 149 /* Do not report it yet */ 150#if 0 151 printf("AHB bus error %d at addr 0x%08x\n", error, addr); 152#endif 153 ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); 154 has_errors = 1; 155 } 156 157 return (has_errors); 158} 159 160static uint32_t 161ar71xx_pci_make_addr(int bus, int slot, int func, int reg) 162{ 163 if (bus == 0) { 164 return ((1 << slot) | (func << 8) | (reg & ~3)); 165 } else { 166 return ((bus << 16) | (slot << 11) | (func << 8) 167 | (reg & ~3) | 1); 168 } 169} 170 171static int 172ar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes, 173 uint32_t cmd) 174{ 175 uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3)); 176 cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4); 177 178 ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); 179 ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); 180 181 dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 182 bus, slot, func, reg, bytes, addr, cmd); 183 184 return ar71xx_pci_check_bus_error(); 185} 186 187static uint32_t 188ar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 189 u_int reg, int bytes) 190{ 191 uint32_t data; 192 uint32_t cmd, shift, mask; 193 194 /* register access is 32-bit aligned */ 195 shift = (reg & 3) * 8; 196 if (shift) 197 mask = (1 << shift) - 1; 198 else 199 mask = 0xffffffff; 200 201 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 202 func, reg, bytes); 203 204 if ((bus == 0) && (slot == 0) && (func == 0)) { 205 cmd = PCI_LCONF_CMD_READ | (reg & ~3); 206 ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 207 data = ATH_READ_REG(AR71XX_PCI_LCONF_READ_DATA); 208 } else { 209 if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 210 PCI_CONF_CMD_READ) == 0) 211 data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); 212 else 213 data = -1; 214 } 215 216 /* get request bytes from 32-bit word */ 217 data = (data >> shift) & mask; 218 219 dprintf("%s: read 0x%x\n", __func__, data); 220 221 return (data); 222} 223 224static void 225ar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 226 u_int reg, uint32_t data, int bytes) 227{ 228 uint32_t cmd; 229 230 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 231 func, reg, bytes); 232 233 data = data << (8*(reg % 4)); 234 235 if ((bus == 0) && (slot == 0) && (func == 0)) { 236 cmd = PCI_LCONF_CMD_WRITE | (reg & ~3); 237 cmd |= ar71xx_get_bytes_to_read(reg, bytes) << 20; 238 ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 239 ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); 240 } else { 241 if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 242 PCI_CONF_CMD_WRITE) == 0) 243 ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); 244 } 245} 246 247static int 248ar71xx_pci_probe(device_t dev) 249{ 250 251 return (0); 252} 253 254static int 255ar71xx_pci_attach(device_t dev) 256{ 257 int busno = 0; 258 int rid = 0; 259 uint32_t reset; 260 struct ar71xx_pci_softc *sc = device_get_softc(dev); 261 262 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 263 sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window"; 264 if (rman_init(&sc->sc_mem_rman) != 0 || 265 rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 266 AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) { 267 panic("ar71xx_pci_attach: failed to set up I/O rman"); 268 } 269 270 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 271 sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs"; 272 if (rman_init(&sc->sc_irq_rman) != 0 || 273 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 274 AR71XX_PCI_IRQ_END) != 0) 275 panic("ar71xx_pci_attach: failed to set up IRQ rman"); 276 277 278 ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); 279 ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0); 280 281 /* Hook up our interrupt handler. */ 282 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 283 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 284 device_printf(dev, "unable to allocate IRQ resource\n"); 285 return ENXIO; 286 } 287 288 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 289 ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) { 290 device_printf(dev, 291 "WARNING: unable to register interrupt handler\n"); 292 return ENXIO; 293 } 294 295 /* reset PCI core and PCI bus */ 296 reset = ATH_READ_REG(AR71XX_RST_RESET); 297 reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 298 ATH_WRITE_REG(AR71XX_RST_RESET, reset); 299 ATH_READ_REG(AR71XX_RST_RESET); 300 DELAY(1000); 301 302 reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 303 ATH_WRITE_REG(AR71XX_RST_RESET, reset); 304 ATH_READ_REG(AR71XX_RST_RESET); 305 DELAY(1000); 306 307 /* Init PCI windows */ 308 ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); 309 ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR); 310 ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR); 311 ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR); 312 ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR); 313 ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); 314 ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); 315 ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); 316 DELAY(1000); 317 318 ar71xx_pci_check_bus_error(); 319 320 /* Fixup internal PCI bridge */ 321 ar71xx_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, 322 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 323 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 324 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2); 325 326 device_add_child(dev, "pci", busno); 327 return (bus_generic_attach(dev)); 328} 329 330static int 331ar71xx_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 332{ 333 struct ar71xx_pci_softc *sc = device_get_softc(dev); 334 335 switch (which) { 336 case PCIB_IVAR_DOMAIN: 337 *result = 0; 338 return (0); 339 case PCIB_IVAR_BUS: 340 *result = sc->sc_busno; 341 return (0); 342 } 343 344 return (ENOENT); 345} 346 347static int 348ar71xx_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 349{ 350 struct ar71xx_pci_softc * sc = device_get_softc(dev); 351 352 switch (which) { 353 case PCIB_IVAR_BUS: 354 sc->sc_busno = result; 355 return (0); 356 } 357 358 return (ENOENT); 359} 360 361static struct resource * 362ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 363 u_long start, u_long end, u_long count, u_int flags) 364{ 365 366 struct ar71xx_pci_softc *sc = device_get_softc(bus); 367 struct resource *rv; 368 struct rman *rm; 369 370 switch (type) { 371 case SYS_RES_IRQ: 372 rm = &sc->sc_irq_rman; 373 break; 374 case SYS_RES_MEMORY: 375 rm = &sc->sc_mem_rman; 376 break; 377 default: 378 return (NULL); 379 } 380 381 rv = rman_reserve_resource(rm, start, end, count, flags, child); 382 383 if (rv == NULL) 384 return (NULL); 385 386 rman_set_rid(rv, *rid); 387 388 if (flags & RF_ACTIVE) { 389 if (bus_activate_resource(child, type, *rid, rv)) { 390 rman_release_resource(rv); 391 return (NULL); 392 } 393 } 394 395 396 return (rv); 397} 398 399 400static int 401ar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid, 402 struct resource *r) 403{ 404 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 405 child, type, rid, r)); 406 407 if (!res) { 408 switch(type) { 409 case SYS_RES_MEMORY: 410 case SYS_RES_IOPORT: 411 rman_set_bustag(r, ar71xx_bus_space_pcimem); 412 break; 413 } 414 } 415 416 return (res); 417} 418 419 420 421static int 422ar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 423 int flags, driver_filter_t *filt, driver_intr_t *handler, 424 void *arg, void **cookiep) 425{ 426 struct ar71xx_pci_softc *sc = device_get_softc(bus); 427 struct intr_event *event; 428 int irq, error; 429 430 irq = rman_get_start(ires); 431 432 if (irq > AR71XX_PCI_IRQ_END) 433 panic("%s: bad irq %d", __func__, irq); 434 435 event = sc->sc_eventstab[irq]; 436 if (event == NULL) { 437 error = intr_event_create(&event, (void *)irq, 0, irq, 438 ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL, 439 "ar71xx_pci intr%d:", irq); 440 441 sc->sc_eventstab[irq] = event; 442 } 443 444 intr_event_add_handler(event, device_get_nameunit(child), filt, 445 handler, arg, intr_priority(flags), flags, cookiep); 446 447 ar71xx_pci_unmask_irq((void*)irq); 448 449 return (0); 450} 451 452static int 453ar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 454 void *cookie) 455{ 456 struct ar71xx_pci_softc *sc = device_get_softc(dev); 457 int irq, result; 458 459 irq = rman_get_start(ires); 460 if (irq > AR71XX_PCI_IRQ_END) 461 panic("%s: bad irq %d", __func__, irq); 462 463 if (sc->sc_eventstab[irq] == NULL) 464 panic("Trying to teardown unoccupied IRQ"); 465 466 ar71xx_pci_mask_irq((void*)irq); 467 468 result = intr_event_remove_handler(cookie); 469 if (!result) 470 sc->sc_eventstab[irq] = NULL; 471 472 return (result); 473} 474 475static int 476ar71xx_pci_intr(void *arg) 477{ 478 struct ar71xx_pci_softc *sc = arg; 479 struct intr_event *event; 480 uint32_t reg, irq, mask; 481 482 reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); 483 mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 484 /* 485 * Handle only unmasked interrupts 486 */ 487 reg &= mask; 488 for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) { 489 if (reg & (1 << irq)) { 490 event = sc->sc_eventstab[irq]; 491 if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 492 /* Ignore timer interrupts */ 493 if (irq != 0) 494 printf("Stray IRQ %d\n", irq); 495 continue; 496 } 497 498 /* TODO: frame instead of NULL? */ 499 intr_event_handle(event, NULL); 500 } 501 } 502 503 return (FILTER_HANDLED); 504} 505 506static int 507ar71xx_pci_maxslots(device_t dev) 508{ 509 510 return (PCI_SLOTMAX); 511} 512 513static int 514ar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin) 515{ 516 if (pci_get_slot(device) < AR71XX_PCI_BASE_SLOT) 517 panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT", 518 __func__, pci_get_slot(device)); 519 520 return (pci_get_slot(device) - AR71XX_PCI_BASE_SLOT); 521} 522 523static device_method_t ar71xx_pci_methods[] = { 524 /* Device interface */ 525 DEVMETHOD(device_probe, ar71xx_pci_probe), 526 DEVMETHOD(device_attach, ar71xx_pci_attach), 527 DEVMETHOD(device_shutdown, bus_generic_shutdown), 528 DEVMETHOD(device_suspend, bus_generic_suspend), 529 DEVMETHOD(device_resume, bus_generic_resume), 530 531 /* Bus interface */ 532 DEVMETHOD(bus_print_child, bus_generic_print_child), 533 DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar), 534 DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar), 535 DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource), 536 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 537 DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource), 538 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 539 DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr), 540 DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr), 541 542 /* pcib interface */ 543 DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots), 544 DEVMETHOD(pcib_read_config, ar71xx_pci_read_config), 545 DEVMETHOD(pcib_write_config, ar71xx_pci_write_config), 546 DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt), 547 548 {0, 0} 549}; 550 551static driver_t ar71xx_pci_driver = { 552 "pcib", 553 ar71xx_pci_methods, 554 sizeof(struct ar71xx_pci_softc), 555}; 556 557static devclass_t ar71xx_pci_devclass; 558 559DRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0); 560