ar71xx_cpudef.h revision 263296
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: head/sys/mips/atheros/ar71xx_cpudef.h 263296 2014-03-18 12:19:39Z adrian $ */ 28 29#ifndef __AR71XX_CPUDEF_H__ 30#define __AR71XX_CPUDEF_H__ 31 32struct ar71xx_cpu_def { 33 void (* detect_mem_size) (void); 34 void (* detect_sys_frequency) (void); 35 void (* ar71xx_chip_device_stop) (uint32_t); 36 void (* ar71xx_chip_device_start) (uint32_t); 37 int (* ar71xx_chip_device_stopped) (uint32_t); 38 void (* ar71xx_chip_set_pll_ge) (int, int, uint32_t); 39 void (* ar71xx_chip_set_mii_speed) (uint32_t, uint32_t); 40 void (* ar71xx_chip_set_mii_if) (uint32_t, ar71xx_mii_mode); 41 void (* ar71xx_chip_ddr_flush_ge) (int); 42 uint32_t (* ar71xx_chip_get_eth_pll) (unsigned int, int); 43 44 /* 45 * From Linux - Handling this IRQ is a bit special. 46 * AR71xx - AR71XX_DDR_REG_FLUSH_PCI 47 * AR724x - AR724X_DDR_REG_FLUSH_PCIE 48 * AR91xx - AR91XX_DDR_REG_FLUSH_WMAC 49 * 50 * These are set when STATUSF_IP2 is set in regiser c0. 51 * This flush is done before the IRQ is handled to make 52 * sure the driver correctly sees any memory updates. 53 */ 54 void (* ar71xx_chip_ddr_flush_ip2) (void); 55 /* 56 * The USB peripheral init code is subtly different for 57 * each chip. 58 */ 59 void (* ar71xx_chip_init_usb_peripheral) (void); 60 61 void (* ar71xx_chip_reset_ethernet_switch) (void); 62 63 void (* ar71xx_chip_reset_wmac) (void); 64 65 void (* ar71xx_chip_init_gmac) (void); 66 67 void (* ar71xx_chip_reset_nfc) (int); 68}; 69 70extern struct ar71xx_cpu_def * ar71xx_cpu_ops; 71 72static inline void ar71xx_detect_sys_frequency(void) 73{ 74 ar71xx_cpu_ops->detect_sys_frequency(); 75} 76 77static inline void ar71xx_device_stop(uint32_t mask) 78{ 79 ar71xx_cpu_ops->ar71xx_chip_device_stop(mask); 80} 81 82static inline void ar71xx_device_start(uint32_t mask) 83{ 84 ar71xx_cpu_ops->ar71xx_chip_device_start(mask); 85} 86 87static inline int ar71xx_device_stopped(uint32_t mask) 88{ 89 return ar71xx_cpu_ops->ar71xx_chip_device_stopped(mask); 90} 91 92static inline void ar71xx_device_set_pll_ge(int unit, int speed, uint32_t pll) 93{ 94 ar71xx_cpu_ops->ar71xx_chip_set_pll_ge(unit, speed, pll); 95} 96 97static inline void ar71xx_device_set_mii_speed(int unit, int speed) 98{ 99 ar71xx_cpu_ops->ar71xx_chip_set_mii_speed(unit, speed); 100} 101 102static inline void ar71xx_device_set_mii_if(int unit, ar71xx_mii_mode mii_cfg) 103{ 104 ar71xx_cpu_ops->ar71xx_chip_set_mii_if(unit, mii_cfg); 105} 106 107static inline void ar71xx_device_flush_ddr_ge(int unit) 108{ 109 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ge(unit); 110} 111 112static inline uint32_t ar71xx_device_get_eth_pll(unsigned int unit, int speed) 113{ 114 return (ar71xx_cpu_ops->ar71xx_chip_get_eth_pll(unit, speed)); 115} 116 117static inline void ar71xx_init_usb_peripheral(void) 118{ 119 ar71xx_cpu_ops->ar71xx_chip_init_usb_peripheral(); 120} 121 122static inline void ar71xx_reset_ethernet_switch(void) 123{ 124 if (ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch) 125 ar71xx_cpu_ops->ar71xx_chip_reset_ethernet_switch(); 126} 127 128static inline void ar71xx_reset_wmac(void) 129{ 130 if (ar71xx_cpu_ops->ar71xx_chip_reset_wmac) 131 ar71xx_cpu_ops->ar71xx_chip_reset_wmac(); 132} 133 134static inline void ar71xx_init_gmac(void) 135{ 136 if (ar71xx_cpu_ops->ar71xx_chip_init_gmac) 137 ar71xx_cpu_ops->ar71xx_chip_init_gmac(); 138} 139 140static inline void ar71xx_device_ddr_flush_ip2(void) 141{ 142 ar71xx_cpu_ops->ar71xx_chip_ddr_flush_ip2(); 143} 144 145static inline void ar71xx_reset_nfc(int active) 146{ 147 148 if (ar71xx_cpu_ops->ar71xx_chip_reset_nfc) 149 ar71xx_cpu_ops->ar71xx_chip_reset_nfc(active); 150} 151 152/* XXX shouldn't be here! */ 153extern uint32_t u_ar71xx_refclk; 154extern uint32_t u_ar71xx_cpu_freq; 155extern uint32_t u_ar71xx_ahb_freq; 156extern uint32_t u_ar71xx_ddr_freq; 157extern uint32_t u_ar71xx_uart_freq; 158extern uint32_t u_ar71xx_wdt_freq; 159extern uint32_t u_ar71xx_mdio_freq; 160 161static inline uint64_t ar71xx_refclk(void) { return u_ar71xx_refclk; } 162static inline uint64_t ar71xx_cpu_freq(void) { return u_ar71xx_cpu_freq; } 163static inline uint64_t ar71xx_ahb_freq(void) { return u_ar71xx_ahb_freq; } 164static inline uint64_t ar71xx_ddr_freq(void) { return u_ar71xx_ddr_freq; } 165static inline uint64_t ar71xx_uart_freq(void) { return u_ar71xx_uart_freq; } 166static inline uint64_t ar71xx_wdt_freq(void) { return u_ar71xx_wdt_freq; } 167static inline uint64_t ar71xx_mdio_freq(void) { return u_ar71xx_mdio_freq; } 168 169#endif 170