ar71xx_chip.c revision 234907 
1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 234907 2012-05-02 04:51:43Z adrian $");
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar71xx_chip.h>
56#include <mips/atheros/ar71xx_cpudef.h>
57
58#include <mips/sentry5/s5reg.h>
59
60/* XXX these should replace the current definitions in ar71xxreg.h */
61/* XXX perhaps an ar71xx_chip.h header file? */
62#define AR71XX_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
63#define AR71XX_PLL_REG_SEC_CONFIG       AR71XX_PLL_CPU_BASE + 0x04
64#define AR71XX_PLL_REG_ETH0_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x10
65#define AR71XX_PLL_REG_ETH1_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x14
66
67#define AR71XX_PLL_DIV_SHIFT            3
68#define AR71XX_PLL_DIV_MASK             0x1f
69#define AR71XX_CPU_DIV_SHIFT            16
70#define AR71XX_CPU_DIV_MASK             0x3
71#define AR71XX_DDR_DIV_SHIFT            18
72#define AR71XX_DDR_DIV_MASK             0x3
73#define AR71XX_AHB_DIV_SHIFT            20
74#define AR71XX_AHB_DIV_MASK             0x7
75
76/* XXX these shouldn't be in here - this file is a per-chip file */
77/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
78uint32_t u_ar71xx_cpu_freq;
79uint32_t u_ar71xx_ahb_freq;
80uint32_t u_ar71xx_ddr_freq;
81
82static void
83ar71xx_chip_detect_mem_size(void)
84{
85}
86
87static void
88ar71xx_chip_detect_sys_frequency(void)
89{
90	uint32_t pll;
91	uint32_t freq;
92	uint32_t div;
93
94	pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
95
96	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
97	freq = div * AR71XX_BASE_FREQ;
98
99	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
100	u_ar71xx_cpu_freq = freq / div;
101
102	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
103	u_ar71xx_ddr_freq = freq / div;
104
105	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
106	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
107}
108
109/*
110 * This does not lock the CPU whilst doing the work!
111 */
112static void
113ar71xx_chip_device_stop(uint32_t mask)
114{
115	uint32_t reg;
116
117	reg = ATH_READ_REG(AR71XX_RST_RESET);
118	ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
119}
120
121static void
122ar71xx_chip_device_start(uint32_t mask)
123{
124	uint32_t reg;
125
126	reg = ATH_READ_REG(AR71XX_RST_RESET);
127	ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
128}
129
130static int
131ar71xx_chip_device_stopped(uint32_t mask)
132{
133	uint32_t reg;
134
135	reg = ATH_READ_REG(AR71XX_RST_RESET);
136	return ((reg & mask) == mask);
137}
138
139void
140ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed)
141{
142	uint32_t val, reg, ctrl;
143
144	switch (unit) {
145	case 0:
146		reg = AR71XX_MII0_CTRL;
147		break;
148	case 1:
149		reg = AR71XX_MII1_CTRL;
150		break;
151	default:
152		printf("%s: invalid MII unit set for arge unit: %d\n",
153		    __func__, unit);
154		return;
155	}
156
157	switch (speed) {
158	case 10:
159		ctrl = MII_CTRL_SPEED_10;
160		break;
161	case 100:
162		ctrl = MII_CTRL_SPEED_100;
163		break;
164	case 1000:
165		ctrl = MII_CTRL_SPEED_1000;
166		break;
167	default:
168		printf("%s: invalid MII speed (%d) set for arge unit: %d\n",
169		    __func__, speed, unit);
170		return;
171	}
172
173	val = ATH_READ_REG(reg);
174	val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
175	val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
176	ATH_WRITE_REG(reg, val);
177}
178
179void
180ar71xx_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
181{
182	uint32_t val, reg, mii_if;
183
184	switch (unit) {
185	case 0:
186		reg = AR71XX_MII0_CTRL;
187		if (mii_mode == AR71XX_MII_MODE_GMII)
188			mii_if = MII0_CTRL_IF_GMII;
189		else if (mii_mode == AR71XX_MII_MODE_MII)
190			mii_if = MII0_CTRL_IF_MII;
191		else if (mii_mode == AR71XX_MII_MODE_RGMII)
192			mii_if = MII0_CTRL_IF_RGMII;
193		else if (mii_mode == AR71XX_MII_MODE_RMII)
194			mii_if = MII0_CTRL_IF_RMII;
195		else
196			printf("%s: invalid MII mode (%d) for unit %d\n",
197			    __func__, mii_mode, unit);
198			return;
199		break;
200	case 1:
201		reg = AR71XX_MII1_CTRL;
202		if (mii_mode == AR71XX_MII_MODE_RGMII)
203			mii_if = MII1_CTRL_IF_RGMII;
204		if (mii_mode == AR71XX_MII_MODE_RMII)
205			mii_if = MII1_CTRL_IF_RMII;
206		else
207			printf("%s: invalid MII mode (%d) for unit %d\n",
208			    __func__, mii_mode, unit);
209			return;
210		break;
211	default:
212		printf("%s: invalid MII unit set for arge unit: %d\n",
213		    __func__, unit);
214		return;
215	}
216
217	val = ATH_READ_REG(reg);
218	val &= ~(MII_CTRL_IF_MASK << MII_CTRL_IF_SHIFT);
219	val |= (mii_if & MII_CTRL_IF_MASK) << MII_CTRL_IF_SHIFT;
220	ATH_WRITE_REG(reg, val);
221}
222
223/* Speed is either 10, 100 or 1000 */
224static void
225ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll)
226{
227
228	switch (unit) {
229	case 0:
230		ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
231		    AR71XX_PLL_ETH_INT0_CLK, pll,
232		    AR71XX_PLL_ETH0_SHIFT);
233		break;
234	case 1:
235		ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
236		    AR71XX_PLL_ETH_INT1_CLK, pll,
237		    AR71XX_PLL_ETH1_SHIFT);
238		break;
239	default:
240		printf("%s: invalid PLL set for arge unit: %d\n",
241		    __func__, unit);
242		return;
243	}
244}
245
246static void
247ar71xx_chip_ddr_flush_ge(int unit)
248{
249
250	switch (unit) {
251	case 0:
252		ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
253		break;
254	case 1:
255		ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
256		break;
257	default:
258		printf("%s: invalid DDR flush for arge unit: %d\n",
259		    __func__, unit);
260		return;
261	}
262}
263
264static void
265ar71xx_chip_ddr_flush_ip2(void)
266{
267	ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI);
268}
269
270static uint32_t
271ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
272{
273	uint32_t pll;
274
275	switch (speed) {
276	case 10:
277		pll = PLL_ETH_INT_CLK_10;
278		break;
279	case 100:
280		pll = PLL_ETH_INT_CLK_100;
281		break;
282	case 1000:
283		pll = PLL_ETH_INT_CLK_1000;
284		break;
285	default:
286		printf("%s%d: invalid speed %d\n", __func__, mac, speed);
287		pll = 0;
288	}
289
290	return (pll);
291}
292
293static void
294ar71xx_chip_init_usb_peripheral(void)
295{
296
297	ar71xx_device_stop(RST_RESET_USB_OHCI_DLL |
298	    RST_RESET_USB_HOST | RST_RESET_USB_PHY);
299	DELAY(1000);
300
301	ar71xx_device_start(RST_RESET_USB_OHCI_DLL |
302	    RST_RESET_USB_HOST | RST_RESET_USB_PHY);
303	DELAY(1000);
304
305	ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
306	    USB_CTRL_CONFIG_OHCI_DES_SWAP |
307	    USB_CTRL_CONFIG_OHCI_BUF_SWAP |
308	    USB_CTRL_CONFIG_EHCI_DES_SWAP |
309	    USB_CTRL_CONFIG_EHCI_BUF_SWAP);
310
311	ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
312	    (32 << USB_CTRL_FLADJ_HOST_SHIFT) |
313	    (3 << USB_CTRL_FLADJ_A5_SHIFT));
314
315	DELAY(1000);
316}
317
318struct ar71xx_cpu_def ar71xx_chip_def = {
319	&ar71xx_chip_detect_mem_size,
320	&ar71xx_chip_detect_sys_frequency,
321	&ar71xx_chip_device_stop,
322	&ar71xx_chip_device_start,
323	&ar71xx_chip_device_stopped,
324	&ar71xx_chip_set_pll_ge,
325	&ar71xx_chip_set_mii_speed,
326	&ar71xx_chip_set_mii_if,
327	&ar71xx_chip_ddr_flush_ge,
328	&ar71xx_chip_get_eth_pll,
329	&ar71xx_chip_ddr_flush_ip2,
330	&ar71xx_chip_init_usb_peripheral,
331};
332