ar71xx_chip.c revision 233081
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 233081 2012-03-17 07:25:23Z adrian $"); 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/cons.h> 38#include <sys/kdb.h> 39#include <sys/reboot.h> 40 41#include <vm/vm.h> 42#include <vm/vm_page.h> 43 44#include <net/ethernet.h> 45 46#include <machine/clock.h> 47#include <machine/cpu.h> 48#include <machine/cpuregs.h> 49#include <machine/hwfunc.h> 50#include <machine/md_var.h> 51#include <machine/trap.h> 52#include <machine/vmparam.h> 53 54#include <mips/atheros/ar71xxreg.h> 55#include <mips/atheros/ar71xx_chip.h> 56#include <mips/atheros/ar71xx_cpudef.h> 57 58#include <mips/sentry5/s5reg.h> 59 60/* XXX these should replace the current definitions in ar71xxreg.h */ 61/* XXX perhaps an ar71xx_chip.h header file? */ 62#define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 63#define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04 64#define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10 65#define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14 66 67#define AR71XX_PLL_DIV_SHIFT 3 68#define AR71XX_PLL_DIV_MASK 0x1f 69#define AR71XX_CPU_DIV_SHIFT 16 70#define AR71XX_CPU_DIV_MASK 0x3 71#define AR71XX_DDR_DIV_SHIFT 18 72#define AR71XX_DDR_DIV_MASK 0x3 73#define AR71XX_AHB_DIV_SHIFT 20 74#define AR71XX_AHB_DIV_MASK 0x7 75 76/* XXX these shouldn't be in here - this file is a per-chip file */ 77/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */ 78uint32_t u_ar71xx_cpu_freq; 79uint32_t u_ar71xx_ahb_freq; 80uint32_t u_ar71xx_ddr_freq; 81 82static void 83ar71xx_chip_detect_mem_size(void) 84{ 85} 86 87static void 88ar71xx_chip_detect_sys_frequency(void) 89{ 90 uint32_t pll; 91 uint32_t freq; 92 uint32_t div; 93 94 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); 95 96 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 97 freq = div * AR71XX_BASE_FREQ; 98 99 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 100 u_ar71xx_cpu_freq = freq / div; 101 102 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 103 u_ar71xx_ddr_freq = freq / div; 104 105 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 106 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; 107} 108 109/* 110 * This does not lock the CPU whilst doing the work! 111 */ 112static void 113ar71xx_chip_device_stop(uint32_t mask) 114{ 115 uint32_t reg; 116 117 reg = ATH_READ_REG(AR71XX_RST_RESET); 118 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask); 119} 120 121static void 122ar71xx_chip_device_start(uint32_t mask) 123{ 124 uint32_t reg; 125 126 reg = ATH_READ_REG(AR71XX_RST_RESET); 127 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask); 128} 129 130static int 131ar71xx_chip_device_stopped(uint32_t mask) 132{ 133 uint32_t reg; 134 135 reg = ATH_READ_REG(AR71XX_RST_RESET); 136 return ((reg & mask) == mask); 137} 138 139static void 140ar71xx_chip_set_mii_speed(uint32_t unit, uint32_t speed) 141{ 142 uint32_t val, reg, ctrl; 143 144 switch (unit) { 145 case 0: 146 reg = AR71XX_MII0_CTRL; 147 break; 148 case 1: 149 reg = AR71XX_MII1_CTRL; 150 break; 151 default: 152 printf("%s: invalid MII unit set for arge unit: %d\n", 153 __func__, unit); 154 return; 155 } 156 157 switch (speed) { 158 case 10: 159 ctrl = MII_CTRL_SPEED_10; 160 break; 161 case 100: 162 ctrl = MII_CTRL_SPEED_100; 163 break; 164 case 1000: 165 ctrl = MII_CTRL_SPEED_1000; 166 break; 167 default: 168 printf("%s: invalid MII speed (%d) set for arge unit: %d\n", 169 __func__, speed, unit); 170 return; 171 } 172 173 val = ATH_READ_REG(reg); 174 val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); 175 val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; 176 ATH_WRITE_REG(reg, val); 177} 178 179/* Speed is either 10, 100 or 1000 */ 180static void 181ar71xx_chip_set_pll_ge(int unit, int speed) 182{ 183 uint32_t pll; 184 185 switch (speed) { 186 case 10: 187 pll = PLL_ETH_INT_CLK_10; 188 break; 189 case 100: 190 pll = PLL_ETH_INT_CLK_100; 191 break; 192 case 1000: 193 pll = PLL_ETH_INT_CLK_1000; 194 break; 195 default: 196 printf("%s%d: invalid speed %d\n", 197 __func__, unit, speed); 198 return; 199 } 200 switch (unit) { 201 case 0: 202 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 203 AR71XX_PLL_ETH_INT0_CLK, pll, 204 AR71XX_PLL_ETH0_SHIFT); 205 break; 206 case 1: 207 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 208 AR71XX_PLL_ETH_INT1_CLK, pll, 209 AR71XX_PLL_ETH1_SHIFT); 210 break; 211 default: 212 printf("%s: invalid PLL set for arge unit: %d\n", 213 __func__, unit); 214 return; 215 } 216} 217 218static void 219ar71xx_chip_ddr_flush_ge(int unit) 220{ 221 222 switch (unit) { 223 case 0: 224 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); 225 break; 226 case 1: 227 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); 228 break; 229 default: 230 printf("%s: invalid DDR flush for arge unit: %d\n", 231 __func__, unit); 232 return; 233 } 234} 235 236static void 237ar71xx_chip_ddr_flush_ip2(void) 238{ 239 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 240} 241 242static uint32_t 243ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 244{ 245 return 0; 246} 247 248static void 249ar71xx_chip_init_usb_peripheral(void) 250{ 251 252 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | 253 RST_RESET_USB_HOST | RST_RESET_USB_PHY); 254 DELAY(1000); 255 256 ar71xx_device_start(RST_RESET_USB_OHCI_DLL | 257 RST_RESET_USB_HOST | RST_RESET_USB_PHY); 258 DELAY(1000); 259 260 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, 261 USB_CTRL_CONFIG_OHCI_DES_SWAP | 262 USB_CTRL_CONFIG_OHCI_BUF_SWAP | 263 USB_CTRL_CONFIG_EHCI_DES_SWAP | 264 USB_CTRL_CONFIG_EHCI_BUF_SWAP); 265 266 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, 267 (32 << USB_CTRL_FLADJ_HOST_SHIFT) | 268 (3 << USB_CTRL_FLADJ_A5_SHIFT)); 269 270 DELAY(1000); 271} 272 273struct ar71xx_cpu_def ar71xx_chip_def = { 274 &ar71xx_chip_detect_mem_size, 275 &ar71xx_chip_detect_sys_frequency, 276 &ar71xx_chip_device_stop, 277 &ar71xx_chip_device_start, 278 &ar71xx_chip_device_stopped, 279 &ar71xx_chip_set_pll_ge, 280 &ar71xx_chip_set_mii_speed, 281 &ar71xx_chip_ddr_flush_ge, 282 &ar71xx_chip_get_eth_pll, 283 &ar71xx_chip_ddr_flush_ip2, 284 &ar71xx_chip_init_usb_peripheral, 285}; 286