ar71xx_chip.c revision 228018
1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 228018 2011-11-27 11:15:59Z ray $"); 29 30#include "opt_ddb.h" 31 32#include <sys/param.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/cons.h> 38#include <sys/kdb.h> 39#include <sys/reboot.h> 40 41#include <vm/vm.h> 42#include <vm/vm_page.h> 43 44#include <net/ethernet.h> 45 46#include <machine/clock.h> 47#include <machine/cpu.h> 48#include <machine/cpuregs.h> 49#include <machine/hwfunc.h> 50#include <machine/md_var.h> 51#include <machine/trap.h> 52#include <machine/vmparam.h> 53 54#include <mips/atheros/ar71xxreg.h> 55 56#include <mips/atheros/ar71xx_chip.h> 57 58#include <mips/atheros/ar71xx_cpudef.h> 59 60#include <mips/sentry5/s5reg.h> 61 62/* XXX these should replace the current definitions in ar71xxreg.h */ 63/* XXX perhaps an ar71xx_chip.h header file? */ 64#define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 65#define AR71XX_PLL_REG_SEC_CONFIG AR71XX_PLL_CPU_BASE + 0x04 66#define AR71XX_PLL_REG_ETH0_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x10 67#define AR71XX_PLL_REG_ETH1_INT_CLOCK AR71XX_PLL_CPU_BASE + 0x14 68 69#define AR71XX_PLL_DIV_SHIFT 3 70#define AR71XX_PLL_DIV_MASK 0x1f 71#define AR71XX_CPU_DIV_SHIFT 16 72#define AR71XX_CPU_DIV_MASK 0x3 73#define AR71XX_DDR_DIV_SHIFT 18 74#define AR71XX_DDR_DIV_MASK 0x3 75#define AR71XX_AHB_DIV_SHIFT 20 76#define AR71XX_AHB_DIV_MASK 0x7 77 78/* XXX these shouldn't be in here - this file is a per-chip file */ 79/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */ 80uint32_t u_ar71xx_cpu_freq; 81uint32_t u_ar71xx_ahb_freq; 82uint32_t u_ar71xx_ddr_freq; 83 84static void 85ar71xx_chip_detect_mem_size(void) 86{ 87} 88 89static void 90ar71xx_chip_detect_sys_frequency(void) 91{ 92 uint32_t pll; 93 uint32_t freq; 94 uint32_t div; 95 96 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); 97 98 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; 99 freq = div * AR71XX_BASE_FREQ; 100 101 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; 102 u_ar71xx_cpu_freq = freq / div; 103 104 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; 105 u_ar71xx_ddr_freq = freq / div; 106 107 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; 108 u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div; 109} 110 111/* 112 * This does not lock the CPU whilst doing the work! 113 */ 114static void 115ar71xx_chip_device_stop(uint32_t mask) 116{ 117 uint32_t reg; 118 119 reg = ATH_READ_REG(AR71XX_RST_RESET); 120 ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask); 121} 122 123static void 124ar71xx_chip_device_start(uint32_t mask) 125{ 126 uint32_t reg; 127 128 reg = ATH_READ_REG(AR71XX_RST_RESET); 129 ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask); 130} 131 132static int 133ar71xx_chip_device_stopped(uint32_t mask) 134{ 135 uint32_t reg; 136 137 reg = ATH_READ_REG(AR71XX_RST_RESET); 138 return ((reg & mask) == mask); 139} 140 141/* Speed is either 10, 100 or 1000 */ 142static void 143ar71xx_chip_set_pll_ge(int unit, int speed) 144{ 145 uint32_t pll; 146 147 switch(speed) { 148 case 10: 149 pll = PLL_ETH_INT_CLK_10; 150 break; 151 case 100: 152 pll = PLL_ETH_INT_CLK_100; 153 break; 154 case 1000: 155 pll = PLL_ETH_INT_CLK_1000; 156 break; 157 default: 158 printf("%s%d: invalid speed %d\n", 159 __func__, unit, speed); 160 return; 161 } 162 switch (unit) { 163 case 0: 164 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 165 AR71XX_PLL_ETH_INT0_CLK, pll, 166 AR71XX_PLL_ETH0_SHIFT); 167 break; 168 case 1: 169 ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, 170 AR71XX_PLL_ETH_INT1_CLK, pll, 171 AR71XX_PLL_ETH1_SHIFT); 172 break; 173 default: 174 printf("%s: invalid PLL set for arge unit: %d\n", 175 __func__, unit); 176 return; 177 } 178} 179 180static void 181ar71xx_chip_ddr_flush_ge(int unit) 182{ 183 switch (unit) { 184 case 0: 185 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0); 186 break; 187 case 1: 188 ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1); 189 break; 190 default: 191 printf("%s: invalid DDR flush for arge unit: %d\n", 192 __func__, unit); 193 return; 194 } 195} 196 197static void 198ar71xx_chip_ddr_flush_ip2(void) 199{ 200 ar71xx_ddr_flush(AR71XX_WB_FLUSH_PCI); 201} 202 203static uint32_t 204ar71xx_chip_get_eth_pll(unsigned int mac, int speed) 205{ 206 return 0; 207} 208 209static void 210ar71xx_chip_init_usb_peripheral(void) 211{ 212 ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); 213 DELAY(1000); 214 215 ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY); 216 DELAY(1000); 217 218 ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG, 219 USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP | 220 USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP); 221 222 ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ, 223 (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT)); 224 225 DELAY(1000); 226} 227 228struct ar71xx_cpu_def ar71xx_chip_def = { 229 &ar71xx_chip_detect_mem_size, 230 &ar71xx_chip_detect_sys_frequency, 231 &ar71xx_chip_device_stop, 232 &ar71xx_chip_device_start, 233 &ar71xx_chip_device_stopped, 234 &ar71xx_chip_set_pll_ge, 235 &ar71xx_chip_ddr_flush_ge, 236 &ar71xx_chip_get_eth_pll, 237 &ar71xx_chip_ddr_flush_ip2, 238 &ar71xx_chip_init_usb_peripheral, 239}; 240