ar71xx_chip.c revision 211476 
1#include <sys/cdefs.h>
2__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_chip.c 211476 2010-08-19 02:03:12Z adrian $");
3
4#include <sys/param.h>
5#include <machine/cpuregs.h>
6
7#include <mips/sentry5/s5reg.h>
8
9#include "opt_ddb.h"
10
11#include <sys/param.h>
12#include <sys/conf.h>
13#include <sys/kernel.h>
14#include <sys/systm.h>
15#include <sys/bus.h>
16#include <sys/cons.h>
17#include <sys/kdb.h>
18#include <sys/reboot.h>
19
20#include <vm/vm.h>
21#include <vm/vm_page.h>
22
23#include <net/ethernet.h>
24
25#include <machine/clock.h>
26#include <machine/cpu.h>
27#include <machine/hwfunc.h>
28#include <machine/md_var.h>
29#include <machine/trap.h>
30#include <machine/vmparam.h>
31
32#include <mips/atheros/ar71xxreg.h>
33
34#include <mips/atheros/ar71xx_chip.h>
35
36#include <mips/atheros/ar71xx_cpudef.h>
37
38/* XXX these should replace the current definitions in ar71xxreg.h */
39/* XXX perhaps an ar71xx_chip.h header file? */
40#define AR71XX_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
41#define AR71XX_PLL_REG_SEC_CONFIG       AR71XX_PLL_CPU_BASE + 0x04
42#define AR71XX_PLL_REG_ETH0_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x10
43#define AR71XX_PLL_REG_ETH1_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x14
44
45#define AR71XX_PLL_DIV_SHIFT            3
46#define AR71XX_PLL_DIV_MASK             0x1f
47#define AR71XX_CPU_DIV_SHIFT            16
48#define AR71XX_CPU_DIV_MASK             0x3
49#define AR71XX_DDR_DIV_SHIFT            18
50#define AR71XX_DDR_DIV_MASK             0x3
51#define AR71XX_AHB_DIV_SHIFT            20
52#define AR71XX_AHB_DIV_MASK             0x7
53
54#define AR71XX_ETH0_PLL_SHIFT           17
55#define AR71XX_ETH1_PLL_SHIFT           19
56
57/* XXX these shouldn't be in here - this file is a per-chip file */
58/* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
59uint32_t u_ar71xx_cpu_freq;
60uint32_t u_ar71xx_ahb_freq;
61uint32_t u_ar71xx_ddr_freq;
62
63static void
64ar71xx_chip_detect_mem_size(void)
65{
66}
67
68static void
69ar71xx_chip_detect_sys_frequency(void)
70{
71	uint32_t pll;
72	uint32_t freq;
73	uint32_t div;
74
75	pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
76
77	div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
78	freq = div * AR71XX_BASE_FREQ;
79
80	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
81	u_ar71xx_cpu_freq = freq / div;
82
83	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
84	u_ar71xx_ddr_freq = freq / div;
85
86	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
87	u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
88}
89
90/*
91 * This does not lock the CPU whilst doing the work!
92 */
93static void
94ar71xx_chip_device_stop(uint32_t mask)
95{
96	uint32_t reg;
97
98	reg = ATH_READ_REG(AR71XX_RST_RESET);
99	ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
100}
101
102static void
103ar71xx_chip_device_start(uint32_t mask)
104{
105	uint32_t reg;
106
107	reg = ATH_READ_REG(AR71XX_RST_RESET);
108	ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
109}
110
111static int
112ar71xx_chip_device_stopped(uint32_t mask)
113{
114	uint32_t reg;
115
116	reg = ATH_READ_REG(AR71XX_RST_RESET);
117        return ((reg & mask) == mask);
118}
119
120static void
121ar71xx_chip_set_pll_ge0(int speed)
122{
123}
124
125static void
126ar71xx_chip_set_pll_ge1(int speed)
127{
128}
129
130static void
131ar71xx_chip_ddr_flush_ge0(void)
132{
133	ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
134}
135
136static void
137ar71xx_chip_ddr_flush_ge1(void)
138{
139	ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
140}
141
142static uint32_t
143ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
144{
145	return 0;
146}
147
148static void
149ar71xx_chip_init_usb_peripheral(void)
150{
151	ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
152	DELAY(1000);
153
154	ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
155	DELAY(1000);
156
157	ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
158	    USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
159	    USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
160
161	ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
162	    (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
163
164	DELAY(1000);
165}
166
167struct ar71xx_cpu_def ar71xx_chip_def = {
168	&ar71xx_chip_detect_mem_size,
169	&ar71xx_chip_detect_sys_frequency,
170	&ar71xx_chip_device_stop,
171	&ar71xx_chip_device_start,
172	&ar71xx_chip_device_stopped,
173	&ar71xx_chip_set_pll_ge0,
174	&ar71xx_chip_set_pll_ge1,
175	&ar71xx_chip_ddr_flush_ge0,
176	&ar71xx_chip_ddr_flush_ge1,
177	&ar71xx_chip_get_eth_pll,
178	NULL,
179	&ar71xx_chip_init_usb_peripheral,
180};
181