npx.c revision 76166
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $FreeBSD: head/sys/i386/isa/npx.c 76166 2001-05-01 08:13:21Z markm $ 36 */ 37 38#include "opt_debug_npx.h" 39#include "opt_math_emulate.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/ipl.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/malloc.h> 48#include <sys/module.h> 49#include <sys/mutex.h> 50#include <sys/mutex.h> 51#include <sys/proc.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59 60#ifndef SMP 61#include <machine/asmacros.h> 62#endif 63#include <machine/cputypes.h> 64#include <machine/frame.h> 65#include <machine/md_var.h> 66#include <machine/pcb.h> 67#include <machine/psl.h> 68#ifndef SMP 69#include <machine/clock.h> 70#endif 71#include <machine/resource.h> 72#include <machine/specialreg.h> 73#include <machine/segments.h> 74 75#ifndef SMP 76#include <i386/isa/icu.h> 77#include <i386/isa/intr_machdep.h> 78#include <i386/isa/isa.h> 79#endif 80#include <isa/isavar.h> 81 82/* 83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 84 */ 85 86/* Configuration flags. */ 87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 90#define NPX_PREFER_EMULATOR (1 << 3) 91 92#ifdef __GNUC__ 93 94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 95#define fnclex() __asm("fnclex") 96#define fninit() __asm("fninit") 97#define fnop() __asm("fnop") 98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 103#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 104 : : "n" (CR0_TS) : "ax") 105#define stop_emulating() __asm("clts") 106 107#else /* not __GNUC__ */ 108 109void fldcw __P((caddr_t addr)); 110void fnclex __P((void)); 111void fninit __P((void)); 112void fnop __P((void)); 113void fnsave __P((caddr_t addr)); 114void fnstcw __P((caddr_t addr)); 115void fnstsw __P((caddr_t addr)); 116void fp_divide_by_0 __P((void)); 117void frstor __P((caddr_t addr)); 118void start_emulating __P((void)); 119void stop_emulating __P((void)); 120 121#endif /* __GNUC__ */ 122 123typedef u_char bool_t; 124 125static int npx_attach __P((device_t dev)); 126 void npx_intr __P((void *)); 127static void npx_identify __P((driver_t *driver, device_t parent)); 128static int npx_probe __P((device_t dev)); 129static int npx_probe1 __P((device_t dev)); 130#ifdef I586_CPU 131static long timezero __P((const char *funcname, 132 void (*func)(void *buf, size_t len))); 133#endif /* I586_CPU */ 134 135int hw_float; /* XXX currently just alias for npx_exists */ 136 137SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 138 CTLFLAG_RD, &hw_float, 0, 139 "Floatingpoint instructions executed in hardware"); 140 141#ifndef SMP 142static u_int npx0_imask = 0; 143static struct gate_descriptor npx_idt_probeintr; 144static int npx_intrno; 145static volatile u_int npx_intrs_while_probing; 146static volatile u_int npx_traps_while_probing; 147#endif 148 149static bool_t npx_ex16; 150static bool_t npx_exists; 151static bool_t npx_irq13; 152static int npx_irq; /* irq number */ 153 154#ifndef SMP 155/* 156 * Special interrupt handlers. Someday intr0-intr15 will be used to count 157 * interrupts. We'll still need a special exception 16 handler. The busy 158 * latch stuff in probeintr() can be moved to npxprobe(). 159 */ 160inthand_t probeintr; 161__asm(" \n\ 162 .text \n\ 163 .p2align 2,0x90 \n\ 164 .type " __XSTRING(CNAME(probeintr)) ",@function \n\ 165" __XSTRING(CNAME(probeintr)) ": \n\ 166 ss \n\ 167 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\ 168 pushl %eax \n\ 169 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\ 170 outb %al,$0xa0 # IO_ICU2 \n\ 171 outb %al,$0x20 # IO_ICU1 \n\ 172 movb $0,%al \n\ 173 outb %al,$0xf0 # clear BUSY# latch \n\ 174 popl %eax \n\ 175 iret \n\ 176"); 177 178inthand_t probetrap; 179__asm(" \n\ 180 .text \n\ 181 .p2align 2,0x90 \n\ 182 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 183" __XSTRING(CNAME(probetrap)) ": \n\ 184 ss \n\ 185 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 186 fnclex \n\ 187 iret \n\ 188"); 189#endif /* SMP */ 190 191/* 192 * Identify routine. Create a connection point on our parent for probing. 193 */ 194static void 195npx_identify(driver, parent) 196 driver_t *driver; 197 device_t parent; 198{ 199 device_t child; 200 201 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 202 if (child == NULL) 203 panic("npx_identify"); 204} 205 206/* 207 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 208 * whether the device exists or not (XXX should be elsewhere). Set flags 209 * to tell npxattach() what to do. Modify device struct if npx doesn't 210 * need to use interrupts. Return 1 if device exists. 211 */ 212static int 213npx_probe(dev) 214 device_t dev; 215{ 216#ifdef SMP 217 218 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 219 npx_irq = 13; 220 return npx_probe1(dev); 221 222#else /* SMP */ 223 224 int result; 225 critical_t savecrit; 226 u_char save_icu1_mask; 227 u_char save_icu2_mask; 228 struct gate_descriptor save_idt_npxintr; 229 struct gate_descriptor save_idt_npxtrap; 230 /* 231 * This routine is now just a wrapper for npxprobe1(), to install 232 * special npx interrupt and trap handlers, to enable npx interrupts 233 * and to disable other interrupts. Someday isa_configure() will 234 * install suitable handlers and run with interrupts enabled so we 235 * won't need to do so much here. 236 */ 237 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0) 238 npx_irq = 13; 239 npx_intrno = NRSVIDT + npx_irq; 240 savecrit = critical_enter(); 241 save_icu1_mask = inb(IO_ICU1 + 1); 242 save_icu2_mask = inb(IO_ICU2 + 1); 243 save_idt_npxintr = idt[npx_intrno]; 244 save_idt_npxtrap = idt[16]; 245 outb(IO_ICU1 + 1, ~IRQ_SLAVE); 246 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8))); 247 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 248 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 249 npx_idt_probeintr = idt[npx_intrno]; 250 251 /* 252 * XXX This looks highly bogus, but it appears that npc_probe1 253 * needs interrupts enabled. Does this make any difference 254 * here? 255 */ 256 critical_exit(savecrit); 257 result = npx_probe1(dev); 258 savecrit = critical_enter(); 259 outb(IO_ICU1 + 1, save_icu1_mask); 260 outb(IO_ICU2 + 1, save_icu2_mask); 261 idt[npx_intrno] = save_idt_npxintr; 262 idt[16] = save_idt_npxtrap; 263 critical_exit(savecrit); 264 return (result); 265 266#endif /* SMP */ 267} 268 269static int 270npx_probe1(dev) 271 device_t dev; 272{ 273#ifndef SMP 274 u_short control; 275 u_short status; 276#endif 277 278 /* 279 * Partially reset the coprocessor, if any. Some BIOS's don't reset 280 * it after a warm boot. 281 */ 282 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 283 outb(0xf0, 0); /* clear BUSY# latch */ 284 /* 285 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 286 * instructions. We must set the CR0_MP bit and use the CR0_TS 287 * bit to control the trap, because setting the CR0_EM bit does 288 * not cause WAIT instructions to trap. It's important to trap 289 * WAIT instructions - otherwise the "wait" variants of no-wait 290 * control instructions would degenerate to the "no-wait" variants 291 * after FP context switches but work correctly otherwise. It's 292 * particularly important to trap WAITs when there is no NPX - 293 * otherwise the "wait" variants would always degenerate. 294 * 295 * Try setting CR0_NE to get correct error reporting on 486DX's. 296 * Setting it should fail or do nothing on lesser processors. 297 */ 298 load_cr0(rcr0() | CR0_MP | CR0_NE); 299 /* 300 * But don't trap while we're probing. 301 */ 302 stop_emulating(); 303 /* 304 * Finish resetting the coprocessor, if any. If there is an error 305 * pending, then we may get a bogus IRQ13, but probeintr() will handle 306 * it OK. Bogus halts have never been observed, but we enabled 307 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 308 */ 309 fninit(); 310 311#ifdef SMP 312 /* 313 * Exception 16 MUST work for SMP. 314 */ 315 npx_irq13 = 0; 316 npx_ex16 = hw_float = npx_exists = 1; 317 device_set_desc(dev, "math processor"); 318 return (0); 319 320#else /* !SMP */ 321 device_set_desc(dev, "math processor"); 322 323 /* 324 * Don't use fwait here because it might hang. 325 * Don't use fnop here because it usually hangs if there is no FPU. 326 */ 327 DELAY(1000); /* wait for any IRQ13 */ 328#ifdef DIAGNOSTIC 329 if (npx_intrs_while_probing != 0) 330 printf("fninit caused %u bogus npx interrupt(s)\n", 331 npx_intrs_while_probing); 332 if (npx_traps_while_probing != 0) 333 printf("fninit caused %u bogus npx trap(s)\n", 334 npx_traps_while_probing); 335#endif 336 /* 337 * Check for a status of mostly zero. 338 */ 339 status = 0x5a5a; 340 fnstsw(&status); 341 if ((status & 0xb8ff) == 0) { 342 /* 343 * Good, now check for a proper control word. 344 */ 345 control = 0x5a5a; 346 fnstcw(&control); 347 if ((control & 0x1f3f) == 0x033f) { 348 hw_float = npx_exists = 1; 349 /* 350 * We have an npx, now divide by 0 to see if exception 351 * 16 works. 352 */ 353 control &= ~(1 << 2); /* enable divide by 0 trap */ 354 fldcw(&control); 355 npx_traps_while_probing = npx_intrs_while_probing = 0; 356 fp_divide_by_0(); 357 if (npx_traps_while_probing != 0) { 358 /* 359 * Good, exception 16 works. 360 */ 361 npx_ex16 = 1; 362 return (0); 363 } 364 if (npx_intrs_while_probing != 0) { 365 int rid; 366 struct resource *r; 367 void *intr; 368 /* 369 * Bad, we are stuck with IRQ13. 370 */ 371 npx_irq13 = 1; 372 /* 373 * npxattach would be too late to set npx0_imask 374 */ 375 npx0_imask |= (1 << npx_irq); 376 377 /* 378 * We allocate these resources permanently, 379 * so there is no need to keep track of them. 380 */ 381 rid = 0; 382 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 383 &rid, IO_NPX, IO_NPX, 384 IO_NPXSIZE, RF_ACTIVE); 385 if (r == 0) 386 panic("npx: can't get ports"); 387 rid = 0; 388 r = bus_alloc_resource(dev, SYS_RES_IRQ, 389 &rid, npx_irq, npx_irq, 390 1, RF_ACTIVE); 391 if (r == 0) 392 panic("npx: can't get IRQ"); 393 BUS_SETUP_INTR(device_get_parent(dev), 394 dev, r, 395 INTR_TYPE_MISC | INTR_MPSAFE, 396 npx_intr, 0, &intr); 397 if (intr == 0) 398 panic("npx: can't create intr"); 399 400 return (0); 401 } 402 /* 403 * Worse, even IRQ13 is broken. Use emulator. 404 */ 405 } 406 } 407 /* 408 * Probe failed, but we want to get to npxattach to initialize the 409 * emulator and say that it has been installed. XXX handle devices 410 * that aren't really devices better. 411 */ 412 return (0); 413#endif /* SMP */ 414} 415 416/* 417 * Attach routine - announce which it is, and wire into system 418 */ 419int 420npx_attach(dev) 421 device_t dev; 422{ 423 int flags; 424 425 if (resource_int_value("npx", 0, "flags", &flags) != 0) 426 flags = 0; 427 428 if (flags) 429 device_printf(dev, "flags 0x%x ", flags); 430 if (npx_irq13) { 431 device_printf(dev, "using IRQ 13 interface\n"); 432 } else { 433#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 434 if (npx_ex16) { 435 if (!(flags & NPX_PREFER_EMULATOR)) 436 device_printf(dev, "INT 16 interface\n"); 437 else { 438 device_printf(dev, "FPU exists, but flags request " 439 "emulator\n"); 440 hw_float = npx_exists = 0; 441 } 442 } else if (npx_exists) { 443 device_printf(dev, "error reporting broken; using 387 emulator\n"); 444 hw_float = npx_exists = 0; 445 } else 446 device_printf(dev, "387 emulator\n"); 447#else 448 if (npx_ex16) { 449 device_printf(dev, "INT 16 interface\n"); 450 if (flags & NPX_PREFER_EMULATOR) { 451 device_printf(dev, "emulator requested, but none compiled " 452 "into kernel, using FPU\n"); 453 } 454 } else 455 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 456#endif 457 } 458 npxinit(__INITIAL_NPXCW__); 459 460#ifdef I586_CPU_XXX 461 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 462 timezero("i586_bzero()", i586_bzero) < 463 timezero("bzero()", bzero) * 4 / 5) { 464 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 465 bcopy_vector = i586_bcopy; 466 ovbcopy_vector = i586_bcopy; 467 } 468 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 469 bzero = i586_bzero; 470 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 471 copyin_vector = i586_copyin; 472 copyout_vector = i586_copyout; 473 } 474 } 475#endif 476 477 return (0); /* XXX unused */ 478} 479 480/* 481 * Initialize floating point unit. 482 */ 483void 484npxinit(control) 485 u_short control; 486{ 487 struct save87 dummy; 488 489 if (!npx_exists) 490 return; 491 /* 492 * fninit has the same h/w bugs as fnsave. Use the detoxified 493 * fnsave to throw away any junk in the fpu. npxsave() initializes 494 * the fpu and sets npxproc = NULL as important side effects. 495 */ 496 npxsave(&dummy); 497 stop_emulating(); 498 fldcw(&control); 499 if (PCPU_GET(curpcb) != NULL) 500 fnsave(&PCPU_GET(curpcb)->pcb_savefpu); 501 start_emulating(); 502} 503 504/* 505 * Free coprocessor (if we have it). 506 */ 507void 508npxexit(p) 509 struct proc *p; 510{ 511 512 if (p == PCPU_GET(npxproc)) 513 npxsave(&PCPU_GET(curpcb)->pcb_savefpu); 514#ifdef NPX_DEBUG 515 if (npx_exists) { 516 u_int masked_exceptions; 517 518 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 519 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 520 /* 521 * Log exceptions that would have trapped with the old 522 * control word (overflow, divide by 0, and invalid operand). 523 */ 524 if (masked_exceptions & 0x0d) 525 log(LOG_ERR, 526 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 527 p->p_pid, p->p_comm, masked_exceptions); 528 } 529#endif 530} 531 532/* 533 * The following mechanism is used to ensure that the FPE_... value 534 * that is passed as a trapcode to the signal handler of the user 535 * process does not have more than one bit set. 536 * 537 * Multiple bits may be set if the user process modifies the control 538 * word while a status word bit is already set. While this is a sign 539 * of bad coding, we have no choise than to narrow them down to one 540 * bit, since we must not send a trapcode that is not exactly one of 541 * the FPE_ macros. 542 * 543 * The mechanism has a static table with 127 entries. Each combination 544 * of the 7 FPU status word exception bits directly translates to a 545 * position in this table, where a single FPE_... value is stored. 546 * This FPE_... value stored there is considered the "most important" 547 * of the exception bits and will be sent as the signal code. The 548 * precedence of the bits is based upon Intel Document "Numerical 549 * Applications", Chapter "Special Computational Situations". 550 * 551 * The macro to choose one of these values does these steps: 1) Throw 552 * away status word bits that cannot be masked. 2) Throw away the bits 553 * currently masked in the control word, assuming the user isn't 554 * interested in them anymore. 3) Reinsert status word bit 7 (stack 555 * fault) if it is set, which cannot be masked but must be presered. 556 * 4) Use the remaining bits to point into the trapcode table. 557 * 558 * The 6 maskable bits in order of their preference, as stated in the 559 * above referenced Intel manual: 560 * 1 Invalid operation (FP_X_INV) 561 * 1a Stack underflow 562 * 1b Stack overflow 563 * 1c Operand of unsupported format 564 * 1d SNaN operand. 565 * 2 QNaN operand (not an exception, irrelavant here) 566 * 3 Any other invalid-operation not mentioned above or zero divide 567 * (FP_X_INV, FP_X_DZ) 568 * 4 Denormal operand (FP_X_DNML) 569 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 570 * 6 Inexact result (FP_X_IMP) 571 */ 572static char fpetable[128] = { 573 0, 574 FPE_FLTINV, /* 1 - INV */ 575 FPE_FLTUND, /* 2 - DNML */ 576 FPE_FLTINV, /* 3 - INV | DNML */ 577 FPE_FLTDIV, /* 4 - DZ */ 578 FPE_FLTINV, /* 5 - INV | DZ */ 579 FPE_FLTDIV, /* 6 - DNML | DZ */ 580 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 581 FPE_FLTOVF, /* 8 - OFL */ 582 FPE_FLTINV, /* 9 - INV | OFL */ 583 FPE_FLTUND, /* A - DNML | OFL */ 584 FPE_FLTINV, /* B - INV | DNML | OFL */ 585 FPE_FLTDIV, /* C - DZ | OFL */ 586 FPE_FLTINV, /* D - INV | DZ | OFL */ 587 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 588 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 589 FPE_FLTUND, /* 10 - UFL */ 590 FPE_FLTINV, /* 11 - INV | UFL */ 591 FPE_FLTUND, /* 12 - DNML | UFL */ 592 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 593 FPE_FLTDIV, /* 14 - DZ | UFL */ 594 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 595 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 596 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 597 FPE_FLTOVF, /* 18 - OFL | UFL */ 598 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 599 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 600 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 601 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 602 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 603 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 604 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 605 FPE_FLTRES, /* 20 - IMP */ 606 FPE_FLTINV, /* 21 - INV | IMP */ 607 FPE_FLTUND, /* 22 - DNML | IMP */ 608 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 609 FPE_FLTDIV, /* 24 - DZ | IMP */ 610 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 611 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 612 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 613 FPE_FLTOVF, /* 28 - OFL | IMP */ 614 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 615 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 616 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 617 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 618 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 619 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 620 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 621 FPE_FLTUND, /* 30 - UFL | IMP */ 622 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 623 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 624 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 625 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 626 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 627 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 628 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 629 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 630 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 631 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 632 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 633 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 634 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 635 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 636 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 637 FPE_FLTSUB, /* 40 - STK */ 638 FPE_FLTSUB, /* 41 - INV | STK */ 639 FPE_FLTUND, /* 42 - DNML | STK */ 640 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 641 FPE_FLTDIV, /* 44 - DZ | STK */ 642 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 643 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 644 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 645 FPE_FLTOVF, /* 48 - OFL | STK */ 646 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 647 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 648 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 649 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 650 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 651 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 652 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 653 FPE_FLTUND, /* 50 - UFL | STK */ 654 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 655 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 656 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 657 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 658 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 659 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 660 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 661 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 662 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 663 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 664 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 665 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 666 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 667 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 668 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 669 FPE_FLTRES, /* 60 - IMP | STK */ 670 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 671 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 672 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 673 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 674 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 675 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 676 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 677 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 678 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 679 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 680 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 681 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 682 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 683 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 684 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 685 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 686 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 687 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 688 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 689 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 691 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 693 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 695 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 697 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 699 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 700 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 701}; 702 703/* 704 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 705 * 706 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 707 * depend on longjmp() restoring a usable state. Restoring the state 708 * or examining it might fail if we didn't clear exceptions. 709 * 710 * The error code chosen will be one of the FPE_... macros. It will be 711 * sent as the second argument to old BSD-style signal handlers and as 712 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 713 * 714 * XXX the FP state is not preserved across signal handlers. So signal 715 * handlers cannot afford to do FP unless they preserve the state or 716 * longjmp() out. Both preserving the state and longjmp()ing may be 717 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 718 * solution for signals other than SIGFPE. 719 */ 720void 721npx_intr(dummy) 722 void *dummy; 723{ 724 int code; 725 u_short control; 726 struct intrframe *frame; 727 728 mtx_lock(&Giant); 729 if (PCPU_GET(npxproc) == NULL || !npx_exists) { 730 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 731 PCPU_GET(npxproc), curproc, npx_exists); 732 panic("npxintr from nowhere"); 733 } 734 if (PCPU_GET(npxproc) != curproc) { 735 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 736 PCPU_GET(npxproc), curproc, npx_exists); 737 panic("npxintr from non-current process"); 738 } 739 740 outb(0xf0, 0); 741 fnstsw(&PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw); 742 fnstcw(&control); 743 fnclex(); 744 745 /* 746 * Pass exception to process. 747 */ 748 frame = (struct intrframe *)&dummy; /* XXX */ 749 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 750 /* 751 * Interrupt is essentially a trap, so we can afford to call 752 * the SIGFPE handler (if any) as soon as the interrupt 753 * returns. 754 * 755 * XXX little or nothing is gained from this, and plenty is 756 * lost - the interrupt frame has to contain the trap frame 757 * (this is otherwise only necessary for the rescheduling trap 758 * in doreti, and the frame for that could easily be set up 759 * just before it is used). 760 */ 761 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 762 /* 763 * Encode the appropriate code for detailed information on 764 * this exception. 765 */ 766 code = 767 fpetable[(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 768 (PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & 0x40)]; 769 trapsignal(curproc, SIGFPE, code); 770 } else { 771 /* 772 * Nested interrupt. These losers occur when: 773 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 774 * o immediately after an fnsave or frstor of an 775 * error state. 776 * o a couple of 386 instructions after 777 * "fstpl _memvar" causes a stack overflow. 778 * These are especially nasty when combined with a 779 * trace trap. 780 * o an IRQ13 occurs at the same time as another higher- 781 * priority interrupt. 782 * 783 * Treat them like a true async interrupt. 784 */ 785 PROC_LOCK(curproc); 786 psignal(curproc, SIGFPE); 787 PROC_UNLOCK(curproc); 788 } 789 mtx_unlock(&Giant); 790} 791 792/* 793 * Implement device not available (DNA) exception 794 * 795 * It would be better to switch FP context here (if curproc != npxproc) 796 * and not necessarily for every context switch, but it is too hard to 797 * access foreign pcb's. 798 */ 799int 800npxdna() 801{ 802 critical_t s; 803 804 if (!npx_exists) 805 return (0); 806 if (PCPU_GET(npxproc) != NULL) { 807 printf("npxdna: npxproc = %p, curproc = %p\n", 808 PCPU_GET(npxproc), curproc); 809 panic("npxdna"); 810 } 811 s = critical_enter(); 812 stop_emulating(); 813 /* 814 * Record new context early in case frstor causes an IRQ13. 815 */ 816 PCPU_SET(npxproc, CURPROC); 817 PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw = 0; 818 /* 819 * The following frstor may cause an IRQ13 when the state being 820 * restored has a pending error. The error will appear to have been 821 * triggered by the current (npx) user instruction even when that 822 * instruction is a no-wait instruction that should not trigger an 823 * error (e.g., fnclex). On at least one 486 system all of the 824 * no-wait instructions are broken the same as frstor, so our 825 * treatment does not amplify the breakage. On at least one 826 * 386/Cyrix 387 system, fnclex works correctly while frstor and 827 * fnsave are broken, so our treatment breaks fnclex if it is the 828 * first FPU instruction after a context switch. 829 */ 830 frstor(&PCPU_GET(curpcb)->pcb_savefpu); 831 critical_exit(s); 832 833 return (1); 834} 835 836/* 837 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 838 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 839 * any IRQ13 to be handled immediately, and then ignore it. This routine is 840 * often called at splhigh so it must not use many system services. In 841 * particular, it's much easier to install a special handler than to 842 * guarantee that it's safe to use npxintr() and its supporting code. 843 */ 844void 845npxsave(addr) 846 struct save87 *addr; 847{ 848#ifdef SMP 849 850 stop_emulating(); 851 fnsave(addr); 852 /* fnop(); */ 853 start_emulating(); 854 PCPU_SET(npxproc, NULL); 855 856#else /* SMP */ 857 858 critical_t savecrit; 859 u_char icu1_mask; 860 u_char icu2_mask; 861 u_char old_icu1_mask; 862 u_char old_icu2_mask; 863 struct gate_descriptor save_idt_npxintr; 864 865 savecrit = critical_enter(); 866 old_icu1_mask = inb(IO_ICU1 + 1); 867 old_icu2_mask = inb(IO_ICU2 + 1); 868 save_idt_npxintr = idt[npx_intrno]; 869 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 870 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 871 idt[npx_intrno] = npx_idt_probeintr; 872 critical_exit(savecrit); 873 stop_emulating(); 874 fnsave(addr); 875 fnop(); 876 start_emulating(); 877 savecrit = critical_enter(); 878 PCPU_SET(npxproc, NULL); 879 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 880 icu2_mask = inb(IO_ICU2 + 1); 881 outb(IO_ICU1 + 1, 882 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 883 outb(IO_ICU2 + 1, 884 (icu2_mask & ~(npx0_imask >> 8)) 885 | (old_icu2_mask & (npx0_imask >> 8))); 886 idt[npx_intrno] = save_idt_npxintr; 887 critical_exit(savecrit); /* back to previous state */ 888 889#endif /* SMP */ 890} 891 892#ifdef I586_CPU 893static long 894timezero(funcname, func) 895 const char *funcname; 896 void (*func) __P((void *buf, size_t len)); 897 898{ 899 void *buf; 900#define BUFSIZE 1048576 901 long usec; 902 struct timeval finish, start; 903 904 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 905 if (buf == NULL) 906 return (BUFSIZE); 907 microtime(&start); 908 (*func)(buf, BUFSIZE); 909 microtime(&finish); 910 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 911 finish.tv_usec - start.tv_usec; 912 if (usec <= 0) 913 usec = 1; 914 if (bootverbose) 915 printf("%s bandwidth = %lu kBps\n", funcname, 916 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 917 free(buf, M_TEMP); 918 return (usec); 919} 920#endif /* I586_CPU */ 921 922static device_method_t npx_methods[] = { 923 /* Device interface */ 924 DEVMETHOD(device_identify, npx_identify), 925 DEVMETHOD(device_probe, npx_probe), 926 DEVMETHOD(device_attach, npx_attach), 927 DEVMETHOD(device_detach, bus_generic_detach), 928 DEVMETHOD(device_shutdown, bus_generic_shutdown), 929 DEVMETHOD(device_suspend, bus_generic_suspend), 930 DEVMETHOD(device_resume, bus_generic_resume), 931 932 { 0, 0 } 933}; 934 935static driver_t npx_driver = { 936 "npx", 937 npx_methods, 938 1, /* no softc */ 939}; 940 941static devclass_t npx_devclass; 942 943/* 944 * We prefer to attach to the root nexus so that the usual case (exception 16) 945 * doesn't describe the processor as being `on isa'. 946 */ 947DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 948 949/* 950 * This sucks up the legacy ISA support assignments from PNPBIOS. 951 */ 952static struct isa_pnp_id npxisa_ids[] = { 953 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 954 { 0 } 955}; 956 957static int 958npxisa_probe(device_t dev) 959{ 960 int result; 961 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 962 device_quiet(dev); 963 } 964 return(result); 965} 966 967static int 968npxisa_attach(device_t dev) 969{ 970 return (0); 971} 972 973static device_method_t npxisa_methods[] = { 974 /* Device interface */ 975 DEVMETHOD(device_probe, npxisa_probe), 976 DEVMETHOD(device_attach, npxisa_attach), 977 DEVMETHOD(device_detach, bus_generic_detach), 978 DEVMETHOD(device_shutdown, bus_generic_shutdown), 979 DEVMETHOD(device_suspend, bus_generic_suspend), 980 DEVMETHOD(device_resume, bus_generic_resume), 981 982 { 0, 0 } 983}; 984 985static driver_t npxisa_driver = { 986 "npxisa", 987 npxisa_methods, 988 1, /* no softc */ 989}; 990 991static devclass_t npxisa_devclass; 992 993DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 994 995