npx.c revision 320309
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/11/sys/i386/isa/npx.c 320309 2017-06-24 13:53:47Z kib $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58#include <vm/uma.h> 59 60#include <machine/asmacros.h> 61#include <machine/cputypes.h> 62#include <machine/frame.h> 63#include <machine/md_var.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/resource.h> 67#include <machine/specialreg.h> 68#include <machine/segments.h> 69#include <machine/ucontext.h> 70 71#include <machine/intr_machdep.h> 72 73#ifdef DEV_ISA 74#include <isa/isavar.h> 75#endif 76 77/* 78 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 79 */ 80 81#if defined(__GNUCLIKE_ASM) && !defined(lint) 82 83#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw)) 84#define fnclex() __asm __volatile("fnclex") 85#define fninit() __asm __volatile("fninit") 86#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 87#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 88#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr))) 89#define fp_divide_by_0() __asm __volatile( \ 90 "fldz; fld1; fdiv %st,%st(1); fnop") 91#define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr))) 92#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr))) 93#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 94#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr)) 95#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr))) 96 97static __inline void 98xrstor(char *addr, uint64_t mask) 99{ 100 uint32_t low, hi; 101 102 low = mask; 103 hi = mask >> 32; 104 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi)); 105} 106 107static __inline void 108xsave(char *addr, uint64_t mask) 109{ 110 uint32_t low, hi; 111 112 low = mask; 113 hi = mask >> 32; 114 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) : 115 "memory"); 116} 117 118static __inline void 119xsaveopt(char *addr, uint64_t mask) 120{ 121 uint32_t low, hi; 122 123 low = mask; 124 hi = mask >> 32; 125 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) : 126 "memory"); 127} 128#else /* !(__GNUCLIKE_ASM && !lint) */ 129 130void fldcw(u_short cw); 131void fnclex(void); 132void fninit(void); 133void fnsave(caddr_t addr); 134void fnstcw(caddr_t addr); 135void fnstsw(caddr_t addr); 136void fp_divide_by_0(void); 137void frstor(caddr_t addr); 138void fxsave(caddr_t addr); 139void fxrstor(caddr_t addr); 140void ldmxcsr(u_int csr); 141void stmxcsr(u_int *csr); 142void xrstor(char *addr, uint64_t mask); 143void xsave(char *addr, uint64_t mask); 144void xsaveopt(char *addr, uint64_t mask); 145 146#endif /* __GNUCLIKE_ASM && !lint */ 147 148#define start_emulating() load_cr0(rcr0() | CR0_TS) 149#define stop_emulating() clts() 150 151#define GET_FPU_CW(thread) \ 152 (cpu_fxsr ? \ 153 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \ 154 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw) 155#define GET_FPU_SW(thread) \ 156 (cpu_fxsr ? \ 157 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \ 158 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw) 159#define SET_FPU_CW(savefpu, value) do { \ 160 if (cpu_fxsr) \ 161 (savefpu)->sv_xmm.sv_env.en_cw = (value); \ 162 else \ 163 (savefpu)->sv_87.sv_env.en_cw = (value); \ 164} while (0) 165 166CTASSERT(sizeof(union savefpu) == 512); 167CTASSERT(sizeof(struct xstate_hdr) == 64); 168CTASSERT(sizeof(struct savefpu_ymm) == 832); 169 170/* 171 * This requirement is to make it easier for asm code to calculate 172 * offset of the fpu save area from the pcb address. FPU save area 173 * must be 64-byte aligned. 174 */ 175CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0); 176 177/* 178 * Ensure the copy of XCR0 saved in a core is contained in the padding 179 * area. 180 */ 181CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) && 182 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm)); 183 184static void fpu_clean_state(void); 185 186static void fpusave(union savefpu *); 187static void fpurstor(union savefpu *); 188 189int hw_float; 190 191SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 192 &hw_float, 0, "Floating point instructions executed in hardware"); 193 194int use_xsave; 195uint64_t xsave_mask; 196static uma_zone_t fpu_save_area_zone; 197static union savefpu *npx_initialstate; 198 199struct xsave_area_elm_descr { 200 u_int offset; 201 u_int size; 202} *xsave_area_desc; 203 204static int use_xsaveopt; 205 206static volatile u_int npx_traps_while_probing; 207 208alias_for_inthand_t probetrap; 209__asm(" \n\ 210 .text \n\ 211 .p2align 2,0x90 \n\ 212 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 213" __XSTRING(CNAME(probetrap)) ": \n\ 214 ss \n\ 215 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 216 fnclex \n\ 217 iret \n\ 218"); 219 220/* 221 * Determine if an FPU is present and how to use it. 222 */ 223static int 224npx_probe(void) 225{ 226 struct gate_descriptor save_idt_npxtrap; 227 u_short control, status; 228 229 /* 230 * Modern CPUs all have an FPU that uses the INT16 interface 231 * and provide a simple way to verify that, so handle the 232 * common case right away. 233 */ 234 if (cpu_feature & CPUID_FPU) { 235 hw_float = 1; 236 return (1); 237 } 238 239 save_idt_npxtrap = idt[IDT_MF]; 240 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 241 GSEL(GCODE_SEL, SEL_KPL)); 242 243 /* 244 * Don't trap while we're probing. 245 */ 246 stop_emulating(); 247 248 /* 249 * Finish resetting the coprocessor, if any. If there is an error 250 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 251 * it OK. Bogus halts have never been observed, but we enabled 252 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 253 */ 254 fninit(); 255 256 /* 257 * Don't use fwait here because it might hang. 258 * Don't use fnop here because it usually hangs if there is no FPU. 259 */ 260 DELAY(1000); /* wait for any IRQ13 */ 261#ifdef DIAGNOSTIC 262 if (npx_traps_while_probing != 0) 263 printf("fninit caused %u bogus npx trap(s)\n", 264 npx_traps_while_probing); 265#endif 266 /* 267 * Check for a status of mostly zero. 268 */ 269 status = 0x5a5a; 270 fnstsw(&status); 271 if ((status & 0xb8ff) == 0) { 272 /* 273 * Good, now check for a proper control word. 274 */ 275 control = 0x5a5a; 276 fnstcw(&control); 277 if ((control & 0x1f3f) == 0x033f) { 278 /* 279 * We have an npx, now divide by 0 to see if exception 280 * 16 works. 281 */ 282 control &= ~(1 << 2); /* enable divide by 0 trap */ 283 fldcw(control); 284#ifdef FPU_ERROR_BROKEN 285 /* 286 * FPU error signal doesn't work on some CPU 287 * accelerator board. 288 */ 289 hw_float = 1; 290 return (1); 291#endif 292 npx_traps_while_probing = 0; 293 fp_divide_by_0(); 294 if (npx_traps_while_probing != 0) { 295 /* 296 * Good, exception 16 works. 297 */ 298 hw_float = 1; 299 goto cleanup; 300 } 301 printf( 302 "FPU does not use exception 16 for error reporting\n"); 303 goto cleanup; 304 } 305 } 306 307 /* 308 * Probe failed. Floating point simply won't work. 309 * Notify user and disable FPU/MMX/SSE instruction execution. 310 */ 311 printf("WARNING: no FPU!\n"); 312 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : : 313 "n" (CR0_EM | CR0_MP) : "ax"); 314 315cleanup: 316 idt[IDT_MF] = save_idt_npxtrap; 317 return (hw_float); 318} 319 320/* 321 * Enable XSAVE if supported and allowed by user. 322 * Calculate the xsave_mask. 323 */ 324static void 325npxinit_bsp1(void) 326{ 327 u_int cp[4]; 328 uint64_t xsave_mask_user; 329 330 if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) { 331 use_xsave = 1; 332 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave); 333 } 334 if (!use_xsave) 335 return; 336 337 cpuid_count(0xd, 0x0, cp); 338 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 339 if ((cp[0] & xsave_mask) != xsave_mask) 340 panic("CPU0 does not support X87 or SSE: %x", cp[0]); 341 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0]; 342 xsave_mask_user = xsave_mask; 343 TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user); 344 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE; 345 xsave_mask &= xsave_mask_user; 346 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512) 347 xsave_mask &= ~XFEATURE_AVX512; 348 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX) 349 xsave_mask &= ~XFEATURE_MPX; 350 351 cpuid_count(0xd, 0x1, cp); 352 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) 353 use_xsaveopt = 1; 354} 355 356/* 357 358 * Calculate the fpu save area size. 359 */ 360static void 361npxinit_bsp2(void) 362{ 363 u_int cp[4]; 364 365 if (use_xsave) { 366 cpuid_count(0xd, 0x0, cp); 367 cpu_max_ext_state_size = cp[1]; 368 369 /* 370 * Reload the cpu_feature2, since we enabled OSXSAVE. 371 */ 372 do_cpuid(1, cp); 373 cpu_feature2 = cp[2]; 374 } else 375 cpu_max_ext_state_size = sizeof(union savefpu); 376} 377 378/* 379 * Initialize floating point unit. 380 */ 381void 382npxinit(bool bsp) 383{ 384 static union savefpu dummy; 385 register_t saveintr; 386 u_int mxcsr; 387 u_short control; 388 389 if (bsp) { 390 if (!npx_probe()) 391 return; 392 npxinit_bsp1(); 393 } 394 395 if (use_xsave) { 396 load_cr4(rcr4() | CR4_XSAVE); 397 load_xcr(XCR0, xsave_mask); 398 } 399 400 /* 401 * XCR0 shall be set up before CPU can report the save area size. 402 */ 403 if (bsp) 404 npxinit_bsp2(); 405 406 /* 407 * fninit has the same h/w bugs as fnsave. Use the detoxified 408 * fnsave to throw away any junk in the fpu. fpusave() initializes 409 * the fpu. 410 * 411 * It is too early for critical_enter() to work on AP. 412 */ 413 saveintr = intr_disable(); 414 stop_emulating(); 415 if (cpu_fxsr) 416 fninit(); 417 else 418 fnsave(&dummy); 419 control = __INITIAL_NPXCW__; 420 fldcw(control); 421 if (cpu_fxsr) { 422 mxcsr = __INITIAL_MXCSR__; 423 ldmxcsr(mxcsr); 424 } 425 start_emulating(); 426 intr_restore(saveintr); 427} 428 429/* 430 * On the boot CPU we generate a clean state that is used to 431 * initialize the floating point unit when it is first used by a 432 * process. 433 */ 434static void 435npxinitstate(void *arg __unused) 436{ 437 register_t saveintr; 438 int cp[4], i, max_ext_n; 439 440 if (!hw_float) 441 return; 442 443 npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF, 444 M_WAITOK | M_ZERO); 445 saveintr = intr_disable(); 446 stop_emulating(); 447 448 fpusave(npx_initialstate); 449 if (cpu_fxsr) { 450 if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask) 451 cpu_mxcsr_mask = 452 npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask; 453 else 454 cpu_mxcsr_mask = 0xFFBF; 455 456 /* 457 * The fninit instruction does not modify XMM 458 * registers or x87 registers (MM/ST). The fpusave 459 * call dumped the garbage contained in the registers 460 * after reset to the initial state saved. Clear XMM 461 * and x87 registers file image to make the startup 462 * program state and signal handler XMM/x87 register 463 * content predictable. 464 */ 465 bzero(npx_initialstate->sv_xmm.sv_fp, 466 sizeof(npx_initialstate->sv_xmm.sv_fp)); 467 bzero(npx_initialstate->sv_xmm.sv_xmm, 468 sizeof(npx_initialstate->sv_xmm.sv_xmm)); 469 } else 470 bzero(npx_initialstate->sv_87.sv_ac, 471 sizeof(npx_initialstate->sv_87.sv_ac)); 472 473 /* 474 * Create a table describing the layout of the CPU Extended 475 * Save Area. 476 */ 477 if (use_xsave) { 478 if (xsave_mask >> 32 != 0) 479 max_ext_n = fls(xsave_mask >> 32) + 32; 480 else 481 max_ext_n = fls(xsave_mask); 482 xsave_area_desc = malloc(max_ext_n * sizeof(struct 483 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO); 484 /* x87 state */ 485 xsave_area_desc[0].offset = 0; 486 xsave_area_desc[0].size = 160; 487 /* XMM */ 488 xsave_area_desc[1].offset = 160; 489 xsave_area_desc[1].size = 288 - 160; 490 491 for (i = 2; i < max_ext_n; i++) { 492 cpuid_count(0xd, i, cp); 493 xsave_area_desc[i].offset = cp[1]; 494 xsave_area_desc[i].size = cp[0]; 495 } 496 } 497 498 fpu_save_area_zone = uma_zcreate("FPU_save_area", 499 cpu_max_ext_state_size, NULL, NULL, NULL, NULL, 500 XSAVE_AREA_ALIGN - 1, 0); 501 502 start_emulating(); 503 intr_restore(saveintr); 504} 505SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL); 506 507/* 508 * Free coprocessor (if we have it). 509 */ 510void 511npxexit(struct thread *td) 512{ 513 514 critical_enter(); 515 if (curthread == PCPU_GET(fpcurthread)) { 516 stop_emulating(); 517 fpusave(curpcb->pcb_save); 518 start_emulating(); 519 PCPU_SET(fpcurthread, NULL); 520 } 521 critical_exit(); 522#ifdef NPX_DEBUG 523 if (hw_float) { 524 u_int masked_exceptions; 525 526 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 527 /* 528 * Log exceptions that would have trapped with the old 529 * control word (overflow, divide by 0, and invalid operand). 530 */ 531 if (masked_exceptions & 0x0d) 532 log(LOG_ERR, 533 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 534 td->td_proc->p_pid, td->td_proc->p_comm, 535 masked_exceptions); 536 } 537#endif 538} 539 540int 541npxformat(void) 542{ 543 544 if (!hw_float) 545 return (_MC_FPFMT_NODEV); 546 if (cpu_fxsr) 547 return (_MC_FPFMT_XMM); 548 return (_MC_FPFMT_387); 549} 550 551/* 552 * The following mechanism is used to ensure that the FPE_... value 553 * that is passed as a trapcode to the signal handler of the user 554 * process does not have more than one bit set. 555 * 556 * Multiple bits may be set if the user process modifies the control 557 * word while a status word bit is already set. While this is a sign 558 * of bad coding, we have no choise than to narrow them down to one 559 * bit, since we must not send a trapcode that is not exactly one of 560 * the FPE_ macros. 561 * 562 * The mechanism has a static table with 127 entries. Each combination 563 * of the 7 FPU status word exception bits directly translates to a 564 * position in this table, where a single FPE_... value is stored. 565 * This FPE_... value stored there is considered the "most important" 566 * of the exception bits and will be sent as the signal code. The 567 * precedence of the bits is based upon Intel Document "Numerical 568 * Applications", Chapter "Special Computational Situations". 569 * 570 * The macro to choose one of these values does these steps: 1) Throw 571 * away status word bits that cannot be masked. 2) Throw away the bits 572 * currently masked in the control word, assuming the user isn't 573 * interested in them anymore. 3) Reinsert status word bit 7 (stack 574 * fault) if it is set, which cannot be masked but must be presered. 575 * 4) Use the remaining bits to point into the trapcode table. 576 * 577 * The 6 maskable bits in order of their preference, as stated in the 578 * above referenced Intel manual: 579 * 1 Invalid operation (FP_X_INV) 580 * 1a Stack underflow 581 * 1b Stack overflow 582 * 1c Operand of unsupported format 583 * 1d SNaN operand. 584 * 2 QNaN operand (not an exception, irrelavant here) 585 * 3 Any other invalid-operation not mentioned above or zero divide 586 * (FP_X_INV, FP_X_DZ) 587 * 4 Denormal operand (FP_X_DNML) 588 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 589 * 6 Inexact result (FP_X_IMP) 590 */ 591static char fpetable[128] = { 592 0, 593 FPE_FLTINV, /* 1 - INV */ 594 FPE_FLTUND, /* 2 - DNML */ 595 FPE_FLTINV, /* 3 - INV | DNML */ 596 FPE_FLTDIV, /* 4 - DZ */ 597 FPE_FLTINV, /* 5 - INV | DZ */ 598 FPE_FLTDIV, /* 6 - DNML | DZ */ 599 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 600 FPE_FLTOVF, /* 8 - OFL */ 601 FPE_FLTINV, /* 9 - INV | OFL */ 602 FPE_FLTUND, /* A - DNML | OFL */ 603 FPE_FLTINV, /* B - INV | DNML | OFL */ 604 FPE_FLTDIV, /* C - DZ | OFL */ 605 FPE_FLTINV, /* D - INV | DZ | OFL */ 606 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 607 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 608 FPE_FLTUND, /* 10 - UFL */ 609 FPE_FLTINV, /* 11 - INV | UFL */ 610 FPE_FLTUND, /* 12 - DNML | UFL */ 611 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 612 FPE_FLTDIV, /* 14 - DZ | UFL */ 613 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 614 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 615 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 616 FPE_FLTOVF, /* 18 - OFL | UFL */ 617 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 618 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 619 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 620 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 621 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 622 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 623 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 624 FPE_FLTRES, /* 20 - IMP */ 625 FPE_FLTINV, /* 21 - INV | IMP */ 626 FPE_FLTUND, /* 22 - DNML | IMP */ 627 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 628 FPE_FLTDIV, /* 24 - DZ | IMP */ 629 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 630 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 631 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 632 FPE_FLTOVF, /* 28 - OFL | IMP */ 633 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 634 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 635 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 636 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 637 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 638 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 639 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 640 FPE_FLTUND, /* 30 - UFL | IMP */ 641 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 642 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 643 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 644 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 645 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 646 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 647 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 648 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 649 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 650 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 651 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 652 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 653 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 654 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 655 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 656 FPE_FLTSUB, /* 40 - STK */ 657 FPE_FLTSUB, /* 41 - INV | STK */ 658 FPE_FLTUND, /* 42 - DNML | STK */ 659 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 660 FPE_FLTDIV, /* 44 - DZ | STK */ 661 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 662 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 663 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 664 FPE_FLTOVF, /* 48 - OFL | STK */ 665 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 666 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 667 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 668 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 669 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 670 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 671 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 672 FPE_FLTUND, /* 50 - UFL | STK */ 673 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 674 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 675 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 676 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 677 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 678 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 679 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 680 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 681 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 682 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 683 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 684 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 685 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 686 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 687 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 688 FPE_FLTRES, /* 60 - IMP | STK */ 689 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 690 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 691 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 692 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 693 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 694 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 695 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 696 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 697 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 698 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 699 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 700 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 701 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 702 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 703 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 704 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 705 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 706 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 707 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 708 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 709 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 710 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 711 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 712 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 713 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 714 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 715 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 716 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 717 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 718 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 719 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 720}; 721 722/* 723 * Read the FP status and control words, then generate si_code value 724 * for SIGFPE. The error code chosen will be one of the 725 * FPE_... macros. It will be sent as the second argument to old 726 * BSD-style signal handlers and as "siginfo_t->si_code" (second 727 * argument) to SA_SIGINFO signal handlers. 728 * 729 * Some time ago, we cleared the x87 exceptions with FNCLEX there. 730 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The 731 * usermode code which understands the FPU hardware enough to enable 732 * the exceptions, can also handle clearing the exception state in the 733 * handler. The only consequence of not clearing the exception is the 734 * rethrow of the SIGFPE on return from the signal handler and 735 * reexecution of the corresponding instruction. 736 * 737 * For XMM traps, the exceptions were never cleared. 738 */ 739int 740npxtrap_x87(void) 741{ 742 u_short control, status; 743 744 if (!hw_float) { 745 printf( 746 "npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n", 747 PCPU_GET(fpcurthread), curthread, hw_float); 748 panic("npxtrap from nowhere"); 749 } 750 critical_enter(); 751 752 /* 753 * Interrupt handling (for another interrupt) may have pushed the 754 * state to memory. Fetch the relevant parts of the state from 755 * wherever they are. 756 */ 757 if (PCPU_GET(fpcurthread) != curthread) { 758 control = GET_FPU_CW(curthread); 759 status = GET_FPU_SW(curthread); 760 } else { 761 fnstcw(&control); 762 fnstsw(&status); 763 } 764 critical_exit(); 765 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 766} 767 768int 769npxtrap_sse(void) 770{ 771 u_int mxcsr; 772 773 if (!hw_float) { 774 printf( 775 "npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n", 776 PCPU_GET(fpcurthread), curthread, hw_float); 777 panic("npxtrap from nowhere"); 778 } 779 critical_enter(); 780 if (PCPU_GET(fpcurthread) != curthread) 781 mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr; 782 else 783 stmxcsr(&mxcsr); 784 critical_exit(); 785 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]); 786} 787 788/* 789 * Implement device not available (DNA) exception 790 * 791 * It would be better to switch FP context here (if curthread != fpcurthread) 792 * and not necessarily for every context switch, but it is too hard to 793 * access foreign pcb's. 794 */ 795 796static int err_count = 0; 797 798int 799npxdna(void) 800{ 801 802 if (!hw_float) 803 return (0); 804 critical_enter(); 805 if (PCPU_GET(fpcurthread) == curthread) { 806 printf("npxdna: fpcurthread == curthread %d times\n", 807 ++err_count); 808 stop_emulating(); 809 critical_exit(); 810 return (1); 811 } 812 if (PCPU_GET(fpcurthread) != NULL) { 813 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 814 PCPU_GET(fpcurthread), 815 PCPU_GET(fpcurthread)->td_proc->p_pid, 816 curthread, curthread->td_proc->p_pid); 817 panic("npxdna"); 818 } 819 stop_emulating(); 820 /* 821 * Record new context early in case frstor causes a trap. 822 */ 823 PCPU_SET(fpcurthread, curthread); 824 825 if (cpu_fxsr) 826 fpu_clean_state(); 827 828 if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) { 829 /* 830 * This is the first time this thread has used the FPU or 831 * the PCB doesn't contain a clean FPU state. Explicitly 832 * load an initial state. 833 * 834 * We prefer to restore the state from the actual save 835 * area in PCB instead of directly loading from 836 * npx_initialstate, to ignite the XSAVEOPT 837 * tracking engine. 838 */ 839 bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size); 840 fpurstor(curpcb->pcb_save); 841 if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__) 842 fldcw(curpcb->pcb_initial_npxcw); 843 curpcb->pcb_flags |= PCB_NPXINITDONE; 844 if (PCB_USER_FPU(curpcb)) 845 curpcb->pcb_flags |= PCB_NPXUSERINITDONE; 846 } else { 847 fpurstor(curpcb->pcb_save); 848 } 849 critical_exit(); 850 851 return (1); 852} 853 854/* 855 * Wrapper for fpusave() called from context switch routines. 856 * 857 * npxsave() must be called with interrupts disabled, so that it clears 858 * fpcurthread atomically with saving the state. We require callers to do the 859 * disabling, since most callers need to disable interrupts anyway to call 860 * npxsave() atomically with checking fpcurthread. 861 */ 862void 863npxsave(addr) 864 union savefpu *addr; 865{ 866 867 stop_emulating(); 868 if (use_xsaveopt) 869 xsaveopt((char *)addr, xsave_mask); 870 else 871 fpusave(addr); 872 start_emulating(); 873 PCPU_SET(fpcurthread, NULL); 874} 875 876/* 877 * Unconditionally save the current co-processor state across suspend and 878 * resume. 879 */ 880void 881npxsuspend(union savefpu *addr) 882{ 883 register_t cr0; 884 885 if (!hw_float) 886 return; 887 if (PCPU_GET(fpcurthread) == NULL) { 888 bcopy(npx_initialstate, addr, cpu_max_ext_state_size); 889 return; 890 } 891 cr0 = rcr0(); 892 stop_emulating(); 893 fpusave(addr); 894 load_cr0(cr0); 895} 896 897void 898npxresume(union savefpu *addr) 899{ 900 register_t cr0; 901 902 if (!hw_float) 903 return; 904 905 cr0 = rcr0(); 906 npxinit(false); 907 stop_emulating(); 908 fpurstor(addr); 909 load_cr0(cr0); 910} 911 912void 913npxdrop(void) 914{ 915 struct thread *td; 916 917 /* 918 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 919 * ones don't cause a panic on the next frstor. 920 */ 921 if (!cpu_fxsr) 922 fnclex(); 923 924 td = PCPU_GET(fpcurthread); 925 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread")); 926 CRITICAL_ASSERT(td); 927 PCPU_SET(fpcurthread, NULL); 928 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 929 start_emulating(); 930} 931 932/* 933 * Get the user state of the FPU into pcb->pcb_user_save without 934 * dropping ownership (if possible). It returns the FPU ownership 935 * status. 936 */ 937int 938npxgetregs(struct thread *td) 939{ 940 struct pcb *pcb; 941 uint64_t *xstate_bv, bit; 942 char *sa; 943 int max_ext_n, i; 944 int owned; 945 946 if (!hw_float) 947 return (_MC_FPOWNED_NONE); 948 949 pcb = td->td_pcb; 950 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 951 bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb), 952 cpu_max_ext_state_size); 953 SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw); 954 npxuserinited(td); 955 return (_MC_FPOWNED_PCB); 956 } 957 critical_enter(); 958 if (td == PCPU_GET(fpcurthread)) { 959 fpusave(get_pcb_user_save_pcb(pcb)); 960 if (!cpu_fxsr) 961 /* 962 * fnsave initializes the FPU and destroys whatever 963 * context it contains. Make sure the FPU owner 964 * starts with a clean state next time. 965 */ 966 npxdrop(); 967 owned = _MC_FPOWNED_FPU; 968 } else { 969 owned = _MC_FPOWNED_PCB; 970 } 971 critical_exit(); 972 if (use_xsave) { 973 /* 974 * Handle partially saved state. 975 */ 976 sa = (char *)get_pcb_user_save_pcb(pcb); 977 xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) + 978 offsetof(struct xstate_hdr, xstate_bv)); 979 if (xsave_mask >> 32 != 0) 980 max_ext_n = fls(xsave_mask >> 32) + 32; 981 else 982 max_ext_n = fls(xsave_mask); 983 for (i = 0; i < max_ext_n; i++) { 984 bit = 1ULL << i; 985 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0) 986 continue; 987 bcopy((char *)npx_initialstate + 988 xsave_area_desc[i].offset, 989 sa + xsave_area_desc[i].offset, 990 xsave_area_desc[i].size); 991 *xstate_bv |= bit; 992 } 993 } 994 return (owned); 995} 996 997void 998npxuserinited(struct thread *td) 999{ 1000 struct pcb *pcb; 1001 1002 pcb = td->td_pcb; 1003 if (PCB_USER_FPU(pcb)) 1004 pcb->pcb_flags |= PCB_NPXINITDONE; 1005 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 1006} 1007 1008int 1009npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size) 1010{ 1011 struct xstate_hdr *hdr, *ehdr; 1012 size_t len, max_len; 1013 uint64_t bv; 1014 1015 /* XXXKIB should we clear all extended state in xstate_bv instead ? */ 1016 if (xfpustate == NULL) 1017 return (0); 1018 if (!use_xsave) 1019 return (EOPNOTSUPP); 1020 1021 len = xfpustate_size; 1022 if (len < sizeof(struct xstate_hdr)) 1023 return (EINVAL); 1024 max_len = cpu_max_ext_state_size - sizeof(union savefpu); 1025 if (len > max_len) 1026 return (EINVAL); 1027 1028 ehdr = (struct xstate_hdr *)xfpustate; 1029 bv = ehdr->xstate_bv; 1030 1031 /* 1032 * Avoid #gp. 1033 */ 1034 if (bv & ~xsave_mask) 1035 return (EINVAL); 1036 1037 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1); 1038 1039 hdr->xstate_bv = bv; 1040 bcopy(xfpustate + sizeof(struct xstate_hdr), 1041 (char *)(hdr + 1), len - sizeof(struct xstate_hdr)); 1042 1043 return (0); 1044} 1045 1046int 1047npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate, 1048 size_t xfpustate_size) 1049{ 1050 struct pcb *pcb; 1051 int error; 1052 1053 if (!hw_float) 1054 return (ENXIO); 1055 1056 pcb = td->td_pcb; 1057 critical_enter(); 1058 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 1059 error = npxsetxstate(td, xfpustate, xfpustate_size); 1060 if (error != 0) { 1061 critical_exit(); 1062 return (error); 1063 } 1064 if (!cpu_fxsr) 1065 fnclex(); /* As in npxdrop(). */ 1066 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1067 fpurstor(get_pcb_user_save_td(td)); 1068 critical_exit(); 1069 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE; 1070 } else { 1071 critical_exit(); 1072 error = npxsetxstate(td, xfpustate, xfpustate_size); 1073 if (error != 0) 1074 return (error); 1075 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr)); 1076 npxuserinited(td); 1077 } 1078 return (0); 1079} 1080 1081static void 1082fpusave(addr) 1083 union savefpu *addr; 1084{ 1085 1086 if (use_xsave) 1087 xsave((char *)addr, xsave_mask); 1088 else if (cpu_fxsr) 1089 fxsave(addr); 1090 else 1091 fnsave(addr); 1092} 1093 1094static void 1095npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87) 1096{ 1097 struct env87 *penv_87; 1098 struct envxmm *penv_xmm; 1099 int i; 1100 1101 penv_87 = &sv_87->sv_env; 1102 penv_xmm = &sv_xmm->sv_env; 1103 1104 /* FPU control/status */ 1105 penv_87->en_cw = penv_xmm->en_cw; 1106 penv_87->en_sw = penv_xmm->en_sw; 1107 penv_87->en_fip = penv_xmm->en_fip; 1108 penv_87->en_fcs = penv_xmm->en_fcs; 1109 penv_87->en_opcode = penv_xmm->en_opcode; 1110 penv_87->en_foo = penv_xmm->en_foo; 1111 penv_87->en_fos = penv_xmm->en_fos; 1112 1113 /* FPU registers and tags */ 1114 penv_87->en_tw = 0xffff; 1115 for (i = 0; i < 8; ++i) { 1116 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc; 1117 if ((penv_xmm->en_tw & (1 << i)) != 0) 1118 /* zero and special are set as valid */ 1119 penv_87->en_tw &= ~(3 << i * 2); 1120 } 1121} 1122 1123void 1124npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87) 1125{ 1126 1127 bzero(sv_87, sizeof(*sv_87)); 1128 npx_fill_fpregs_xmm1(sv_xmm, sv_87); 1129} 1130 1131void 1132npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm) 1133{ 1134 struct env87 *penv_87; 1135 struct envxmm *penv_xmm; 1136 int i; 1137 1138 penv_87 = &sv_87->sv_env; 1139 penv_xmm = &sv_xmm->sv_env; 1140 1141 /* FPU control/status */ 1142 penv_xmm->en_cw = penv_87->en_cw; 1143 penv_xmm->en_sw = penv_87->en_sw; 1144 penv_xmm->en_fip = penv_87->en_fip; 1145 penv_xmm->en_fcs = penv_87->en_fcs; 1146 penv_xmm->en_opcode = penv_87->en_opcode; 1147 penv_xmm->en_foo = penv_87->en_foo; 1148 penv_xmm->en_fos = penv_87->en_fos; 1149 1150 /* 1151 * FPU registers and tags. 1152 * Abridged / Full translation (values in binary), see FXSAVE spec. 1153 * 0 11 1154 * 1 00, 01, 10 1155 */ 1156 penv_xmm->en_tw = 0; 1157 for (i = 0; i < 8; ++i) { 1158 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i]; 1159 if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2)) 1160 penv_xmm->en_tw |= 1 << i; 1161 } 1162} 1163 1164void 1165npx_get_fsave(void *addr) 1166{ 1167 struct thread *td; 1168 union savefpu *sv; 1169 1170 td = curthread; 1171 npxgetregs(td); 1172 sv = get_pcb_user_save_td(td); 1173 if (cpu_fxsr) 1174 npx_fill_fpregs_xmm1(&sv->sv_xmm, addr); 1175 else 1176 bcopy(sv, addr, sizeof(struct env87) + 1177 sizeof(struct fpacc87[8])); 1178} 1179 1180int 1181npx_set_fsave(void *addr) 1182{ 1183 union savefpu sv; 1184 int error; 1185 1186 bzero(&sv, sizeof(sv)); 1187 if (cpu_fxsr) 1188 npx_set_fpregs_xmm(addr, &sv.sv_xmm); 1189 else 1190 bcopy(addr, &sv, sizeof(struct env87) + 1191 sizeof(struct fpacc87[8])); 1192 error = npxsetregs(curthread, &sv, NULL, 0); 1193 return (error); 1194} 1195 1196/* 1197 * On AuthenticAMD processors, the fxrstor instruction does not restore 1198 * the x87's stored last instruction pointer, last data pointer, and last 1199 * opcode values, except in the rare case in which the exception summary 1200 * (ES) bit in the x87 status word is set to 1. 1201 * 1202 * In order to avoid leaking this information across processes, we clean 1203 * these values by performing a dummy load before executing fxrstor(). 1204 */ 1205static void 1206fpu_clean_state(void) 1207{ 1208 static float dummy_variable = 0.0; 1209 u_short status; 1210 1211 /* 1212 * Clear the ES bit in the x87 status word if it is currently 1213 * set, in order to avoid causing a fault in the upcoming load. 1214 */ 1215 fnstsw(&status); 1216 if (status & 0x80) 1217 fnclex(); 1218 1219 /* 1220 * Load the dummy variable into the x87 stack. This mangles 1221 * the x87 stack, but we don't care since we're about to call 1222 * fxrstor() anyway. 1223 */ 1224 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable)); 1225} 1226 1227static void 1228fpurstor(union savefpu *addr) 1229{ 1230 1231 if (use_xsave) 1232 xrstor((char *)addr, xsave_mask); 1233 else if (cpu_fxsr) 1234 fxrstor(addr); 1235 else 1236 frstor(addr); 1237} 1238 1239#ifdef DEV_ISA 1240/* 1241 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1242 */ 1243static struct isa_pnp_id npxisa_ids[] = { 1244 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1245 { 0 } 1246}; 1247 1248static int 1249npxisa_probe(device_t dev) 1250{ 1251 int result; 1252 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1253 device_quiet(dev); 1254 } 1255 return(result); 1256} 1257 1258static int 1259npxisa_attach(device_t dev) 1260{ 1261 return (0); 1262} 1263 1264static device_method_t npxisa_methods[] = { 1265 /* Device interface */ 1266 DEVMETHOD(device_probe, npxisa_probe), 1267 DEVMETHOD(device_attach, npxisa_attach), 1268 DEVMETHOD(device_detach, bus_generic_detach), 1269 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1270 DEVMETHOD(device_suspend, bus_generic_suspend), 1271 DEVMETHOD(device_resume, bus_generic_resume), 1272 1273 { 0, 0 } 1274}; 1275 1276static driver_t npxisa_driver = { 1277 "npxisa", 1278 npxisa_methods, 1279 1, /* no softc */ 1280}; 1281 1282static devclass_t npxisa_devclass; 1283 1284DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1285#ifndef PC98 1286DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1287#endif 1288#endif /* DEV_ISA */ 1289 1290static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx", 1291 "Kernel contexts for FPU state"); 1292 1293#define FPU_KERN_CTX_NPXINITDONE 0x01 1294#define FPU_KERN_CTX_DUMMY 0x02 1295#define FPU_KERN_CTX_INUSE 0x04 1296 1297struct fpu_kern_ctx { 1298 union savefpu *prev; 1299 uint32_t flags; 1300 char hwstate1[]; 1301}; 1302 1303struct fpu_kern_ctx * 1304fpu_kern_alloc_ctx(u_int flags) 1305{ 1306 struct fpu_kern_ctx *res; 1307 size_t sz; 1308 1309 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN + 1310 cpu_max_ext_state_size; 1311 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ? 1312 M_NOWAIT : M_WAITOK) | M_ZERO); 1313 return (res); 1314} 1315 1316void 1317fpu_kern_free_ctx(struct fpu_kern_ctx *ctx) 1318{ 1319 1320 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx")); 1321 /* XXXKIB clear the memory ? */ 1322 free(ctx, M_FPUKERN_CTX); 1323} 1324 1325static union savefpu * 1326fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx) 1327{ 1328 vm_offset_t p; 1329 1330 p = (vm_offset_t)&ctx->hwstate1; 1331 p = roundup2(p, XSAVE_AREA_ALIGN); 1332 return ((union savefpu *)p); 1333} 1334 1335int 1336fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1337{ 1338 struct pcb *pcb; 1339 1340 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx")); 1341 1342 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) { 1343 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE; 1344 return (0); 1345 } 1346 pcb = td->td_pcb; 1347 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == 1348 get_pcb_user_save_pcb(pcb), ("mangled pcb_save")); 1349 ctx->flags = FPU_KERN_CTX_INUSE; 1350 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0) 1351 ctx->flags |= FPU_KERN_CTX_NPXINITDONE; 1352 npxexit(td); 1353 ctx->prev = pcb->pcb_save; 1354 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx); 1355 pcb->pcb_flags |= PCB_KERNNPX; 1356 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1357 return (0); 1358} 1359 1360int 1361fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1362{ 1363 struct pcb *pcb; 1364 1365 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0, 1366 ("leaving not inuse ctx")); 1367 ctx->flags &= ~FPU_KERN_CTX_INUSE; 1368 1369 if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0) 1370 return (0); 1371 pcb = td->td_pcb; 1372 critical_enter(); 1373 if (curthread == PCPU_GET(fpcurthread)) 1374 npxdrop(); 1375 critical_exit(); 1376 pcb->pcb_save = ctx->prev; 1377 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) { 1378 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) 1379 pcb->pcb_flags |= PCB_NPXINITDONE; 1380 else 1381 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1382 pcb->pcb_flags &= ~PCB_KERNNPX; 1383 } else { 1384 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0) 1385 pcb->pcb_flags |= PCB_NPXINITDONE; 1386 else 1387 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1388 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1389 } 1390 return (0); 1391} 1392 1393int 1394fpu_kern_thread(u_int flags) 1395{ 1396 1397 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1398 ("Only kthread may use fpu_kern_thread")); 1399 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb), 1400 ("mangled pcb_save")); 1401 KASSERT(PCB_USER_FPU(curpcb), ("recursive call")); 1402 1403 curpcb->pcb_flags |= PCB_KERNNPX; 1404 return (0); 1405} 1406 1407int 1408is_fpu_kern_thread(u_int flags) 1409{ 1410 1411 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1412 return (0); 1413 return ((curpcb->pcb_flags & PCB_KERNNPX) != 0); 1414} 1415 1416/* 1417 * FPU save area alloc/free/init utility routines 1418 */ 1419union savefpu * 1420fpu_save_area_alloc(void) 1421{ 1422 1423 return (uma_zalloc(fpu_save_area_zone, 0)); 1424} 1425 1426void 1427fpu_save_area_free(union savefpu *fsa) 1428{ 1429 1430 uma_zfree(fpu_save_area_zone, fsa); 1431} 1432 1433void 1434fpu_save_area_reset(union savefpu *fsa) 1435{ 1436 1437 bcopy(npx_initialstate, fsa, cpu_max_ext_state_size); 1438} 1439