npx.c revision 27555
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $Id: npx.c,v 1.47 1997/07/17 02:09:25 peter Exp $ 36 */ 37 38#include "npx.h" 39#if NNPX > 0 40 41#include "opt_cpu.h" 42#include "opt_math_emulate.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/sysctl.h> 48#include <sys/conf.h> 49#include <sys/proc.h> 50#ifdef NPX_DEBUG 51#include <sys/syslog.h> 52#endif 53#include <sys/signalvar.h> 54 55#include <machine/asmacros.h> 56#include <machine/cpu.h> 57#include <machine/ipl.h> 58#include <machine/md_var.h> 59#include <machine/pcb.h> 60#include <machine/clock.h> 61#include <machine/specialreg.h> 62#if defined(APIC_IO) 63#include <machine/smp.h> 64#include <machine/apic.h> 65#include <machine/mpapic.h> 66#endif /* APIC_IO */ 67 68#include <i386/isa/icu.h> 69#include <i386/isa/isa_device.h> 70#include <i386/isa/intr_machdep.h> 71#include <i386/isa/isa.h> 72 73/* 74 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 75 */ 76 77/* Configuration flags. */ 78#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 79#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 80#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 81 82/* XXX - should be in header file. */ 83extern void (*bcopy_vector) __P((const void *from, void *to, size_t len)); 84extern void (*ovbcopy_vector) __P((const void *from, void *to, size_t len)); 85extern int (*copyin_vector) __P((const void *udaddr, void *kaddr, size_t len)); 86extern int (*copyout_vector) __P((const void *kaddr, void *udaddr, size_t len)); 87 88void i586_bcopy __P((const void *from, void *to, size_t len)); 89void i586_bzero __P((void *buf, size_t len)); 90int i586_copyin __P((const void *udaddr, void *kaddr, size_t len)); 91int i586_copyout __P((const void *kaddr, void *udaddr, size_t len)); 92 93#ifdef __GNUC__ 94 95#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 96#define fnclex() __asm("fnclex") 97#define fninit() __asm("fninit") 98#define fnop() __asm("fnop") 99#define fnsave(addr) __asm("fnsave %0" : "=m" (*(addr))) 100#define fnstcw(addr) __asm("fnstcw %0" : "=m" (*(addr))) 101#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*(addr))) 102#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 103#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 104#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 105 : : "n" (CR0_TS) : "ax") 106#define stop_emulating() __asm("clts") 107 108#else /* not __GNUC__ */ 109 110void fldcw __P((caddr_t addr)); 111void fnclex __P((void)); 112void fninit __P((void)); 113void fnop __P((void)); 114void fnsave __P((caddr_t addr)); 115void fnstcw __P((caddr_t addr)); 116void fnstsw __P((caddr_t addr)); 117void fp_divide_by_0 __P((void)); 118void frstor __P((caddr_t addr)); 119void start_emulating __P((void)); 120void stop_emulating __P((void)); 121 122#endif /* __GNUC__ */ 123 124typedef u_char bool_t; 125 126static int npxattach __P((struct isa_device *dvp)); 127static int npxprobe __P((struct isa_device *dvp)); 128static int npxprobe1 __P((struct isa_device *dvp)); 129 130struct isa_driver npxdriver = { 131 npxprobe, npxattach, "npx", 132}; 133 134int hw_float; /* XXX currently just alias for npx_exists */ 135 136SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 137 CTLFLAG_RD, &hw_float, 0, 138 "Floatingpoint instructions executed in hardware"); 139 140static u_int npx0_imask = SWI_CLOCK_MASK; 141 142#ifndef SMP /* XXX per-cpu on smp */ 143struct proc *npxproc; 144#endif 145 146static bool_t npx_ex16; 147static bool_t npx_exists; 148static struct gate_descriptor npx_idt_probeintr; 149static int npx_intrno; 150static volatile u_int npx_intrs_while_probing; 151static bool_t npx_irq13; 152static volatile u_int npx_traps_while_probing; 153 154/* 155 * Special interrupt handlers. Someday intr0-intr15 will be used to count 156 * interrupts. We'll still need a special exception 16 handler. The busy 157 * latch stuff in probeintr() can be moved to npxprobe(). 158 */ 159inthand_t probeintr; 160 161#if defined(APIC_IO) 162 163asm 164(" 165 .text 166 .p2align 2,0x90 167" __XSTRING(CNAME(probeintr)) ": 168 ss 169 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " 170 pushl %eax 171 movl $lapic_eoi,%eax # EOI to local APIC 172 movl $0,(%eax) # movl $0, APIC_EOI(%eax) 173 movb $0,%al 174 outb %al,$0xf0 # clear BUSY# latch 175 popl %eax 176 iret 177"); 178 179#else 180 181asm 182(" 183 .text 184 .p2align 2,0x90 185" __XSTRING(CNAME(probeintr)) ": 186 ss 187 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " 188 pushl %eax 189 movb $0x20,%al # EOI (asm in strings loses cpp features) 190 outb %al,$0xa0 # IO_ICU2 191 outb %al,$0x20 # IO_ICU1 192 movb $0,%al 193 outb %al,$0xf0 # clear BUSY# latch 194 popl %eax 195 iret 196"); 197 198#endif /* APIC_IO */ 199 200inthand_t probetrap; 201asm 202(" 203 .text 204 .p2align 2,0x90 205" __XSTRING(CNAME(probetrap)) ": 206 ss 207 incl " __XSTRING(CNAME(npx_traps_while_probing)) " 208 fnclex 209 iret 210"); 211 212/* 213 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 214 * whether the device exists or not (XXX should be elsewhere). Set flags 215 * to tell npxattach() what to do. Modify device struct if npx doesn't 216 * need to use interrupts. Return 1 if device exists. 217 */ 218static int 219npxprobe(dvp) 220 struct isa_device *dvp; 221{ 222 int result; 223 u_long save_eflags; 224#if defined(APIC_IO) 225 u_int save_apic_mask; 226#else 227 u_char save_icu1_mask; 228 u_char save_icu2_mask; 229#endif /* APIC_IO */ 230 struct gate_descriptor save_idt_npxintr; 231 struct gate_descriptor save_idt_npxtrap; 232 /* 233 * This routine is now just a wrapper for npxprobe1(), to install 234 * special npx interrupt and trap handlers, to enable npx interrupts 235 * and to disable other interrupts. Someday isa_configure() will 236 * install suitable handlers and run with interrupts enabled so we 237 * won't need to do so much here. 238 */ 239 npx_intrno = NRSVIDT + ffs(dvp->id_irq) - 1; 240 save_eflags = read_eflags(); 241 disable_intr(); 242#if defined(APIC_IO) 243 save_apic_mask = INTRGET(); 244#else 245 save_icu1_mask = inb(IO_ICU1 + 1); 246 save_icu2_mask = inb(IO_ICU2 + 1); 247#endif /* APIC_IO */ 248 save_idt_npxintr = idt[npx_intrno]; 249 save_idt_npxtrap = idt[16]; 250#if defined(APIC_IO) 251 INTRSET( ~dvp->id_irq ); 252#else 253 outb(IO_ICU1 + 1, ~(IRQ_SLAVE | dvp->id_irq)); 254 outb(IO_ICU2 + 1, ~(dvp->id_irq >> 8)); 255#endif /* APIC_IO */ 256 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 257 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 258 npx_idt_probeintr = idt[npx_intrno]; 259 enable_intr(); 260 result = npxprobe1(dvp); 261 disable_intr(); 262#if defined(APIC_IO) 263 INTRSET( save_apic_mask ); 264#else 265 outb(IO_ICU1 + 1, save_icu1_mask); 266 outb(IO_ICU2 + 1, save_icu2_mask); 267#endif /* APIC_IO */ 268 idt[npx_intrno] = save_idt_npxintr; 269 idt[16] = save_idt_npxtrap; 270 write_eflags(save_eflags); 271 return (result); 272} 273 274static int 275npxprobe1(dvp) 276 struct isa_device *dvp; 277{ 278 u_short control; 279 u_short status; 280 281 /* 282 * Partially reset the coprocessor, if any. Some BIOS's don't reset 283 * it after a warm boot. 284 */ 285 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 286 outb(0xf0, 0); /* clear BUSY# latch */ 287 /* 288 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 289 * instructions. We must set the CR0_MP bit and use the CR0_TS 290 * bit to control the trap, because setting the CR0_EM bit does 291 * not cause WAIT instructions to trap. It's important to trap 292 * WAIT instructions - otherwise the "wait" variants of no-wait 293 * control instructions would degenerate to the "no-wait" variants 294 * after FP context switches but work correctly otherwise. It's 295 * particularly important to trap WAITs when there is no NPX - 296 * otherwise the "wait" variants would always degenerate. 297 * 298 * Try setting CR0_NE to get correct error reporting on 486DX's. 299 * Setting it should fail or do nothing on lesser processors. 300 */ 301 load_cr0(rcr0() | CR0_MP | CR0_NE); 302 /* 303 * But don't trap while we're probing. 304 */ 305 stop_emulating(); 306 /* 307 * Finish resetting the coprocessor, if any. If there is an error 308 * pending, then we may get a bogus IRQ13, but probeintr() will handle 309 * it OK. Bogus halts have never been observed, but we enabled 310 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 311 */ 312 fninit(); 313 /* 314 * Don't use fwait here because it might hang. 315 * Don't use fnop here because it usually hangs if there is no FPU. 316 */ 317 DELAY(1000); /* wait for any IRQ13 */ 318#ifdef DIAGNOSTIC 319 if (npx_intrs_while_probing != 0) 320 printf("fninit caused %u bogus npx interrupt(s)\n", 321 npx_intrs_while_probing); 322 if (npx_traps_while_probing != 0) 323 printf("fninit caused %u bogus npx trap(s)\n", 324 npx_traps_while_probing); 325#endif 326 /* 327 * Check for a status of mostly zero. 328 */ 329 status = 0x5a5a; 330 fnstsw(&status); 331 if ((status & 0xb8ff) == 0) { 332 /* 333 * Good, now check for a proper control word. 334 */ 335 control = 0x5a5a; 336 fnstcw(&control); 337 if ((control & 0x1f3f) == 0x033f) { 338 hw_float = npx_exists = 1; 339 /* 340 * We have an npx, now divide by 0 to see if exception 341 * 16 works. 342 */ 343 control &= ~(1 << 2); /* enable divide by 0 trap */ 344 fldcw(&control); 345 npx_traps_while_probing = npx_intrs_while_probing = 0; 346 fp_divide_by_0(); 347 if (npx_traps_while_probing != 0) { 348 /* 349 * Good, exception 16 works. 350 */ 351 npx_ex16 = 1; 352 dvp->id_irq = 0; /* zap the interrupt */ 353 /* 354 * special return value to flag that we do not 355 * actually use any I/O registers 356 */ 357 return (-1); 358 } 359 if (npx_intrs_while_probing != 0) { 360 /* 361 * Bad, we are stuck with IRQ13. 362 */ 363 npx_irq13 = 1; 364 /* 365 * npxattach would be too late to set npx0_imask. 366 */ 367 npx0_imask |= dvp->id_irq; 368 return (IO_NPXSIZE); 369 } 370 /* 371 * Worse, even IRQ13 is broken. Use emulator. 372 */ 373 } 374 } 375 /* 376 * Probe failed, but we want to get to npxattach to initialize the 377 * emulator and say that it has been installed. XXX handle devices 378 * that aren't really devices better. 379 */ 380 dvp->id_irq = 0; 381 /* 382 * special return value to flag that we do not 383 * actually use any I/O registers 384 */ 385 return (-1); 386} 387 388/* 389 * Attach routine - announce which it is, and wire into system 390 */ 391int 392npxattach(dvp) 393 struct isa_device *dvp; 394{ 395 /* The caller has printed "irq 13" for the npx_irq13 case. */ 396 if (!npx_irq13) { 397 printf("npx%d: ", dvp->id_unit); 398 if (npx_ex16) 399 printf("INT 16 interface\n"); 400#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 401 else if (npx_exists) { 402 printf("error reporting broken; using 387 emulator\n"); 403 hw_float = npx_exists = 0; 404 } else 405 printf("387 emulator\n"); 406#else 407 else 408 printf("no 387 emulator in kernel!\n"); 409#endif 410 } 411 npxinit(__INITIAL_NPXCW__); 412 413#if defined(I586_CPU) 414 if (cpu_class == CPUCLASS_586 && npx_ex16) { 415 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 416 bcopy_vector = i586_bcopy; 417 ovbcopy_vector = i586_bcopy; 418 } 419 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 420 bzero = i586_bzero; 421 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 422 copyin_vector = i586_copyin; 423 copyout_vector = i586_copyout; 424 } 425 } 426#endif 427 428 return (1); /* XXX unused */ 429} 430 431/* 432 * Initialize floating point unit. 433 */ 434void 435npxinit(control) 436 u_short control; 437{ 438 struct save87 dummy; 439 440 if (!npx_exists) 441 return; 442 /* 443 * fninit has the same h/w bugs as fnsave. Use the detoxified 444 * fnsave to throw away any junk in the fpu. npxsave() initializes 445 * the fpu and sets npxproc = NULL as important side effects. 446 */ 447 npxsave(&dummy); 448 stop_emulating(); 449 fldcw(&control); 450 if (curpcb != NULL) 451 fnsave(&curpcb->pcb_savefpu); 452 start_emulating(); 453} 454 455/* 456 * Free coprocessor (if we have it). 457 */ 458void 459npxexit(p) 460 struct proc *p; 461{ 462 463 if (p == npxproc) 464 npxsave(&curpcb->pcb_savefpu); 465#ifdef NPX_DEBUG 466 if (npx_exists) { 467 u_int masked_exceptions; 468 469 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 470 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 471 /* 472 * Log exceptions that would have trapped with the old 473 * control word (overflow, divide by 0, and invalid operand). 474 */ 475 if (masked_exceptions & 0x0d) 476 log(LOG_ERR, 477 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 478 p->p_pid, p->p_comm, masked_exceptions); 479 } 480#endif 481} 482 483/* 484 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 485 * 486 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 487 * depend on longjmp() restoring a usable state. Restoring the state 488 * or examining it might fail if we didn't clear exceptions. 489 * 490 * XXX there is no standard way to tell SIGFPE handlers about the error 491 * state. The old interface: 492 * 493 * void handler(int sig, int code, struct sigcontext *scp); 494 * 495 * is broken because it is non-ANSI and because the FP state is not in 496 * struct sigcontext. 497 * 498 * XXX the FP state is not preserved across signal handlers. So signal 499 * handlers cannot afford to do FP unless they preserve the state or 500 * longjmp() out. Both preserving the state and longjmp()ing may be 501 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 502 * solution for signals other than SIGFPE. 503 */ 504void 505npxintr(unit) 506 int unit; 507{ 508 int code; 509 struct intrframe *frame; 510 511 if (npxproc == NULL || !npx_exists) { 512 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 513 npxproc, curproc, npx_exists); 514 panic("npxintr from nowhere"); 515 } 516 if (npxproc != curproc) { 517 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 518 npxproc, curproc, npx_exists); 519 panic("npxintr from non-current process"); 520 } 521 522 outb(0xf0, 0); 523 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 524 fnclex(); 525 fnop(); 526 527 /* 528 * Pass exception to process. 529 */ 530 frame = (struct intrframe *)&unit; /* XXX */ 531 if (ISPL(frame->if_cs) == SEL_UPL) { 532 /* 533 * Interrupt is essentially a trap, so we can afford to call 534 * the SIGFPE handler (if any) as soon as the interrupt 535 * returns. 536 * 537 * XXX little or nothing is gained from this, and plenty is 538 * lost - the interrupt frame has to contain the trap frame 539 * (this is otherwise only necessary for the rescheduling trap 540 * in doreti, and the frame for that could easily be set up 541 * just before it is used). 542 */ 543 curproc->p_md.md_regs = (struct trapframe *)&frame->if_es; 544#ifdef notyet 545 /* 546 * Encode the appropriate code for detailed information on 547 * this exception. 548 */ 549 code = XXX_ENCODE(curpcb->pcb_savefpu.sv_ex_sw); 550#else 551 code = 0; /* XXX */ 552#endif 553 trapsignal(curproc, SIGFPE, code); 554 } else { 555 /* 556 * Nested interrupt. These losers occur when: 557 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 558 * o immediately after an fnsave or frstor of an 559 * error state. 560 * o a couple of 386 instructions after 561 * "fstpl _memvar" causes a stack overflow. 562 * These are especially nasty when combined with a 563 * trace trap. 564 * o an IRQ13 occurs at the same time as another higher- 565 * priority interrupt. 566 * 567 * Treat them like a true async interrupt. 568 */ 569 psignal(curproc, SIGFPE); 570 } 571} 572 573/* 574 * Implement device not available (DNA) exception 575 * 576 * It would be better to switch FP context here (if curproc != npxproc) 577 * and not necessarily for every context switch, but it is too hard to 578 * access foreign pcb's. 579 */ 580int 581npxdna() 582{ 583 if (!npx_exists) 584 return (0); 585 if (npxproc != NULL) { 586 printf("npxdna: npxproc = %p, curproc = %p\n", 587 npxproc, curproc); 588 panic("npxdna"); 589 } 590 stop_emulating(); 591 /* 592 * Record new context early in case frstor causes an IRQ13. 593 */ 594 npxproc = curproc; 595 curpcb->pcb_savefpu.sv_ex_sw = 0; 596 /* 597 * The following frstor may cause an IRQ13 when the state being 598 * restored has a pending error. The error will appear to have been 599 * triggered by the current (npx) user instruction even when that 600 * instruction is a no-wait instruction that should not trigger an 601 * error (e.g., fnclex). On at least one 486 system all of the 602 * no-wait instructions are broken the same as frstor, so our 603 * treatment does not amplify the breakage. On at least one 604 * 386/Cyrix 387 system, fnclex works correctly while frstor and 605 * fnsave are broken, so our treatment breaks fnclex if it is the 606 * first FPU instruction after a context switch. 607 */ 608 frstor(&curpcb->pcb_savefpu); 609 610 return (1); 611} 612 613/* 614 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 615 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 616 * any IRQ13 to be handled immediately, and then ignore it. This routine is 617 * often called at splhigh so it must not use many system services. In 618 * particular, it's much easier to install a special handler than to 619 * guarantee that it's safe to use npxintr() and its supporting code. 620 */ 621void 622npxsave(addr) 623 struct save87 *addr; 624{ 625#if defined(APIC_IO) 626 u_int apic_mask; 627 u_int old_apic_mask; 628#else 629 u_char icu1_mask; 630 u_char icu2_mask; 631 u_char old_icu1_mask; 632 u_char old_icu2_mask; 633#endif /* APIC_IO */ 634 struct gate_descriptor save_idt_npxintr; 635 636 disable_intr(); 637#if defined(APIC_IO) 638 old_apic_mask = INTRGET(); 639#else 640 old_icu1_mask = inb(IO_ICU1 + 1); 641 old_icu2_mask = inb(IO_ICU2 + 1); 642#endif /* APIC_IO */ 643 save_idt_npxintr = idt[npx_intrno]; 644#if defined(APIC_IO) 645 /** FIXME: try clrIoApicMaskBit( npx0_imask ); */ 646 INTRSET( old_apic_mask & ~(npx0_imask & 0xffff) ); 647#else 648 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 649 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 650#endif /* APIC_IO */ 651 idt[npx_intrno] = npx_idt_probeintr; 652 enable_intr(); 653 stop_emulating(); 654 fnsave(addr); 655 fnop(); 656 start_emulating(); 657 npxproc = NULL; 658 disable_intr(); 659#if defined(APIC_IO) 660 apic_mask = INTRGET(); /* masks may have changed */ 661 INTRSET( (apic_mask & ~(npx0_imask & 0xffff)) | 662 (old_apic_mask & (npx0_imask & 0xffff))); 663#else 664 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 665 icu2_mask = inb(IO_ICU2 + 1); 666 outb(IO_ICU1 + 1, 667 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 668 outb(IO_ICU2 + 1, 669 (icu2_mask & ~(npx0_imask >> 8)) 670 | (old_icu2_mask & (npx0_imask >> 8))); 671#endif /* APIC_IO */ 672 idt[npx_intrno] = save_idt_npxintr; 673 enable_intr(); /* back to usual state */ 674} 675 676#endif /* NNPX > 0 */ 677