npx.c revision 27462
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 * $Id: npx.c,v 1.46 1997/06/22 16:04:06 peter Exp $ 36 */ 37 38#include "npx.h" 39#if NNPX > 0 40 41#include "opt_cpu.h" 42#include "opt_math_emulate.h" 43#include "opt_smp.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/kernel.h> 48#include <sys/sysctl.h> 49#include <sys/conf.h> 50#include <sys/file.h> 51#include <sys/proc.h> 52#ifdef NPX_DEBUG 53#include <sys/syslog.h> 54#endif 55#include <sys/signalvar.h> 56 57#include <machine/asmacros.h> 58#include <machine/cpu.h> 59#include <machine/ipl.h> 60#include <machine/md_var.h> 61#include <machine/pcb.h> 62#include <machine/trap.h> 63#include <machine/clock.h> 64#include <machine/specialreg.h> 65#if defined(APIC_IO) 66#include <machine/smp.h> 67#include <machine/apic.h> 68#include <machine/mpapic.h> 69#endif /* APIC_IO */ 70 71#include <i386/isa/icu.h> 72#include <i386/isa/isa_device.h> 73#include <i386/isa/intr_machdep.h> 74#include <i386/isa/isa.h> 75 76/* 77 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 78 */ 79 80/* Configuration flags. */ 81#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 82#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 83#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 84 85/* XXX - should be in header file. */ 86extern void (*bcopy_vector) __P((const void *from, void *to, size_t len)); 87extern void (*ovbcopy_vector) __P((const void *from, void *to, size_t len)); 88extern int (*copyin_vector) __P((const void *udaddr, void *kaddr, size_t len)); 89extern int (*copyout_vector) __P((const void *kaddr, void *udaddr, size_t len)); 90 91void i586_bcopy __P((const void *from, void *to, size_t len)); 92void i586_bzero __P((void *buf, size_t len)); 93int i586_copyin __P((const void *udaddr, void *kaddr, size_t len)); 94int i586_copyout __P((const void *kaddr, void *udaddr, size_t len)); 95 96#ifdef __GNUC__ 97 98#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 99#define fnclex() __asm("fnclex") 100#define fninit() __asm("fninit") 101#define fnop() __asm("fnop") 102#define fnsave(addr) __asm("fnsave %0" : "=m" (*(addr))) 103#define fnstcw(addr) __asm("fnstcw %0" : "=m" (*(addr))) 104#define fnstsw(addr) __asm("fnstsw %0" : "=m" (*(addr))) 105#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 106#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 108 : : "n" (CR0_TS) : "ax") 109#define stop_emulating() __asm("clts") 110 111#else /* not __GNUC__ */ 112 113void fldcw __P((caddr_t addr)); 114void fnclex __P((void)); 115void fninit __P((void)); 116void fnop __P((void)); 117void fnsave __P((caddr_t addr)); 118void fnstcw __P((caddr_t addr)); 119void fnstsw __P((caddr_t addr)); 120void fp_divide_by_0 __P((void)); 121void frstor __P((caddr_t addr)); 122void start_emulating __P((void)); 123void stop_emulating __P((void)); 124 125#endif /* __GNUC__ */ 126 127typedef u_char bool_t; 128 129static int npxattach __P((struct isa_device *dvp)); 130static int npxprobe __P((struct isa_device *dvp)); 131static int npxprobe1 __P((struct isa_device *dvp)); 132 133struct isa_driver npxdriver = { 134 npxprobe, npxattach, "npx", 135}; 136 137int hw_float; /* XXX currently just alias for npx_exists */ 138 139SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 140 CTLFLAG_RD, &hw_float, 0, 141 "Floatingpoint instructions executed in hardware"); 142 143static u_int npx0_imask = SWI_CLOCK_MASK; 144 145#ifndef SMP /* XXX per-cpu on smp */ 146struct proc *npxproc; 147#endif 148 149static bool_t npx_ex16; 150static bool_t npx_exists; 151static struct gate_descriptor npx_idt_probeintr; 152static int npx_intrno; 153static volatile u_int npx_intrs_while_probing; 154static bool_t npx_irq13; 155static volatile u_int npx_traps_while_probing; 156 157/* 158 * Special interrupt handlers. Someday intr0-intr15 will be used to count 159 * interrupts. We'll still need a special exception 16 handler. The busy 160 * latch stuff in probeintr() can be moved to npxprobe(). 161 */ 162inthand_t probeintr; 163 164#if defined(APIC_IO) 165 166asm 167(" 168 .text 169 .p2align 2,0x90 170" __XSTRING(CNAME(probeintr)) ": 171 ss 172 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " 173 pushl %eax 174 movl $lapic_eoi,%eax # EOI to local APIC 175 movl $0,(%eax) # movl $0, APIC_EOI(%eax) 176 movb $0,%al 177 outb %al,$0xf0 # clear BUSY# latch 178 popl %eax 179 iret 180"); 181 182#else 183 184asm 185(" 186 .text 187 .p2align 2,0x90 188" __XSTRING(CNAME(probeintr)) ": 189 ss 190 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " 191 pushl %eax 192 movb $0x20,%al # EOI (asm in strings loses cpp features) 193 outb %al,$0xa0 # IO_ICU2 194 outb %al,$0x20 # IO_ICU1 195 movb $0,%al 196 outb %al,$0xf0 # clear BUSY# latch 197 popl %eax 198 iret 199"); 200 201#endif /* APIC_IO */ 202 203inthand_t probetrap; 204asm 205(" 206 .text 207 .p2align 2,0x90 208" __XSTRING(CNAME(probetrap)) ": 209 ss 210 incl " __XSTRING(CNAME(npx_traps_while_probing)) " 211 fnclex 212 iret 213"); 214 215/* 216 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 217 * whether the device exists or not (XXX should be elsewhere). Set flags 218 * to tell npxattach() what to do. Modify device struct if npx doesn't 219 * need to use interrupts. Return 1 if device exists. 220 */ 221static int 222npxprobe(dvp) 223 struct isa_device *dvp; 224{ 225 int result; 226 u_long save_eflags; 227#if defined(APIC_IO) 228 u_int save_apic_mask; 229#else 230 u_char save_icu1_mask; 231 u_char save_icu2_mask; 232#endif /* APIC_IO */ 233 struct gate_descriptor save_idt_npxintr; 234 struct gate_descriptor save_idt_npxtrap; 235 /* 236 * This routine is now just a wrapper for npxprobe1(), to install 237 * special npx interrupt and trap handlers, to enable npx interrupts 238 * and to disable other interrupts. Someday isa_configure() will 239 * install suitable handlers and run with interrupts enabled so we 240 * won't need to do so much here. 241 */ 242 npx_intrno = NRSVIDT + ffs(dvp->id_irq) - 1; 243 save_eflags = read_eflags(); 244 disable_intr(); 245#if defined(APIC_IO) 246 save_apic_mask = INTRGET(); 247#else 248 save_icu1_mask = inb(IO_ICU1 + 1); 249 save_icu2_mask = inb(IO_ICU2 + 1); 250#endif /* APIC_IO */ 251 save_idt_npxintr = idt[npx_intrno]; 252 save_idt_npxtrap = idt[16]; 253#if defined(APIC_IO) 254 INTRSET( ~dvp->id_irq ); 255#else 256 outb(IO_ICU1 + 1, ~(IRQ_SLAVE | dvp->id_irq)); 257 outb(IO_ICU2 + 1, ~(dvp->id_irq >> 8)); 258#endif /* APIC_IO */ 259 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 260 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 261 npx_idt_probeintr = idt[npx_intrno]; 262 enable_intr(); 263 result = npxprobe1(dvp); 264 disable_intr(); 265#if defined(APIC_IO) 266 INTRSET( save_apic_mask ); 267#else 268 outb(IO_ICU1 + 1, save_icu1_mask); 269 outb(IO_ICU2 + 1, save_icu2_mask); 270#endif /* APIC_IO */ 271 idt[npx_intrno] = save_idt_npxintr; 272 idt[16] = save_idt_npxtrap; 273 write_eflags(save_eflags); 274 return (result); 275} 276 277static int 278npxprobe1(dvp) 279 struct isa_device *dvp; 280{ 281 u_short control; 282 u_short status; 283 284 /* 285 * Partially reset the coprocessor, if any. Some BIOS's don't reset 286 * it after a warm boot. 287 */ 288 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 289 outb(0xf0, 0); /* clear BUSY# latch */ 290 /* 291 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 292 * instructions. We must set the CR0_MP bit and use the CR0_TS 293 * bit to control the trap, because setting the CR0_EM bit does 294 * not cause WAIT instructions to trap. It's important to trap 295 * WAIT instructions - otherwise the "wait" variants of no-wait 296 * control instructions would degenerate to the "no-wait" variants 297 * after FP context switches but work correctly otherwise. It's 298 * particularly important to trap WAITs when there is no NPX - 299 * otherwise the "wait" variants would always degenerate. 300 * 301 * Try setting CR0_NE to get correct error reporting on 486DX's. 302 * Setting it should fail or do nothing on lesser processors. 303 */ 304 load_cr0(rcr0() | CR0_MP | CR0_NE); 305 /* 306 * But don't trap while we're probing. 307 */ 308 stop_emulating(); 309 /* 310 * Finish resetting the coprocessor, if any. If there is an error 311 * pending, then we may get a bogus IRQ13, but probeintr() will handle 312 * it OK. Bogus halts have never been observed, but we enabled 313 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 314 */ 315 fninit(); 316 /* 317 * Don't use fwait here because it might hang. 318 * Don't use fnop here because it usually hangs if there is no FPU. 319 */ 320 DELAY(1000); /* wait for any IRQ13 */ 321#ifdef DIAGNOSTIC 322 if (npx_intrs_while_probing != 0) 323 printf("fninit caused %u bogus npx interrupt(s)\n", 324 npx_intrs_while_probing); 325 if (npx_traps_while_probing != 0) 326 printf("fninit caused %u bogus npx trap(s)\n", 327 npx_traps_while_probing); 328#endif 329 /* 330 * Check for a status of mostly zero. 331 */ 332 status = 0x5a5a; 333 fnstsw(&status); 334 if ((status & 0xb8ff) == 0) { 335 /* 336 * Good, now check for a proper control word. 337 */ 338 control = 0x5a5a; 339 fnstcw(&control); 340 if ((control & 0x1f3f) == 0x033f) { 341 hw_float = npx_exists = 1; 342 /* 343 * We have an npx, now divide by 0 to see if exception 344 * 16 works. 345 */ 346 control &= ~(1 << 2); /* enable divide by 0 trap */ 347 fldcw(&control); 348 npx_traps_while_probing = npx_intrs_while_probing = 0; 349 fp_divide_by_0(); 350 if (npx_traps_while_probing != 0) { 351 /* 352 * Good, exception 16 works. 353 */ 354 npx_ex16 = 1; 355 dvp->id_irq = 0; /* zap the interrupt */ 356 /* 357 * special return value to flag that we do not 358 * actually use any I/O registers 359 */ 360 return (-1); 361 } 362 if (npx_intrs_while_probing != 0) { 363 /* 364 * Bad, we are stuck with IRQ13. 365 */ 366 npx_irq13 = 1; 367 /* 368 * npxattach would be too late to set npx0_imask. 369 */ 370 npx0_imask |= dvp->id_irq; 371 return (IO_NPXSIZE); 372 } 373 /* 374 * Worse, even IRQ13 is broken. Use emulator. 375 */ 376 } 377 } 378 /* 379 * Probe failed, but we want to get to npxattach to initialize the 380 * emulator and say that it has been installed. XXX handle devices 381 * that aren't really devices better. 382 */ 383 dvp->id_irq = 0; 384 /* 385 * special return value to flag that we do not 386 * actually use any I/O registers 387 */ 388 return (-1); 389} 390 391/* 392 * Attach routine - announce which it is, and wire into system 393 */ 394int 395npxattach(dvp) 396 struct isa_device *dvp; 397{ 398 /* The caller has printed "irq 13" for the npx_irq13 case. */ 399 if (!npx_irq13) { 400 printf("npx%d: ", dvp->id_unit); 401 if (npx_ex16) 402 printf("INT 16 interface\n"); 403#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 404 else if (npx_exists) { 405 printf("error reporting broken; using 387 emulator\n"); 406 hw_float = npx_exists = 0; 407 } else 408 printf("387 emulator\n"); 409#else 410 else 411 printf("no 387 emulator in kernel!\n"); 412#endif 413 } 414 npxinit(__INITIAL_NPXCW__); 415 416#if defined(I586_CPU) 417 if (cpu_class == CPUCLASS_586 && npx_ex16) { 418 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 419 bcopy_vector = i586_bcopy; 420 ovbcopy_vector = i586_bcopy; 421 } 422 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 423 bzero = i586_bzero; 424 if (!(dvp->id_flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 425 copyin_vector = i586_copyin; 426 copyout_vector = i586_copyout; 427 } 428 } 429#endif 430 431 return (1); /* XXX unused */ 432} 433 434/* 435 * Initialize floating point unit. 436 */ 437void 438npxinit(control) 439 u_short control; 440{ 441 struct save87 dummy; 442 443 if (!npx_exists) 444 return; 445 /* 446 * fninit has the same h/w bugs as fnsave. Use the detoxified 447 * fnsave to throw away any junk in the fpu. npxsave() initializes 448 * the fpu and sets npxproc = NULL as important side effects. 449 */ 450 npxsave(&dummy); 451 stop_emulating(); 452 fldcw(&control); 453 if (curpcb != NULL) 454 fnsave(&curpcb->pcb_savefpu); 455 start_emulating(); 456} 457 458/* 459 * Free coprocessor (if we have it). 460 */ 461void 462npxexit(p) 463 struct proc *p; 464{ 465 466 if (p == npxproc) 467 npxsave(&curpcb->pcb_savefpu); 468#ifdef NPX_DEBUG 469 if (npx_exists) { 470 u_int masked_exceptions; 471 472 masked_exceptions = curpcb->pcb_savefpu.sv_env.en_cw 473 & curpcb->pcb_savefpu.sv_env.en_sw & 0x7f; 474 /* 475 * Log exceptions that would have trapped with the old 476 * control word (overflow, divide by 0, and invalid operand). 477 */ 478 if (masked_exceptions & 0x0d) 479 log(LOG_ERR, 480 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 481 p->p_pid, p->p_comm, masked_exceptions); 482 } 483#endif 484} 485 486/* 487 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 488 * 489 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 490 * depend on longjmp() restoring a usable state. Restoring the state 491 * or examining it might fail if we didn't clear exceptions. 492 * 493 * XXX there is no standard way to tell SIGFPE handlers about the error 494 * state. The old interface: 495 * 496 * void handler(int sig, int code, struct sigcontext *scp); 497 * 498 * is broken because it is non-ANSI and because the FP state is not in 499 * struct sigcontext. 500 * 501 * XXX the FP state is not preserved across signal handlers. So signal 502 * handlers cannot afford to do FP unless they preserve the state or 503 * longjmp() out. Both preserving the state and longjmp()ing may be 504 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 505 * solution for signals other than SIGFPE. 506 */ 507void 508npxintr(unit) 509 int unit; 510{ 511 int code; 512 struct intrframe *frame; 513 514 if (npxproc == NULL || !npx_exists) { 515 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 516 npxproc, curproc, npx_exists); 517 panic("npxintr from nowhere"); 518 } 519 if (npxproc != curproc) { 520 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 521 npxproc, curproc, npx_exists); 522 panic("npxintr from non-current process"); 523 } 524 525 outb(0xf0, 0); 526 fnstsw(&curpcb->pcb_savefpu.sv_ex_sw); 527 fnclex(); 528 fnop(); 529 530 /* 531 * Pass exception to process. 532 */ 533 frame = (struct intrframe *)&unit; /* XXX */ 534 if (ISPL(frame->if_cs) == SEL_UPL) { 535 /* 536 * Interrupt is essentially a trap, so we can afford to call 537 * the SIGFPE handler (if any) as soon as the interrupt 538 * returns. 539 * 540 * XXX little or nothing is gained from this, and plenty is 541 * lost - the interrupt frame has to contain the trap frame 542 * (this is otherwise only necessary for the rescheduling trap 543 * in doreti, and the frame for that could easily be set up 544 * just before it is used). 545 */ 546 curproc->p_md.md_regs = (struct trapframe *)&frame->if_es; 547#ifdef notyet 548 /* 549 * Encode the appropriate code for detailed information on 550 * this exception. 551 */ 552 code = XXX_ENCODE(curpcb->pcb_savefpu.sv_ex_sw); 553#else 554 code = 0; /* XXX */ 555#endif 556 trapsignal(curproc, SIGFPE, code); 557 } else { 558 /* 559 * Nested interrupt. These losers occur when: 560 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 561 * o immediately after an fnsave or frstor of an 562 * error state. 563 * o a couple of 386 instructions after 564 * "fstpl _memvar" causes a stack overflow. 565 * These are especially nasty when combined with a 566 * trace trap. 567 * o an IRQ13 occurs at the same time as another higher- 568 * priority interrupt. 569 * 570 * Treat them like a true async interrupt. 571 */ 572 psignal(curproc, SIGFPE); 573 } 574} 575 576/* 577 * Implement device not available (DNA) exception 578 * 579 * It would be better to switch FP context here (if curproc != npxproc) 580 * and not necessarily for every context switch, but it is too hard to 581 * access foreign pcb's. 582 */ 583int 584npxdna() 585{ 586 if (!npx_exists) 587 return (0); 588 if (npxproc != NULL) { 589 printf("npxdna: npxproc = %p, curproc = %p\n", 590 npxproc, curproc); 591 panic("npxdna"); 592 } 593 stop_emulating(); 594 /* 595 * Record new context early in case frstor causes an IRQ13. 596 */ 597 npxproc = curproc; 598 curpcb->pcb_savefpu.sv_ex_sw = 0; 599 /* 600 * The following frstor may cause an IRQ13 when the state being 601 * restored has a pending error. The error will appear to have been 602 * triggered by the current (npx) user instruction even when that 603 * instruction is a no-wait instruction that should not trigger an 604 * error (e.g., fnclex). On at least one 486 system all of the 605 * no-wait instructions are broken the same as frstor, so our 606 * treatment does not amplify the breakage. On at least one 607 * 386/Cyrix 387 system, fnclex works correctly while frstor and 608 * fnsave are broken, so our treatment breaks fnclex if it is the 609 * first FPU instruction after a context switch. 610 */ 611 frstor(&curpcb->pcb_savefpu); 612 613 return (1); 614} 615 616/* 617 * Wrapper for fnsave instruction to handle h/w bugs. If there is an error 618 * pending, then fnsave generates a bogus IRQ13 on some systems. Force 619 * any IRQ13 to be handled immediately, and then ignore it. This routine is 620 * often called at splhigh so it must not use many system services. In 621 * particular, it's much easier to install a special handler than to 622 * guarantee that it's safe to use npxintr() and its supporting code. 623 */ 624void 625npxsave(addr) 626 struct save87 *addr; 627{ 628#if defined(APIC_IO) 629 u_int apic_mask; 630 u_int old_apic_mask; 631#else 632 u_char icu1_mask; 633 u_char icu2_mask; 634 u_char old_icu1_mask; 635 u_char old_icu2_mask; 636#endif /* APIC_IO */ 637 struct gate_descriptor save_idt_npxintr; 638 639 disable_intr(); 640#if defined(APIC_IO) 641 old_apic_mask = INTRGET(); 642#else 643 old_icu1_mask = inb(IO_ICU1 + 1); 644 old_icu2_mask = inb(IO_ICU2 + 1); 645#endif /* APIC_IO */ 646 save_idt_npxintr = idt[npx_intrno]; 647#if defined(APIC_IO) 648 /** FIXME: try clrIoApicMaskBit( npx0_imask ); */ 649 INTRSET( old_apic_mask & ~(npx0_imask & 0xffff) ); 650#else 651 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask)); 652 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8)); 653#endif /* APIC_IO */ 654 idt[npx_intrno] = npx_idt_probeintr; 655 enable_intr(); 656 stop_emulating(); 657 fnsave(addr); 658 fnop(); 659 start_emulating(); 660 npxproc = NULL; 661 disable_intr(); 662#if defined(APIC_IO) 663 apic_mask = INTRGET(); /* masks may have changed */ 664 INTRSET( (apic_mask & ~(npx0_imask & 0xffff)) | 665 (old_apic_mask & (npx0_imask & 0xffff))); 666#else 667 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */ 668 icu2_mask = inb(IO_ICU2 + 1); 669 outb(IO_ICU1 + 1, 670 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask)); 671 outb(IO_ICU2 + 1, 672 (icu2_mask & ~(npx0_imask >> 8)) 673 | (old_icu2_mask & (npx0_imask >> 8))); 674#endif /* APIC_IO */ 675 idt[npx_intrno] = save_idt_npxintr; 676 enable_intr(); /* back to usual state */ 677} 678 679#endif /* NNPX > 0 */ 680