npx.c revision 209461
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 209461 2010-06-23 11:12:58Z kib $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58 59#include <machine/asmacros.h> 60#include <machine/cputypes.h> 61#include <machine/frame.h> 62#include <machine/md_var.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#include <machine/resource.h> 66#include <machine/specialreg.h> 67#include <machine/segments.h> 68#include <machine/ucontext.h> 69 70#include <machine/intr_machdep.h> 71#ifdef XEN 72#include <machine/xen/xen-os.h> 73#include <xen/hypervisor.h> 74#endif 75 76#ifdef DEV_ISA 77#include <isa/isavar.h> 78#endif 79 80#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 81#define CPU_ENABLE_SSE 82#endif 83 84/* 85 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 86 */ 87 88#if defined(__GNUCLIKE_ASM) && !defined(lint) 89 90#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 91#define fnclex() __asm("fnclex") 92#define fninit() __asm("fninit") 93#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 94#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 95#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 96#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 97#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 98#ifdef CPU_ENABLE_SSE 99#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 100#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 101#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 102#endif 103#ifdef XEN 104#define start_emulating() (HYPERVISOR_fpu_taskswitch(1)) 105#define stop_emulating() (HYPERVISOR_fpu_taskswitch(0)) 106#else 107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 108 : : "n" (CR0_TS) : "ax") 109#define stop_emulating() __asm("clts") 110#endif 111#else /* !(__GNUCLIKE_ASM && !lint) */ 112 113void fldcw(caddr_t addr); 114void fnclex(void); 115void fninit(void); 116void fnsave(caddr_t addr); 117void fnstcw(caddr_t addr); 118void fnstsw(caddr_t addr); 119void fp_divide_by_0(void); 120void frstor(caddr_t addr); 121#ifdef CPU_ENABLE_SSE 122void fxsave(caddr_t addr); 123void fxrstor(caddr_t addr); 124#endif 125void start_emulating(void); 126void stop_emulating(void); 127 128#endif /* __GNUCLIKE_ASM && !lint */ 129 130#ifdef CPU_ENABLE_SSE 131#define GET_FPU_CW(thread) \ 132 (cpu_fxsr ? \ 133 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \ 134 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw) 135#define GET_FPU_SW(thread) \ 136 (cpu_fxsr ? \ 137 (thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \ 138 (thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw) 139#define SET_FPU_CW(savefpu, value) do { \ 140 if (cpu_fxsr) \ 141 (savefpu)->sv_xmm.sv_env.en_cw = (value); \ 142 else \ 143 (savefpu)->sv_87.sv_env.en_cw = (value); \ 144} while (0) 145#else /* CPU_ENABLE_SSE */ 146#define GET_FPU_CW(thread) \ 147 (thread->td_pcb->pcb_save->sv_87.sv_env.en_cw) 148#define GET_FPU_SW(thread) \ 149 (thread->td_pcb->pcb_save->sv_87.sv_env.en_sw) 150#define SET_FPU_CW(savefpu, value) \ 151 (savefpu)->sv_87.sv_env.en_cw = (value) 152#endif /* CPU_ENABLE_SSE */ 153 154typedef u_char bool_t; 155 156#ifdef CPU_ENABLE_SSE 157static void fpu_clean_state(void); 158#endif 159 160static void fpusave(union savefpu *); 161static void fpurstor(union savefpu *); 162static int npx_attach(device_t dev); 163static void npx_identify(driver_t *driver, device_t parent); 164static int npx_probe(device_t dev); 165 166int hw_float; 167 168SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 169 &hw_float, 0, "Floating point instructions executed in hardware"); 170 171static volatile u_int npx_traps_while_probing; 172static union savefpu npx_initialstate; 173 174alias_for_inthand_t probetrap; 175__asm(" \n\ 176 .text \n\ 177 .p2align 2,0x90 \n\ 178 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 179" __XSTRING(CNAME(probetrap)) ": \n\ 180 ss \n\ 181 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 182 fnclex \n\ 183 iret \n\ 184"); 185 186/* 187 * Identify routine. Create a connection point on our parent for probing. 188 */ 189static void 190npx_identify(driver, parent) 191 driver_t *driver; 192 device_t parent; 193{ 194 device_t child; 195 196 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 197 if (child == NULL) 198 panic("npx_identify"); 199} 200 201/* 202 * Probe routine. Set flags to tell npxattach() what to do. Set up an 203 * interrupt handler if npx needs to use interrupts. 204 */ 205static int 206npx_probe(device_t dev) 207{ 208 struct gate_descriptor save_idt_npxtrap; 209 u_short control, status; 210 211 device_set_desc(dev, "math processor"); 212 213 /* 214 * Modern CPUs all have an FPU that uses the INT16 interface 215 * and provide a simple way to verify that, so handle the 216 * common case right away. 217 */ 218 if (cpu_feature & CPUID_FPU) { 219 hw_float = 1; 220 device_quiet(dev); 221 return (0); 222 } 223 224 save_idt_npxtrap = idt[IDT_MF]; 225 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 226 GSEL(GCODE_SEL, SEL_KPL)); 227 228 /* 229 * Don't trap while we're probing. 230 */ 231 stop_emulating(); 232 233 /* 234 * Finish resetting the coprocessor, if any. If there is an error 235 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 236 * it OK. Bogus halts have never been observed, but we enabled 237 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 238 */ 239 fninit(); 240 241 /* 242 * Don't use fwait here because it might hang. 243 * Don't use fnop here because it usually hangs if there is no FPU. 244 */ 245 DELAY(1000); /* wait for any IRQ13 */ 246#ifdef DIAGNOSTIC 247 if (npx_traps_while_probing != 0) 248 printf("fninit caused %u bogus npx trap(s)\n", 249 npx_traps_while_probing); 250#endif 251 /* 252 * Check for a status of mostly zero. 253 */ 254 status = 0x5a5a; 255 fnstsw(&status); 256 if ((status & 0xb8ff) == 0) { 257 /* 258 * Good, now check for a proper control word. 259 */ 260 control = 0x5a5a; 261 fnstcw(&control); 262 if ((control & 0x1f3f) == 0x033f) { 263 /* 264 * We have an npx, now divide by 0 to see if exception 265 * 16 works. 266 */ 267 control &= ~(1 << 2); /* enable divide by 0 trap */ 268 fldcw(&control); 269#ifdef FPU_ERROR_BROKEN 270 /* 271 * FPU error signal doesn't work on some CPU 272 * accelerator board. 273 */ 274 hw_float = 1; 275 return (0); 276#endif 277 npx_traps_while_probing = 0; 278 fp_divide_by_0(); 279 if (npx_traps_while_probing != 0) { 280 /* 281 * Good, exception 16 works. 282 */ 283 hw_float = 1; 284 goto cleanup; 285 } 286 device_printf(dev, 287 "FPU does not use exception 16 for error reporting\n"); 288 goto cleanup; 289 } 290 } 291 292 /* 293 * Probe failed. Floating point simply won't work. 294 * Notify user and disable FPU/MMX/SSE instruction execution. 295 */ 296 device_printf(dev, "WARNING: no FPU!\n"); 297 __asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : : 298 "n" (CR0_EM | CR0_MP) : "ax"); 299 300cleanup: 301 idt[IDT_MF] = save_idt_npxtrap; 302 return (hw_float ? 0 : ENXIO); 303} 304 305/* 306 * Attach routine - announce which it is, and wire into system 307 */ 308static int 309npx_attach(device_t dev) 310{ 311 register_t s; 312 313 npxinit(); 314 s = intr_disable(); 315 stop_emulating(); 316 fpusave(&npx_initialstate); 317 start_emulating(); 318#ifdef CPU_ENABLE_SSE 319 if (cpu_fxsr) { 320 if (npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask) 321 cpu_mxcsr_mask = 322 npx_initialstate.sv_xmm.sv_env.en_mxcsr_mask; 323 else 324 cpu_mxcsr_mask = 0xFFBF; 325 bzero(npx_initialstate.sv_xmm.sv_fp, 326 sizeof(npx_initialstate.sv_xmm.sv_fp)); 327 bzero(npx_initialstate.sv_xmm.sv_xmm, 328 sizeof(npx_initialstate.sv_xmm.sv_xmm)); 329 /* XXX might need even more zeroing. */ 330 } else 331#endif 332 bzero(npx_initialstate.sv_87.sv_ac, 333 sizeof(npx_initialstate.sv_87.sv_ac)); 334 intr_restore(s); 335 336 return (0); 337} 338 339/* 340 * Initialize floating point unit. 341 */ 342void 343npxinit(void) 344{ 345 static union savefpu dummy; 346 register_t savecrit; 347 u_short control; 348 349 if (!hw_float) 350 return; 351 /* 352 * fninit has the same h/w bugs as fnsave. Use the detoxified 353 * fnsave to throw away any junk in the fpu. npxsave() initializes 354 * the fpu and sets fpcurthread = NULL as important side effects. 355 */ 356 savecrit = intr_disable(); 357 npxsave(&dummy); 358 stop_emulating(); 359#ifdef CPU_ENABLE_SSE 360 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 361 if (cpu_fxsr) 362 fninit(); 363#endif 364 control = __INITIAL_NPXCW__; 365 fldcw(&control); 366 start_emulating(); 367 intr_restore(savecrit); 368} 369 370/* 371 * Free coprocessor (if we have it). 372 */ 373void 374npxexit(td) 375 struct thread *td; 376{ 377 register_t savecrit; 378 379 savecrit = intr_disable(); 380 if (curthread == PCPU_GET(fpcurthread)) 381 npxsave(PCPU_GET(curpcb)->pcb_save); 382 intr_restore(savecrit); 383#ifdef NPX_DEBUG 384 if (hw_float) { 385 u_int masked_exceptions; 386 387 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 388 /* 389 * Log exceptions that would have trapped with the old 390 * control word (overflow, divide by 0, and invalid operand). 391 */ 392 if (masked_exceptions & 0x0d) 393 log(LOG_ERR, 394 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 395 td->td_proc->p_pid, td->td_proc->p_comm, 396 masked_exceptions); 397 } 398#endif 399} 400 401int 402npxformat() 403{ 404 405 if (!hw_float) 406 return (_MC_FPFMT_NODEV); 407#ifdef CPU_ENABLE_SSE 408 if (cpu_fxsr) 409 return (_MC_FPFMT_XMM); 410#endif 411 return (_MC_FPFMT_387); 412} 413 414/* 415 * The following mechanism is used to ensure that the FPE_... value 416 * that is passed as a trapcode to the signal handler of the user 417 * process does not have more than one bit set. 418 * 419 * Multiple bits may be set if the user process modifies the control 420 * word while a status word bit is already set. While this is a sign 421 * of bad coding, we have no choise than to narrow them down to one 422 * bit, since we must not send a trapcode that is not exactly one of 423 * the FPE_ macros. 424 * 425 * The mechanism has a static table with 127 entries. Each combination 426 * of the 7 FPU status word exception bits directly translates to a 427 * position in this table, where a single FPE_... value is stored. 428 * This FPE_... value stored there is considered the "most important" 429 * of the exception bits and will be sent as the signal code. The 430 * precedence of the bits is based upon Intel Document "Numerical 431 * Applications", Chapter "Special Computational Situations". 432 * 433 * The macro to choose one of these values does these steps: 1) Throw 434 * away status word bits that cannot be masked. 2) Throw away the bits 435 * currently masked in the control word, assuming the user isn't 436 * interested in them anymore. 3) Reinsert status word bit 7 (stack 437 * fault) if it is set, which cannot be masked but must be presered. 438 * 4) Use the remaining bits to point into the trapcode table. 439 * 440 * The 6 maskable bits in order of their preference, as stated in the 441 * above referenced Intel manual: 442 * 1 Invalid operation (FP_X_INV) 443 * 1a Stack underflow 444 * 1b Stack overflow 445 * 1c Operand of unsupported format 446 * 1d SNaN operand. 447 * 2 QNaN operand (not an exception, irrelavant here) 448 * 3 Any other invalid-operation not mentioned above or zero divide 449 * (FP_X_INV, FP_X_DZ) 450 * 4 Denormal operand (FP_X_DNML) 451 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 452 * 6 Inexact result (FP_X_IMP) 453 */ 454static char fpetable[128] = { 455 0, 456 FPE_FLTINV, /* 1 - INV */ 457 FPE_FLTUND, /* 2 - DNML */ 458 FPE_FLTINV, /* 3 - INV | DNML */ 459 FPE_FLTDIV, /* 4 - DZ */ 460 FPE_FLTINV, /* 5 - INV | DZ */ 461 FPE_FLTDIV, /* 6 - DNML | DZ */ 462 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 463 FPE_FLTOVF, /* 8 - OFL */ 464 FPE_FLTINV, /* 9 - INV | OFL */ 465 FPE_FLTUND, /* A - DNML | OFL */ 466 FPE_FLTINV, /* B - INV | DNML | OFL */ 467 FPE_FLTDIV, /* C - DZ | OFL */ 468 FPE_FLTINV, /* D - INV | DZ | OFL */ 469 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 470 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 471 FPE_FLTUND, /* 10 - UFL */ 472 FPE_FLTINV, /* 11 - INV | UFL */ 473 FPE_FLTUND, /* 12 - DNML | UFL */ 474 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 475 FPE_FLTDIV, /* 14 - DZ | UFL */ 476 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 477 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 478 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 479 FPE_FLTOVF, /* 18 - OFL | UFL */ 480 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 481 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 482 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 483 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 484 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 485 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 486 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 487 FPE_FLTRES, /* 20 - IMP */ 488 FPE_FLTINV, /* 21 - INV | IMP */ 489 FPE_FLTUND, /* 22 - DNML | IMP */ 490 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 491 FPE_FLTDIV, /* 24 - DZ | IMP */ 492 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 493 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 494 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 495 FPE_FLTOVF, /* 28 - OFL | IMP */ 496 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 497 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 498 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 499 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 500 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 501 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 502 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 503 FPE_FLTUND, /* 30 - UFL | IMP */ 504 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 505 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 506 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 507 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 508 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 509 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 510 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 511 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 512 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 513 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 514 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 515 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 516 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 517 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 518 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 519 FPE_FLTSUB, /* 40 - STK */ 520 FPE_FLTSUB, /* 41 - INV | STK */ 521 FPE_FLTUND, /* 42 - DNML | STK */ 522 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 523 FPE_FLTDIV, /* 44 - DZ | STK */ 524 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 525 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 526 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 527 FPE_FLTOVF, /* 48 - OFL | STK */ 528 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 529 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 530 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 531 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 532 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 533 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 534 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 535 FPE_FLTUND, /* 50 - UFL | STK */ 536 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 537 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 538 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 539 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 540 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 541 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 542 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 543 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 544 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 545 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 546 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 547 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 548 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 549 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 550 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 551 FPE_FLTRES, /* 60 - IMP | STK */ 552 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 553 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 554 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 555 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 556 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 557 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 558 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 559 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 560 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 561 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 562 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 563 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 564 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 565 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 566 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 567 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 568 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 569 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 570 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 571 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 572 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 573 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 574 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 575 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 576 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 577 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 578 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 579 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 580 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 581 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 582 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 583}; 584 585/* 586 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 587 * 588 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 589 * depend on longjmp() restoring a usable state. Restoring the state 590 * or examining it might fail if we didn't clear exceptions. 591 * 592 * The error code chosen will be one of the FPE_... macros. It will be 593 * sent as the second argument to old BSD-style signal handlers and as 594 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 595 * 596 * XXX the FP state is not preserved across signal handlers. So signal 597 * handlers cannot afford to do FP unless they preserve the state or 598 * longjmp() out. Both preserving the state and longjmp()ing may be 599 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 600 * solution for signals other than SIGFPE. 601 */ 602int 603npxtrap() 604{ 605 register_t savecrit; 606 u_short control, status; 607 608 if (!hw_float) { 609 printf("npxtrap: fpcurthread = %p, curthread = %p, hw_float = %d\n", 610 PCPU_GET(fpcurthread), curthread, hw_float); 611 panic("npxtrap from nowhere"); 612 } 613 savecrit = intr_disable(); 614 615 /* 616 * Interrupt handling (for another interrupt) may have pushed the 617 * state to memory. Fetch the relevant parts of the state from 618 * wherever they are. 619 */ 620 if (PCPU_GET(fpcurthread) != curthread) { 621 control = GET_FPU_CW(curthread); 622 status = GET_FPU_SW(curthread); 623 } else { 624 fnstcw(&control); 625 fnstsw(&status); 626 } 627 628 if (PCPU_GET(fpcurthread) == curthread) 629 fnclex(); 630 intr_restore(savecrit); 631 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 632} 633 634/* 635 * Implement device not available (DNA) exception 636 * 637 * It would be better to switch FP context here (if curthread != fpcurthread) 638 * and not necessarily for every context switch, but it is too hard to 639 * access foreign pcb's. 640 */ 641 642static int err_count = 0; 643 644int 645npxdna(void) 646{ 647 struct pcb *pcb; 648 register_t s; 649 650 if (!hw_float) 651 return (0); 652 if (PCPU_GET(fpcurthread) == curthread) { 653 printf("npxdna: fpcurthread == curthread %d times\n", 654 ++err_count); 655 stop_emulating(); 656 return (1); 657 } 658 if (PCPU_GET(fpcurthread) != NULL) { 659 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 660 PCPU_GET(fpcurthread), 661 PCPU_GET(fpcurthread)->td_proc->p_pid, 662 curthread, curthread->td_proc->p_pid); 663 panic("npxdna"); 664 } 665 s = intr_disable(); 666 stop_emulating(); 667 /* 668 * Record new context early in case frstor causes an IRQ13. 669 */ 670 PCPU_SET(fpcurthread, curthread); 671 pcb = PCPU_GET(curpcb); 672 673#ifdef CPU_ENABLE_SSE 674 if (cpu_fxsr) 675 fpu_clean_state(); 676#endif 677 678 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 679 /* 680 * This is the first time this thread has used the FPU or 681 * the PCB doesn't contain a clean FPU state. Explicitly 682 * load an initial state. 683 */ 684 fpurstor(&npx_initialstate); 685 if (pcb->pcb_initial_npxcw != __INITIAL_NPXCW__) 686 fldcw(&pcb->pcb_initial_npxcw); 687 pcb->pcb_flags |= PCB_NPXINITDONE; 688 if (PCB_USER_FPU(pcb)) 689 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 690 } else { 691 /* 692 * The following fpurstor() may cause an IRQ13 when the 693 * state being restored has a pending error. The error will 694 * appear to have been triggered by the current (npx) user 695 * instruction even when that instruction is a no-wait 696 * instruction that should not trigger an error (e.g., 697 * fnclex). On at least one 486 system all of the no-wait 698 * instructions are broken the same as frstor, so our 699 * treatment does not amplify the breakage. On at least 700 * one 386/Cyrix 387 system, fnclex works correctly while 701 * frstor and fnsave are broken, so our treatment breaks 702 * fnclex if it is the first FPU instruction after a context 703 * switch. 704 */ 705 fpurstor(pcb->pcb_save); 706 } 707 intr_restore(s); 708 709 return (1); 710} 711 712/* 713 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 714 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 715 * no-wait npx instructions. See the Intel application note AP-578 for 716 * details. This doesn't cause any additional complications here. IRQ13's 717 * are inherently asynchronous unless the CPU is frozen to deliver them -- 718 * one that started in userland may be delivered many instructions later, 719 * after the process has entered the kernel. It may even be delivered after 720 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 721 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 722 * it is normally ignored at first because we set fpcurthread to NULL; it is 723 * normally retriggered in npxdna() after return to user mode. 724 * 725 * npxsave() must be called with interrupts disabled, so that it clears 726 * fpcurthread atomically with saving the state. We require callers to do the 727 * disabling, since most callers need to disable interrupts anyway to call 728 * npxsave() atomically with checking fpcurthread. 729 * 730 * A previous version of npxsave() went to great lengths to excecute fnsave 731 * with interrupts enabled in case executing it froze the CPU. This case 732 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 733 * spurious freezes. 734 */ 735void 736npxsave(addr) 737 union savefpu *addr; 738{ 739 740 stop_emulating(); 741 fpusave(addr); 742 743 start_emulating(); 744 PCPU_SET(fpcurthread, NULL); 745} 746 747/* 748 * This should be called with interrupts disabled and only when the owning 749 * FPU thread is non-null. 750 */ 751void 752npxdrop() 753{ 754 struct thread *td; 755 756 /* 757 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 758 * ones don't cause a panic on the next frstor. 759 */ 760#ifdef CPU_ENABLE_SSE 761 if (!cpu_fxsr) 762#endif 763 fnclex(); 764 765 td = PCPU_GET(fpcurthread); 766 PCPU_SET(fpcurthread, NULL); 767 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 768 start_emulating(); 769} 770 771/* 772 * Get the state of the FPU without dropping ownership (if possible). 773 * It returns the FPU ownership status. 774 */ 775int 776npxgetregs(struct thread *td, union savefpu *addr) 777{ 778 struct pcb *pcb; 779 register_t s; 780 781 if (!hw_float) 782 return (_MC_FPOWNED_NONE); 783 784 pcb = td->td_pcb; 785 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 786 bcopy(&npx_initialstate, addr, sizeof(npx_initialstate)); 787 SET_FPU_CW(addr, pcb->pcb_initial_npxcw); 788 return (_MC_FPOWNED_NONE); 789 } 790 s = intr_disable(); 791 if (td == PCPU_GET(fpcurthread)) { 792 fpusave(addr); 793#ifdef CPU_ENABLE_SSE 794 if (!cpu_fxsr) 795#endif 796 /* 797 * fnsave initializes the FPU and destroys whatever 798 * context it contains. Make sure the FPU owner 799 * starts with a clean state next time. 800 */ 801 npxdrop(); 802 intr_restore(s); 803 return (_MC_FPOWNED_FPU); 804 } else { 805 intr_restore(s); 806 bcopy(pcb->pcb_save, addr, sizeof(*addr)); 807 return (_MC_FPOWNED_PCB); 808 } 809} 810 811int 812npxgetuserregs(struct thread *td, union savefpu *addr) 813{ 814 struct pcb *pcb; 815 register_t s; 816 817 if (!hw_float) 818 return (_MC_FPOWNED_NONE); 819 820 pcb = td->td_pcb; 821 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) == 0) { 822 bcopy(&npx_initialstate, addr, sizeof(npx_initialstate)); 823 SET_FPU_CW(addr, pcb->pcb_initial_npxcw); 824 return (_MC_FPOWNED_NONE); 825 } 826 s = intr_disable(); 827 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 828 fpusave(addr); 829#ifdef CPU_ENABLE_SSE 830 if (!cpu_fxsr) 831#endif 832 /* 833 * fnsave initializes the FPU and destroys whatever 834 * context it contains. Make sure the FPU owner 835 * starts with a clean state next time. 836 */ 837 npxdrop(); 838 intr_restore(s); 839 return (_MC_FPOWNED_FPU); 840 } else { 841 intr_restore(s); 842 bcopy(&pcb->pcb_user_save, addr, sizeof(*addr)); 843 return (_MC_FPOWNED_PCB); 844 } 845} 846 847/* 848 * Set the state of the FPU. 849 */ 850void 851npxsetregs(struct thread *td, union savefpu *addr) 852{ 853 struct pcb *pcb; 854 register_t s; 855 856 if (!hw_float) 857 return; 858 859 pcb = td->td_pcb; 860 s = intr_disable(); 861 if (td == PCPU_GET(fpcurthread)) { 862#ifdef CPU_ENABLE_SSE 863 if (!cpu_fxsr) 864#endif 865 fnclex(); /* As in npxdrop(). */ 866 fpurstor(addr); 867 intr_restore(s); 868 } else { 869 intr_restore(s); 870 bcopy(addr, pcb->pcb_save, sizeof(*addr)); 871 } 872 if (PCB_USER_FPU(pcb)) 873 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 874 pcb->pcb_flags |= PCB_NPXINITDONE; 875} 876 877void 878npxsetuserregs(struct thread *td, union savefpu *addr) 879{ 880 struct pcb *pcb; 881 register_t s; 882 883 if (!hw_float) 884 return; 885 886 pcb = td->td_pcb; 887 s = intr_disable(); 888 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) { 889#ifdef CPU_ENABLE_SSE 890 if (!cpu_fxsr) 891#endif 892 fnclex(); /* As in npxdrop(). */ 893 fpurstor(addr); 894 intr_restore(s); 895 pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE; 896 } else { 897 intr_restore(s); 898 bcopy(addr, &pcb->pcb_user_save, sizeof(*addr)); 899 if (PCB_USER_FPU(pcb)) 900 pcb->pcb_flags |= PCB_NPXINITDONE; 901 pcb->pcb_flags |= PCB_NPXUSERINITDONE; 902 } 903} 904 905static void 906fpusave(addr) 907 union savefpu *addr; 908{ 909 910#ifdef CPU_ENABLE_SSE 911 if (cpu_fxsr) 912 fxsave(addr); 913 else 914#endif 915 fnsave(addr); 916} 917 918#ifdef CPU_ENABLE_SSE 919/* 920 * On AuthenticAMD processors, the fxrstor instruction does not restore 921 * the x87's stored last instruction pointer, last data pointer, and last 922 * opcode values, except in the rare case in which the exception summary 923 * (ES) bit in the x87 status word is set to 1. 924 * 925 * In order to avoid leaking this information across processes, we clean 926 * these values by performing a dummy load before executing fxrstor(). 927 */ 928static void 929fpu_clean_state(void) 930{ 931 static float dummy_variable = 0.0; 932 u_short status; 933 934 /* 935 * Clear the ES bit in the x87 status word if it is currently 936 * set, in order to avoid causing a fault in the upcoming load. 937 */ 938 fnstsw(&status); 939 if (status & 0x80) 940 fnclex(); 941 942 /* 943 * Load the dummy variable into the x87 stack. This mangles 944 * the x87 stack, but we don't care since we're about to call 945 * fxrstor() anyway. 946 */ 947 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 948} 949#endif /* CPU_ENABLE_SSE */ 950 951static void 952fpurstor(addr) 953 union savefpu *addr; 954{ 955 956#ifdef CPU_ENABLE_SSE 957 if (cpu_fxsr) 958 fxrstor(addr); 959 else 960#endif 961 frstor(addr); 962} 963 964static device_method_t npx_methods[] = { 965 /* Device interface */ 966 DEVMETHOD(device_identify, npx_identify), 967 DEVMETHOD(device_probe, npx_probe), 968 DEVMETHOD(device_attach, npx_attach), 969 DEVMETHOD(device_detach, bus_generic_detach), 970 DEVMETHOD(device_shutdown, bus_generic_shutdown), 971 DEVMETHOD(device_suspend, bus_generic_suspend), 972 DEVMETHOD(device_resume, bus_generic_resume), 973 974 { 0, 0 } 975}; 976 977static driver_t npx_driver = { 978 "npx", 979 npx_methods, 980 1, /* no softc */ 981}; 982 983static devclass_t npx_devclass; 984 985/* 986 * We prefer to attach to the root nexus so that the usual case (exception 16) 987 * doesn't describe the processor as being `on isa'. 988 */ 989DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 990 991#ifdef DEV_ISA 992/* 993 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 994 */ 995static struct isa_pnp_id npxisa_ids[] = { 996 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 997 { 0 } 998}; 999 1000static int 1001npxisa_probe(device_t dev) 1002{ 1003 int result; 1004 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1005 device_quiet(dev); 1006 } 1007 return(result); 1008} 1009 1010static int 1011npxisa_attach(device_t dev) 1012{ 1013 return (0); 1014} 1015 1016static device_method_t npxisa_methods[] = { 1017 /* Device interface */ 1018 DEVMETHOD(device_probe, npxisa_probe), 1019 DEVMETHOD(device_attach, npxisa_attach), 1020 DEVMETHOD(device_detach, bus_generic_detach), 1021 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1022 DEVMETHOD(device_suspend, bus_generic_suspend), 1023 DEVMETHOD(device_resume, bus_generic_resume), 1024 1025 { 0, 0 } 1026}; 1027 1028static driver_t npxisa_driver = { 1029 "npxisa", 1030 npxisa_methods, 1031 1, /* no softc */ 1032}; 1033 1034static devclass_t npxisa_devclass; 1035 1036DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1037#ifndef PC98 1038DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1039#endif 1040#endif /* DEV_ISA */ 1041 1042int 1043fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags) 1044{ 1045 struct pcb *pcb; 1046 1047 pcb = td->td_pcb; 1048 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == &pcb->pcb_user_save, 1049 ("mangled pcb_save")); 1050 ctx->flags = 0; 1051 if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0) 1052 ctx->flags |= FPU_KERN_CTX_NPXINITDONE; 1053 npxexit(td); 1054 ctx->prev = pcb->pcb_save; 1055 pcb->pcb_save = &ctx->hwstate; 1056 pcb->pcb_flags |= PCB_KERNNPX; 1057 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1058 return (0); 1059} 1060 1061int 1062fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx) 1063{ 1064 struct pcb *pcb; 1065 register_t savecrit; 1066 1067 pcb = td->td_pcb; 1068 savecrit = intr_disable(); 1069 if (curthread == PCPU_GET(fpcurthread)) 1070 npxdrop(); 1071 intr_restore(savecrit); 1072 pcb->pcb_save = ctx->prev; 1073 if (pcb->pcb_save == &pcb->pcb_user_save) { 1074 if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0) 1075 pcb->pcb_flags |= PCB_NPXINITDONE; 1076 else 1077 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1078 pcb->pcb_flags &= ~PCB_KERNNPX; 1079 } else { 1080 if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0) 1081 pcb->pcb_flags |= PCB_NPXINITDONE; 1082 else 1083 pcb->pcb_flags &= ~PCB_NPXINITDONE; 1084 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave")); 1085 } 1086 return (0); 1087} 1088 1089int 1090fpu_kern_thread(u_int flags) 1091{ 1092 struct pcb *pcb; 1093 1094 pcb = PCPU_GET(curpcb); 1095 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0, 1096 ("Only kthread may use fpu_kern_thread")); 1097 KASSERT(pcb->pcb_save == &pcb->pcb_user_save, ("mangled pcb_save")); 1098 KASSERT(PCB_USER_FPU(pcb), ("recursive call")); 1099 1100 pcb->pcb_flags |= PCB_KERNNPX; 1101 return (0); 1102} 1103 1104int 1105is_fpu_kern_thread(u_int flags) 1106{ 1107 1108 if ((curthread->td_pflags & TDP_KTHREAD) == 0) 1109 return (0); 1110 return ((PCPU_GET(curpcb)->pcb_flags & PCB_KERNNPX) != 0); 1111} 1112