npx.c revision 189004
121259Swollman/*- 221259Swollman * Copyright (c) 1990 William Jolitz. 321259Swollman * Copyright (c) 1991 The Regents of the University of California. 421259Swollman * All rights reserved. 521259Swollman * 621259Swollman * Redistribution and use in source and binary forms, with or without 721259Swollman * modification, are permitted provided that the following conditions 821259Swollman * are met: 921259Swollman * 1. Redistributions of source code must retain the above copyright 1021259Swollman * notice, this list of conditions and the following disclaimer. 1121259Swollman * 2. Redistributions in binary form must reproduce the above copyright 1221259Swollman * notice, this list of conditions and the following disclaimer in the 1321259Swollman * documentation and/or other materials provided with the distribution. 1421259Swollman * 4. Neither the name of the University nor the names of its contributors 1521259Swollman * may be used to endorse or promote products derived from this software 1621259Swollman * without specific prior written permission. 1721259Swollman * 1821259Swollman * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 1921259Swollman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2021259Swollman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2121259Swollman * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2221259Swollman * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2321259Swollman * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2421259Swollman * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2521259Swollman * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2621259Swollman * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2721259Swollman * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2821259Swollman * SUCH DAMAGE. 2921259Swollman * 3021259Swollman * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 3121259Swollman */ 3221259Swollman 3321259Swollman#include <sys/cdefs.h> 3428845Sjulian__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 189004 2009-02-24 18:09:31Z rdivacky $"); 3521259Swollman 3621259Swollman#include "opt_cpu.h" 3721259Swollman#include "opt_isa.h" 3821259Swollman#include "opt_npx.h" 3921259Swollman 4021259Swollman#include <sys/param.h> 4121259Swollman#include <sys/systm.h> 4221259Swollman#include <sys/bus.h> 4321259Swollman#include <sys/kernel.h> 4421259Swollman#include <sys/lock.h> 4521259Swollman#include <sys/malloc.h> 4621259Swollman#include <sys/module.h> 4721259Swollman#include <sys/mutex.h> 4821259Swollman#include <sys/mutex.h> 4921259Swollman#include <sys/proc.h> 5021259Swollman#include <sys/smp.h> 5121259Swollman#include <sys/sysctl.h> 5221259Swollman#include <machine/bus.h> 5321259Swollman#include <sys/rman.h> 5421259Swollman#ifdef NPX_DEBUG 5521259Swollman#include <sys/syslog.h> 5621259Swollman#endif 5721259Swollman#include <sys/signalvar.h> 5821259Swollman 5921259Swollman#include <machine/asmacros.h> 6021259Swollman#include <machine/cputypes.h> 6121259Swollman#include <machine/frame.h> 6221259Swollman#include <machine/md_var.h> 6321259Swollman#include <machine/pcb.h> 6421259Swollman#include <machine/psl.h> 6521259Swollman#include <machine/resource.h> 6621259Swollman#include <machine/specialreg.h> 6721259Swollman#include <machine/segments.h> 6821259Swollman#include <machine/ucontext.h> 6921259Swollman 7021259Swollman#include <machine/intr_machdep.h> 7121259Swollman#ifdef XEN 7221259Swollman#include <machine/xen/xen-os.h> 7321259Swollman#include <xen/hypervisor.h> 7421259Swollman#endif 7521259Swollman 7621259Swollman#ifdef DEV_ISA 7721259Swollman#include <isa/isavar.h> 7821259Swollman#endif 7921259Swollman 8021404Swollman#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 8121259Swollman#define CPU_ENABLE_SSE 8221259Swollman#endif 8321259Swollman 8421259Swollman/* 8521259Swollman * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 8621259Swollman */ 8721259Swollman 8821259Swollman/* Configuration flags. */ 8921259Swollman#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 9021259Swollman#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 9121259Swollman#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 9221259Swollman 9321259Swollman#if defined(__GNUCLIKE_ASM) && !defined(lint) 9421259Swollman 9521259Swollman#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 9621259Swollman#define fnclex() __asm("fnclex") 9721259Swollman#define fninit() __asm("fninit") 9821259Swollman#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 9921259Swollman#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 10021259Swollman#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 10121259Swollman#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 10221259Swollman#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 10321259Swollman#ifdef CPU_ENABLE_SSE 10421259Swollman#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 10521259Swollman#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 10621259Swollman#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 10721259Swollman#endif 10821259Swollman#ifdef XEN 10921259Swollman#define start_emulating() (HYPERVISOR_fpu_taskswitch(1)) 11021259Swollman#define stop_emulating() (HYPERVISOR_fpu_taskswitch(0)) 11121259Swollman#else 11221259Swollman#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 11321404Swollman : : "n" (CR0_TS) : "ax") 11421404Swollman#define stop_emulating() __asm("clts") 11521259Swollman#endif 11621259Swollman#else /* !(__GNUCLIKE_ASM && !lint) */ 11721259Swollman 11821259Swollmanvoid fldcw(caddr_t addr); 11921259Swollmanvoid fnclex(void); 12021259Swollmanvoid fninit(void); 12121259Swollmanvoid fnsave(caddr_t addr); 12221259Swollmanvoid fnstcw(caddr_t addr); 12321259Swollmanvoid fnstsw(caddr_t addr); 12421259Swollmanvoid fp_divide_by_0(void); 12521259Swollmanvoid frstor(caddr_t addr); 12621259Swollman#ifdef CPU_ENABLE_SSE 12721259Swollmanvoid fxsave(caddr_t addr); 12821259Swollmanvoid fxrstor(caddr_t addr); 12921259Swollman#endif 13021259Swollmanvoid start_emulating(void); 13121259Swollmanvoid stop_emulating(void); 13221259Swollman 13321259Swollman#endif /* __GNUCLIKE_ASM && !lint */ 13421259Swollman 13521259Swollman#ifdef CPU_ENABLE_SSE 13621259Swollman#define GET_FPU_CW(thread) \ 13721404Swollman (cpu_fxsr ? \ 13821404Swollman (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 13921259Swollman (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 14021259Swollman#define GET_FPU_SW(thread) \ 14121259Swollman (cpu_fxsr ? \ 14221259Swollman (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 14321259Swollman (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 14421259Swollman#else /* CPU_ENABLE_SSE */ 14521259Swollman#define GET_FPU_CW(thread) \ 14621259Swollman (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 14721259Swollman#define GET_FPU_SW(thread) \ 14821259Swollman (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 14921259Swollman#endif /* CPU_ENABLE_SSE */ 15021259Swollman 15121259Swollmantypedef u_char bool_t; 15221259Swollman 15321259Swollman#ifdef CPU_ENABLE_SSE 15421259Swollmanstatic void fpu_clean_state(void); 15521259Swollman#endif 15621259Swollman 15721259Swollmanstatic void fpusave(union savefpu *); 15821259Swollmanstatic void fpurstor(union savefpu *); 15921259Swollmanstatic int npx_attach(device_t dev); 16021259Swollmanstatic void npx_identify(driver_t *driver, device_t parent); 16121259Swollmanstatic int npx_intr(void *); 16221259Swollmanstatic int npx_probe(device_t dev); 16321259Swollman#ifdef I586_CPU_XXX 16421259Swollmanstatic long timezero(const char *funcname, 16521259Swollman void (*func)(void *buf, size_t len)); 16621259Swollman#endif /* I586_CPU */ 16721259Swollman 16821259Swollmanint hw_float; /* XXX currently just alias for npx_exists */ 16921259Swollman 17021259SwollmanSYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD, 17121259Swollman &hw_float, 0, "Floating point instructions executed in hardware"); 17221259Swollman 17321259Swollmanstatic volatile u_int npx_intrs_while_probing; 17421259Swollmanstatic volatile u_int npx_traps_while_probing; 17521259Swollman 17621259Swollmanstatic union savefpu npx_cleanstate; 17721259Swollmanstatic bool_t npx_cleanstate_ready; 17821259Swollmanstatic bool_t npx_ex16; 17921259Swollmanstatic bool_t npx_exists; 18021259Swollmanstatic bool_t npx_irq13; 18121259Swollman 18221259Swollmanalias_for_inthand_t probetrap; 18321259Swollman__asm(" \n\ 18421259Swollman .text \n\ 18521259Swollman .p2align 2,0x90 \n\ 18621259Swollman .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 18721259Swollman" __XSTRING(CNAME(probetrap)) ": \n\ 18821259Swollman ss \n\ 18921259Swollman incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 19021259Swollman fnclex \n\ 19121259Swollman iret \n\ 19221259Swollman"); 19321259Swollman 19421259Swollman/* 19521259Swollman * Identify routine. Create a connection point on our parent for probing. 19621259Swollman */ 19721259Swollmanstatic void 19821259Swollmannpx_identify(driver, parent) 19921259Swollman driver_t *driver; 20021259Swollman device_t parent; 20121259Swollman{ 20221259Swollman device_t child; 20321259Swollman 20421259Swollman child = BUS_ADD_CHILD(parent, 0, "npx", 0); 20521259Swollman if (child == NULL) 20621259Swollman panic("npx_identify"); 20721259Swollman} 20821259Swollman 20921259Swollman/* 21021259Swollman * Do minimal handling of npx interrupts to convert them to traps. 21121259Swollman */ 21221259Swollmanstatic int 21321259Swollmannpx_intr(dummy) 21421259Swollman void *dummy; 21521259Swollman{ 21621259Swollman struct thread *td; 21721259Swollman 21821259Swollman npx_intrs_while_probing++; 21921259Swollman 22021259Swollman /* 22121259Swollman * The BUSY# latch must be cleared in all cases so that the next 22221259Swollman * unmasked npx exception causes an interrupt. 22321259Swollman */ 22421259Swollman outb(IO_NPX, 0); 22521259Swollman 22621259Swollman /* 22721259Swollman * fpcurthread is normally non-null here. In that case, schedule an 22821259Swollman * AST to finish the exception handling in the correct context 22921259Swollman * (this interrupt may occur after the thread has entered the 23021259Swollman * kernel via a syscall or an interrupt). Otherwise, the npx 23121259Swollman * state of the thread that caused this interrupt must have been 23221259Swollman * pushed to the thread's pcb, and clearing of the busy latch 23321259Swollman * above has finished the (essentially null) handling of this 23421259Swollman * interrupt. Control will eventually return to the instruction 23521259Swollman * that caused it and it will repeat. We will eventually (usually 23621259Swollman * soon) win the race to handle the interrupt properly. 23721259Swollman */ 23821259Swollman td = PCPU_GET(fpcurthread); 23921259Swollman if (td != NULL) { 24021259Swollman td->td_pcb->pcb_flags |= PCB_NPXTRAP; 24121259Swollman thread_lock(td); 24221259Swollman td->td_flags |= TDF_ASTPENDING; 24321259Swollman thread_unlock(td); 24421259Swollman } 24521259Swollman return (FILTER_HANDLED); 24621259Swollman} 24721259Swollman 24821259Swollman/* 24921259Swollman * Probe routine. Set flags to tell npxattach() what to do. Set up an 25021259Swollman * interrupt handler if npx needs to use interrupts. 25121259Swollman */ 25221259Swollmanstatic int 25321259Swollmannpx_probe(dev) 25421259Swollman device_t dev; 25521259Swollman{ 25621259Swollman struct gate_descriptor save_idt_npxtrap; 25728845Sjulian struct resource *ioport_res, *irq_res; 25828845Sjulian void *irq_cookie; 25928845Sjulian int ioport_rid, irq_num, irq_rid; 26021259Swollman u_short control; 26121259Swollman u_short status; 26221259Swollman 26321404Swollman device_set_desc(dev, "math processor"); 26421404Swollman 26521404Swollman /* 26621404Swollman * Modern CPUs all have an FPU that uses the INT16 interface 26721404Swollman * and provide a simple way to verify that, so handle the 26821404Swollman * common case right away. 26921404Swollman */ 27021434Swollman if (cpu_feature & CPUID_FPU) { 27121434Swollman hw_float = npx_exists = 1; 27221434Swollman npx_ex16 = 1; 27321434Swollman device_quiet(dev); 27421434Swollman return (0); 27521434Swollman } 27621404Swollman 27721404Swollman save_idt_npxtrap = idt[IDT_MF]; 27821259Swollman setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 27921259Swollman GSEL(GCODE_SEL, SEL_KPL)); 28021259Swollman ioport_rid = 0; 28121259Swollman ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 28221259Swollman IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 28321259Swollman if (ioport_res == NULL) 28421259Swollman panic("npx: can't get ports"); 28521259Swollman if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 28621259Swollman irq_num = IRQ_NPX; 28721259Swollman irq_rid = 0; 28821259Swollman irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 28921259Swollman irq_num, 1, RF_ACTIVE); 29021259Swollman if (irq_res != NULL) { 29121259Swollman if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC, 29221259Swollman npx_intr, NULL, NULL, &irq_cookie) != 0) 29321259Swollman panic("npx: can't create intr"); 29421259Swollman } 29521259Swollman 29621259Swollman /* 29721434Swollman * Partially reset the coprocessor, if any. Some BIOS's don't reset 29821434Swollman * it after a warm boot. 29921404Swollman */ 30021259Swollman npx_full_reset(); 30121404Swollman outb(IO_NPX, 0); 30221259Swollman 30321259Swollman /* 30421259Swollman * Don't trap while we're probing. 30521259Swollman */ 30621259Swollman stop_emulating(); 30721259Swollman 30821259Swollman /* 30921259Swollman * Finish resetting the coprocessor, if any. If there is an error 31021259Swollman * pending, then we may get a bogus IRQ13, but npx_intr() will handle 31121259Swollman * it OK. Bogus halts have never been observed, but we enabled 31221259Swollman * IRQ13 and cleared the BUSY# latch early to handle them anyway. 31321259Swollman */ 31421259Swollman fninit(); 31521259Swollman 31621259Swollman /* 31721259Swollman * Don't use fwait here because it might hang. 31821259Swollman * Don't use fnop here because it usually hangs if there is no FPU. 31921259Swollman */ 32021259Swollman DELAY(1000); /* wait for any IRQ13 */ 32121259Swollman#ifdef DIAGNOSTIC 32221259Swollman if (npx_intrs_while_probing != 0) 32321259Swollman printf("fninit caused %u bogus npx interrupt(s)\n", 32421259Swollman npx_intrs_while_probing); 32521259Swollman if (npx_traps_while_probing != 0) 32621259Swollman printf("fninit caused %u bogus npx trap(s)\n", 32721434Swollman npx_traps_while_probing); 32821434Swollman#endif 32921434Swollman /* 33021259Swollman * Check for a status of mostly zero. 33121259Swollman */ 33221259Swollman status = 0x5a5a; 33321259Swollman fnstsw(&status); 33421259Swollman if ((status & 0xb8ff) == 0) { 33521259Swollman /* 336 * Good, now check for a proper control word. 337 */ 338 control = 0x5a5a; 339 fnstcw(&control); 340 if ((control & 0x1f3f) == 0x033f) { 341 hw_float = npx_exists = 1; 342 /* 343 * We have an npx, now divide by 0 to see if exception 344 * 16 works. 345 */ 346 control &= ~(1 << 2); /* enable divide by 0 trap */ 347 fldcw(&control); 348#ifdef FPU_ERROR_BROKEN 349 /* 350 * FPU error signal doesn't work on some CPU 351 * accelerator board. 352 */ 353 npx_ex16 = 1; 354 return (0); 355#endif 356 npx_traps_while_probing = npx_intrs_while_probing = 0; 357 fp_divide_by_0(); 358 DELAY(1000); /* wait for any IRQ13 */ 359 if (npx_traps_while_probing != 0) { 360 /* 361 * Good, exception 16 works. 362 */ 363 npx_ex16 = 1; 364 goto no_irq13; 365 } 366 if (npx_intrs_while_probing != 0) { 367 /* 368 * Bad, we are stuck with IRQ13. 369 */ 370 npx_irq13 = 1; 371 idt[IDT_MF] = save_idt_npxtrap; 372#ifdef SMP 373 if (mp_ncpus > 1) 374 panic("npx0 cannot use IRQ 13 on an SMP system"); 375#endif 376 return (0); 377 } 378 /* 379 * Worse, even IRQ13 is broken. Use emulator. 380 */ 381 } 382 } 383 /* 384 * Probe failed, but we want to get to npxattach to initialize the 385 * emulator and say that it has been installed. XXX handle devices 386 * that aren't really devices better. 387 */ 388#ifdef SMP 389 if (mp_ncpus > 1) 390 panic("npx0 cannot be emulated on an SMP system"); 391#endif 392 /* FALLTHROUGH */ 393no_irq13: 394 idt[IDT_MF] = save_idt_npxtrap; 395 if (irq_res != NULL) { 396 bus_teardown_intr(dev, irq_res, irq_cookie); 397 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 398 } 399 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 400 return (0); 401} 402 403/* 404 * Attach routine - announce which it is, and wire into system 405 */ 406static int 407npx_attach(dev) 408 device_t dev; 409{ 410 int flags; 411 register_t s; 412 413 flags = device_get_flags(dev); 414 415 if (npx_irq13) 416 device_printf(dev, "IRQ 13 interface\n"); 417 else if (!npx_ex16) 418 device_printf(dev, "WARNING: no FPU!\n"); 419 else if (!device_is_quiet(dev) || bootverbose) 420 device_printf(dev, "INT 16 interface\n"); 421 422 npxinit(__INITIAL_NPXCW__); 423 424 if (npx_cleanstate_ready == 0) { 425 s = intr_disable(); 426 stop_emulating(); 427 fpusave(&npx_cleanstate); 428 start_emulating(); 429#ifdef CPU_ENABLE_SSE 430 if (cpu_fxsr) { 431 if (npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask) 432 cpu_mxcsr_mask = 433 npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask; 434 else 435 cpu_mxcsr_mask = 0xFFBF; 436 } 437#endif 438 npx_cleanstate_ready = 1; 439 intr_restore(s); 440 } 441#ifdef I586_CPU_XXX 442 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 443 timezero("i586_bzero()", i586_bzero) < 444 timezero("bzero()", bzero) * 4 / 5) { 445 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 446 bcopy_vector = i586_bcopy; 447 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 448 bzero_vector = i586_bzero; 449 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 450 copyin_vector = i586_copyin; 451 copyout_vector = i586_copyout; 452 } 453 } 454#endif 455 456 return (0); /* XXX unused */ 457} 458 459/* 460 * Initialize floating point unit. 461 */ 462void 463npxinit(u_short control) 464{ 465 static union savefpu dummy; 466 register_t savecrit; 467 468 if (!npx_exists) 469 return; 470 /* 471 * fninit has the same h/w bugs as fnsave. Use the detoxified 472 * fnsave to throw away any junk in the fpu. npxsave() initializes 473 * the fpu and sets fpcurthread = NULL as important side effects. 474 */ 475 savecrit = intr_disable(); 476 npxsave(&dummy); 477 stop_emulating(); 478#ifdef CPU_ENABLE_SSE 479 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 480 if (cpu_fxsr) 481 fninit(); 482#endif 483 fldcw(&control); 484 start_emulating(); 485 intr_restore(savecrit); 486} 487 488/* 489 * Free coprocessor (if we have it). 490 */ 491void 492npxexit(td) 493 struct thread *td; 494{ 495 register_t savecrit; 496 497 savecrit = intr_disable(); 498 if (curthread == PCPU_GET(fpcurthread)) 499 npxsave(&PCPU_GET(curpcb)->pcb_save); 500 intr_restore(savecrit); 501#ifdef NPX_DEBUG 502 if (npx_exists) { 503 u_int masked_exceptions; 504 505 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 506 /* 507 * Log exceptions that would have trapped with the old 508 * control word (overflow, divide by 0, and invalid operand). 509 */ 510 if (masked_exceptions & 0x0d) 511 log(LOG_ERR, 512 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 513 td->td_proc->p_pid, td->td_proc->p_comm, 514 masked_exceptions); 515 } 516#endif 517} 518 519int 520npxformat() 521{ 522 523 if (!npx_exists) 524 return (_MC_FPFMT_NODEV); 525#ifdef CPU_ENABLE_SSE 526 if (cpu_fxsr) 527 return (_MC_FPFMT_XMM); 528#endif 529 return (_MC_FPFMT_387); 530} 531 532/* 533 * The following mechanism is used to ensure that the FPE_... value 534 * that is passed as a trapcode to the signal handler of the user 535 * process does not have more than one bit set. 536 * 537 * Multiple bits may be set if the user process modifies the control 538 * word while a status word bit is already set. While this is a sign 539 * of bad coding, we have no choise than to narrow them down to one 540 * bit, since we must not send a trapcode that is not exactly one of 541 * the FPE_ macros. 542 * 543 * The mechanism has a static table with 127 entries. Each combination 544 * of the 7 FPU status word exception bits directly translates to a 545 * position in this table, where a single FPE_... value is stored. 546 * This FPE_... value stored there is considered the "most important" 547 * of the exception bits and will be sent as the signal code. The 548 * precedence of the bits is based upon Intel Document "Numerical 549 * Applications", Chapter "Special Computational Situations". 550 * 551 * The macro to choose one of these values does these steps: 1) Throw 552 * away status word bits that cannot be masked. 2) Throw away the bits 553 * currently masked in the control word, assuming the user isn't 554 * interested in them anymore. 3) Reinsert status word bit 7 (stack 555 * fault) if it is set, which cannot be masked but must be presered. 556 * 4) Use the remaining bits to point into the trapcode table. 557 * 558 * The 6 maskable bits in order of their preference, as stated in the 559 * above referenced Intel manual: 560 * 1 Invalid operation (FP_X_INV) 561 * 1a Stack underflow 562 * 1b Stack overflow 563 * 1c Operand of unsupported format 564 * 1d SNaN operand. 565 * 2 QNaN operand (not an exception, irrelavant here) 566 * 3 Any other invalid-operation not mentioned above or zero divide 567 * (FP_X_INV, FP_X_DZ) 568 * 4 Denormal operand (FP_X_DNML) 569 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 570 * 6 Inexact result (FP_X_IMP) 571 */ 572static char fpetable[128] = { 573 0, 574 FPE_FLTINV, /* 1 - INV */ 575 FPE_FLTUND, /* 2 - DNML */ 576 FPE_FLTINV, /* 3 - INV | DNML */ 577 FPE_FLTDIV, /* 4 - DZ */ 578 FPE_FLTINV, /* 5 - INV | DZ */ 579 FPE_FLTDIV, /* 6 - DNML | DZ */ 580 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 581 FPE_FLTOVF, /* 8 - OFL */ 582 FPE_FLTINV, /* 9 - INV | OFL */ 583 FPE_FLTUND, /* A - DNML | OFL */ 584 FPE_FLTINV, /* B - INV | DNML | OFL */ 585 FPE_FLTDIV, /* C - DZ | OFL */ 586 FPE_FLTINV, /* D - INV | DZ | OFL */ 587 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 588 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 589 FPE_FLTUND, /* 10 - UFL */ 590 FPE_FLTINV, /* 11 - INV | UFL */ 591 FPE_FLTUND, /* 12 - DNML | UFL */ 592 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 593 FPE_FLTDIV, /* 14 - DZ | UFL */ 594 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 595 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 596 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 597 FPE_FLTOVF, /* 18 - OFL | UFL */ 598 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 599 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 600 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 601 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 602 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 603 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 604 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 605 FPE_FLTRES, /* 20 - IMP */ 606 FPE_FLTINV, /* 21 - INV | IMP */ 607 FPE_FLTUND, /* 22 - DNML | IMP */ 608 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 609 FPE_FLTDIV, /* 24 - DZ | IMP */ 610 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 611 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 612 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 613 FPE_FLTOVF, /* 28 - OFL | IMP */ 614 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 615 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 616 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 617 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 618 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 619 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 620 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 621 FPE_FLTUND, /* 30 - UFL | IMP */ 622 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 623 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 624 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 625 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 626 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 627 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 628 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 629 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 630 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 631 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 632 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 633 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 634 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 635 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 636 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 637 FPE_FLTSUB, /* 40 - STK */ 638 FPE_FLTSUB, /* 41 - INV | STK */ 639 FPE_FLTUND, /* 42 - DNML | STK */ 640 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 641 FPE_FLTDIV, /* 44 - DZ | STK */ 642 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 643 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 644 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 645 FPE_FLTOVF, /* 48 - OFL | STK */ 646 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 647 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 648 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 649 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 650 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 651 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 652 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 653 FPE_FLTUND, /* 50 - UFL | STK */ 654 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 655 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 656 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 657 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 658 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 659 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 660 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 661 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 662 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 663 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 664 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 665 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 666 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 667 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 668 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 669 FPE_FLTRES, /* 60 - IMP | STK */ 670 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 671 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 672 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 673 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 674 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 675 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 676 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 677 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 678 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 679 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 680 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 681 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 682 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 683 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 684 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 685 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 686 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 687 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 688 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 689 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 691 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 693 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 695 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 697 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 699 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 700 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 701}; 702 703/* 704 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 705 * 706 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 707 * depend on longjmp() restoring a usable state. Restoring the state 708 * or examining it might fail if we didn't clear exceptions. 709 * 710 * The error code chosen will be one of the FPE_... macros. It will be 711 * sent as the second argument to old BSD-style signal handlers and as 712 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 713 * 714 * XXX the FP state is not preserved across signal handlers. So signal 715 * handlers cannot afford to do FP unless they preserve the state or 716 * longjmp() out. Both preserving the state and longjmp()ing may be 717 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 718 * solution for signals other than SIGFPE. 719 */ 720int 721npxtrap() 722{ 723 register_t savecrit; 724 u_short control, status; 725 726 if (!npx_exists) { 727 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 728 PCPU_GET(fpcurthread), curthread, npx_exists); 729 panic("npxtrap from nowhere"); 730 } 731 savecrit = intr_disable(); 732 733 /* 734 * Interrupt handling (for another interrupt) may have pushed the 735 * state to memory. Fetch the relevant parts of the state from 736 * wherever they are. 737 */ 738 if (PCPU_GET(fpcurthread) != curthread) { 739 control = GET_FPU_CW(curthread); 740 status = GET_FPU_SW(curthread); 741 } else { 742 fnstcw(&control); 743 fnstsw(&status); 744 } 745 746 if (PCPU_GET(fpcurthread) == curthread) 747 fnclex(); 748 intr_restore(savecrit); 749 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 750} 751 752/* 753 * Implement device not available (DNA) exception 754 * 755 * It would be better to switch FP context here (if curthread != fpcurthread) 756 * and not necessarily for every context switch, but it is too hard to 757 * access foreign pcb's. 758 */ 759 760static int err_count = 0; 761 762int 763npxdna() 764{ 765 struct pcb *pcb; 766 register_t s; 767#ifdef CPU_ENABLE_SSE 768 int mxcsr; 769#endif 770 u_short control; 771 772 if (!npx_exists) 773 return (0); 774 if (PCPU_GET(fpcurthread) == curthread) { 775 printf("npxdna: fpcurthread == curthread %d times\n", 776 ++err_count); 777 stop_emulating(); 778 return (1); 779 } 780 if (PCPU_GET(fpcurthread) != NULL) { 781 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 782 PCPU_GET(fpcurthread), 783 PCPU_GET(fpcurthread)->td_proc->p_pid, 784 curthread, curthread->td_proc->p_pid); 785 panic("npxdna"); 786 } 787 s = intr_disable(); 788 stop_emulating(); 789 /* 790 * Record new context early in case frstor causes an IRQ13. 791 */ 792 PCPU_SET(fpcurthread, curthread); 793 pcb = PCPU_GET(curpcb); 794 795 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 796 /* 797 * This is the first time this thread has used the FPU or 798 * the PCB doesn't contain a clean FPU state. Explicitly 799 * initialize the FPU and load the default control word. 800 */ 801 fninit(); 802 control = __INITIAL_NPXCW__; 803 fldcw(&control); 804#ifdef CPU_ENABLE_SSE 805 if (cpu_fxsr) { 806 mxcsr = __INITIAL_MXCSR__; 807 ldmxcsr(mxcsr); 808 } 809#endif 810 pcb->pcb_flags |= PCB_NPXINITDONE; 811 } else { 812 /* 813 * The following fpurstor() may cause an IRQ13 when the 814 * state being restored has a pending error. The error will 815 * appear to have been triggered by the current (npx) user 816 * instruction even when that instruction is a no-wait 817 * instruction that should not trigger an error (e.g., 818 * fnclex). On at least one 486 system all of the no-wait 819 * instructions are broken the same as frstor, so our 820 * treatment does not amplify the breakage. On at least 821 * one 386/Cyrix 387 system, fnclex works correctly while 822 * frstor and fnsave are broken, so our treatment breaks 823 * fnclex if it is the first FPU instruction after a context 824 * switch. 825 */ 826 fpurstor(&pcb->pcb_save); 827 } 828 intr_restore(s); 829 830 return (1); 831} 832 833/* 834 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 835 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 836 * no-wait npx instructions. See the Intel application note AP-578 for 837 * details. This doesn't cause any additional complications here. IRQ13's 838 * are inherently asynchronous unless the CPU is frozen to deliver them -- 839 * one that started in userland may be delivered many instructions later, 840 * after the process has entered the kernel. It may even be delivered after 841 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 842 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 843 * it is normally ignored at first because we set fpcurthread to NULL; it is 844 * normally retriggered in npxdna() after return to user mode. 845 * 846 * npxsave() must be called with interrupts disabled, so that it clears 847 * fpcurthread atomically with saving the state. We require callers to do the 848 * disabling, since most callers need to disable interrupts anyway to call 849 * npxsave() atomically with checking fpcurthread. 850 * 851 * A previous version of npxsave() went to great lengths to excecute fnsave 852 * with interrupts enabled in case executing it froze the CPU. This case 853 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 854 * spurious freezes. 855 */ 856void 857npxsave(addr) 858 union savefpu *addr; 859{ 860 861 stop_emulating(); 862 fpusave(addr); 863 864 start_emulating(); 865 PCPU_SET(fpcurthread, NULL); 866} 867 868/* 869 * This should be called with interrupts disabled and only when the owning 870 * FPU thread is non-null. 871 */ 872void 873npxdrop() 874{ 875 struct thread *td; 876 877 /* 878 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 879 * ones don't cause a panic on the next frstor. 880 */ 881#ifdef CPU_ENABLE_SSE 882 if (!cpu_fxsr) 883#endif 884 fnclex(); 885 886 td = PCPU_GET(fpcurthread); 887 PCPU_SET(fpcurthread, NULL); 888 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 889 start_emulating(); 890} 891 892/* 893 * Get the state of the FPU without dropping ownership (if possible). 894 * It returns the FPU ownership status. 895 */ 896int 897npxgetregs(td, addr) 898 struct thread *td; 899 union savefpu *addr; 900{ 901 register_t s; 902 903 if (!npx_exists) 904 return (_MC_FPOWNED_NONE); 905 906 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 907 if (npx_cleanstate_ready) 908 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 909 else 910 bzero(addr, sizeof(*addr)); 911 return (_MC_FPOWNED_NONE); 912 } 913 s = intr_disable(); 914 if (td == PCPU_GET(fpcurthread)) { 915 fpusave(addr); 916#ifdef CPU_ENABLE_SSE 917 if (!cpu_fxsr) 918#endif 919 /* 920 * fnsave initializes the FPU and destroys whatever 921 * context it contains. Make sure the FPU owner 922 * starts with a clean state next time. 923 */ 924 npxdrop(); 925 intr_restore(s); 926 return (_MC_FPOWNED_FPU); 927 } else { 928 intr_restore(s); 929 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 930 return (_MC_FPOWNED_PCB); 931 } 932} 933 934/* 935 * Set the state of the FPU. 936 */ 937void 938npxsetregs(td, addr) 939 struct thread *td; 940 union savefpu *addr; 941{ 942 register_t s; 943 944 if (!npx_exists) 945 return; 946 947 s = intr_disable(); 948 if (td == PCPU_GET(fpcurthread)) { 949#ifdef CPU_ENABLE_SSE 950 if (!cpu_fxsr) 951#endif 952 fnclex(); /* As in npxdrop(). */ 953 fpurstor(addr); 954 intr_restore(s); 955 } else { 956 intr_restore(s); 957 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 958 } 959 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 960} 961 962static void 963fpusave(addr) 964 union savefpu *addr; 965{ 966 967#ifdef CPU_ENABLE_SSE 968 if (cpu_fxsr) 969 fxsave(addr); 970 else 971#endif 972 fnsave(addr); 973} 974 975#ifdef CPU_ENABLE_SSE 976/* 977 * On AuthenticAMD processors, the fxrstor instruction does not restore 978 * the x87's stored last instruction pointer, last data pointer, and last 979 * opcode values, except in the rare case in which the exception summary 980 * (ES) bit in the x87 status word is set to 1. 981 * 982 * In order to avoid leaking this information across processes, we clean 983 * these values by performing a dummy load before executing fxrstor(). 984 */ 985static double dummy_variable = 0.0; 986static void 987fpu_clean_state(void) 988{ 989 u_short status; 990 991 /* 992 * Clear the ES bit in the x87 status word if it is currently 993 * set, in order to avoid causing a fault in the upcoming load. 994 */ 995 fnstsw(&status); 996 if (status & 0x80) 997 fnclex(); 998 999 /* 1000 * Load the dummy variable into the x87 stack. This mangles 1001 * the x87 stack, but we don't care since we're about to call 1002 * fxrstor() anyway. 1003 */ 1004 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 1005} 1006#endif /* CPU_ENABLE_SSE */ 1007 1008static void 1009fpurstor(addr) 1010 union savefpu *addr; 1011{ 1012 1013#ifdef CPU_ENABLE_SSE 1014 if (cpu_fxsr) { 1015 fpu_clean_state(); 1016 fxrstor(addr); 1017 } else 1018#endif 1019 frstor(addr); 1020} 1021 1022#ifdef I586_CPU_XXX 1023static long 1024timezero(funcname, func) 1025 const char *funcname; 1026 void (*func)(void *buf, size_t len); 1027 1028{ 1029 void *buf; 1030#define BUFSIZE 1048576 1031 long usec; 1032 struct timeval finish, start; 1033 1034 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 1035 if (buf == NULL) 1036 return (BUFSIZE); 1037 microtime(&start); 1038 (*func)(buf, BUFSIZE); 1039 microtime(&finish); 1040 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1041 finish.tv_usec - start.tv_usec; 1042 if (usec <= 0) 1043 usec = 1; 1044 if (bootverbose) 1045 printf("%s bandwidth = %u kBps\n", funcname, 1046 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1047 free(buf, M_TEMP); 1048 return (usec); 1049} 1050#endif /* I586_CPU */ 1051 1052static device_method_t npx_methods[] = { 1053 /* Device interface */ 1054 DEVMETHOD(device_identify, npx_identify), 1055 DEVMETHOD(device_probe, npx_probe), 1056 DEVMETHOD(device_attach, npx_attach), 1057 DEVMETHOD(device_detach, bus_generic_detach), 1058 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1059 DEVMETHOD(device_suspend, bus_generic_suspend), 1060 DEVMETHOD(device_resume, bus_generic_resume), 1061 1062 { 0, 0 } 1063}; 1064 1065static driver_t npx_driver = { 1066 "npx", 1067 npx_methods, 1068 1, /* no softc */ 1069}; 1070 1071static devclass_t npx_devclass; 1072 1073/* 1074 * We prefer to attach to the root nexus so that the usual case (exception 16) 1075 * doesn't describe the processor as being `on isa'. 1076 */ 1077DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1078 1079#ifdef DEV_ISA 1080/* 1081 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1082 */ 1083static struct isa_pnp_id npxisa_ids[] = { 1084 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1085 { 0 } 1086}; 1087 1088static int 1089npxisa_probe(device_t dev) 1090{ 1091 int result; 1092 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1093 device_quiet(dev); 1094 } 1095 return(result); 1096} 1097 1098static int 1099npxisa_attach(device_t dev) 1100{ 1101 return (0); 1102} 1103 1104static device_method_t npxisa_methods[] = { 1105 /* Device interface */ 1106 DEVMETHOD(device_probe, npxisa_probe), 1107 DEVMETHOD(device_attach, npxisa_attach), 1108 DEVMETHOD(device_detach, bus_generic_detach), 1109 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1110 DEVMETHOD(device_suspend, bus_generic_suspend), 1111 DEVMETHOD(device_resume, bus_generic_resume), 1112 1113 { 0, 0 } 1114}; 1115 1116static driver_t npxisa_driver = { 1117 "npxisa", 1118 npxisa_methods, 1119 1, /* no softc */ 1120}; 1121 1122static devclass_t npxisa_devclass; 1123 1124DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1125#ifndef PC98 1126DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1127#endif 1128#endif /* DEV_ISA */ 1129