npx.c revision 186557
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 186557 2008-12-29 06:31:03Z kmacy $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58 59#include <machine/asmacros.h> 60#include <machine/cputypes.h> 61#include <machine/frame.h> 62#include <machine/md_var.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#include <machine/resource.h> 66#include <machine/specialreg.h> 67#include <machine/segments.h> 68#include <machine/ucontext.h> 69 70#include <machine/intr_machdep.h> 71#ifdef XEN 72#include <machine/xen/xen-os.h> 73#include <xen/hypervisor.h> 74#endif 75 76#ifdef DEV_ISA 77#include <isa/isavar.h> 78#endif 79 80#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 81#define CPU_ENABLE_SSE 82#endif 83 84/* 85 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 86 */ 87 88/* Configuration flags. */ 89#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 90#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 91#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 92 93#if defined(__GNUCLIKE_ASM) && !defined(lint) 94 95#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 96#define fnclex() __asm("fnclex") 97#define fninit() __asm("fninit") 98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 103#ifdef CPU_ENABLE_SSE 104#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 105#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 106#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 107#endif 108#ifdef XEN 109#define start_emulating() (HYPERVISOR_fpu_taskswitch(1)) 110#define stop_emulating() (HYPERVISOR_fpu_taskswitch(0)) 111#else 112#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 113 : : "n" (CR0_TS) : "ax") 114#define stop_emulating() __asm("clts") 115#endif 116#else /* !(__GNUCLIKE_ASM && !lint) */ 117 118void fldcw(caddr_t addr); 119void fnclex(void); 120void fninit(void); 121void fnsave(caddr_t addr); 122void fnstcw(caddr_t addr); 123void fnstsw(caddr_t addr); 124void fp_divide_by_0(void); 125void frstor(caddr_t addr); 126#ifdef CPU_ENABLE_SSE 127void fxsave(caddr_t addr); 128void fxrstor(caddr_t addr); 129#endif 130void start_emulating(void); 131void stop_emulating(void); 132 133#endif /* __GNUCLIKE_ASM && !lint */ 134 135#ifdef CPU_ENABLE_SSE 136#define GET_FPU_CW(thread) \ 137 (cpu_fxsr ? \ 138 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 139 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 140#define GET_FPU_SW(thread) \ 141 (cpu_fxsr ? \ 142 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 143 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 144#else /* CPU_ENABLE_SSE */ 145#define GET_FPU_CW(thread) \ 146 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 147#define GET_FPU_SW(thread) \ 148 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 149#endif /* CPU_ENABLE_SSE */ 150 151typedef u_char bool_t; 152 153#ifdef CPU_ENABLE_SSE 154static void fpu_clean_state(void); 155#endif 156 157static void fpusave(union savefpu *); 158static void fpurstor(union savefpu *); 159static int npx_attach(device_t dev); 160static void npx_identify(driver_t *driver, device_t parent); 161static int npx_intr(void *); 162static int npx_probe(device_t dev); 163#ifdef I586_CPU_XXX 164static long timezero(const char *funcname, 165 void (*func)(void *buf, size_t len)); 166#endif /* I586_CPU */ 167 168int hw_float; /* XXX currently just alias for npx_exists */ 169 170SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 171 CTLFLAG_RD, &hw_float, 0, 172 "Floatingpoint instructions executed in hardware"); 173 174static volatile u_int npx_intrs_while_probing; 175static volatile u_int npx_traps_while_probing; 176 177static union savefpu npx_cleanstate; 178static bool_t npx_cleanstate_ready; 179static bool_t npx_ex16; 180static bool_t npx_exists; 181static bool_t npx_irq13; 182 183alias_for_inthand_t probetrap; 184__asm(" \n\ 185 .text \n\ 186 .p2align 2,0x90 \n\ 187 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 188" __XSTRING(CNAME(probetrap)) ": \n\ 189 ss \n\ 190 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 191 fnclex \n\ 192 iret \n\ 193"); 194 195/* 196 * Identify routine. Create a connection point on our parent for probing. 197 */ 198static void 199npx_identify(driver, parent) 200 driver_t *driver; 201 device_t parent; 202{ 203 device_t child; 204 205 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 206 if (child == NULL) 207 panic("npx_identify"); 208} 209 210/* 211 * Do minimal handling of npx interrupts to convert them to traps. 212 */ 213static int 214npx_intr(dummy) 215 void *dummy; 216{ 217 struct thread *td; 218 219 npx_intrs_while_probing++; 220 221 /* 222 * The BUSY# latch must be cleared in all cases so that the next 223 * unmasked npx exception causes an interrupt. 224 */ 225 outb(IO_NPX, 0); 226 227 /* 228 * fpcurthread is normally non-null here. In that case, schedule an 229 * AST to finish the exception handling in the correct context 230 * (this interrupt may occur after the thread has entered the 231 * kernel via a syscall or an interrupt). Otherwise, the npx 232 * state of the thread that caused this interrupt must have been 233 * pushed to the thread's pcb, and clearing of the busy latch 234 * above has finished the (essentially null) handling of this 235 * interrupt. Control will eventually return to the instruction 236 * that caused it and it will repeat. We will eventually (usually 237 * soon) win the race to handle the interrupt properly. 238 */ 239 td = PCPU_GET(fpcurthread); 240 if (td != NULL) { 241 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 242 thread_lock(td); 243 td->td_flags |= TDF_ASTPENDING; 244 thread_unlock(td); 245 } 246 return (FILTER_HANDLED); 247} 248 249/* 250 * Probe routine. Set flags to tell npxattach() what to do. Set up an 251 * interrupt handler if npx needs to use interrupts. 252 */ 253static int 254npx_probe(dev) 255 device_t dev; 256{ 257 struct gate_descriptor save_idt_npxtrap; 258 struct resource *ioport_res, *irq_res; 259 void *irq_cookie; 260 int ioport_rid, irq_num, irq_rid; 261 u_short control; 262 u_short status; 263 264 device_set_desc(dev, "math processor"); 265 266 /* 267 * Modern CPUs all have an FPU that uses the INT16 interface 268 * and provide a simple way to verify that, so handle the 269 * common case right away. 270 */ 271 if (cpu_feature & CPUID_FPU) { 272 hw_float = npx_exists = 1; 273 npx_ex16 = 1; 274 device_quiet(dev); 275 return (0); 276 } 277 278 save_idt_npxtrap = idt[IDT_MF]; 279 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 280 GSEL(GCODE_SEL, SEL_KPL)); 281 ioport_rid = 0; 282 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 283 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 284 if (ioport_res == NULL) 285 panic("npx: can't get ports"); 286 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 287 irq_num = IRQ_NPX; 288 irq_rid = 0; 289 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 290 irq_num, 1, RF_ACTIVE); 291 if (irq_res != NULL) { 292 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC, 293 npx_intr, NULL, NULL, &irq_cookie) != 0) 294 panic("npx: can't create intr"); 295 } 296 297 /* 298 * Partially reset the coprocessor, if any. Some BIOS's don't reset 299 * it after a warm boot. 300 */ 301 npx_full_reset(); 302 outb(IO_NPX, 0); 303 304 /* 305 * Don't trap while we're probing. 306 */ 307 stop_emulating(); 308 309 /* 310 * Finish resetting the coprocessor, if any. If there is an error 311 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 312 * it OK. Bogus halts have never been observed, but we enabled 313 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 314 */ 315 fninit(); 316 317 /* 318 * Don't use fwait here because it might hang. 319 * Don't use fnop here because it usually hangs if there is no FPU. 320 */ 321 DELAY(1000); /* wait for any IRQ13 */ 322#ifdef DIAGNOSTIC 323 if (npx_intrs_while_probing != 0) 324 printf("fninit caused %u bogus npx interrupt(s)\n", 325 npx_intrs_while_probing); 326 if (npx_traps_while_probing != 0) 327 printf("fninit caused %u bogus npx trap(s)\n", 328 npx_traps_while_probing); 329#endif 330 /* 331 * Check for a status of mostly zero. 332 */ 333 status = 0x5a5a; 334 fnstsw(&status); 335 if ((status & 0xb8ff) == 0) { 336 /* 337 * Good, now check for a proper control word. 338 */ 339 control = 0x5a5a; 340 fnstcw(&control); 341 if ((control & 0x1f3f) == 0x033f) { 342 hw_float = npx_exists = 1; 343 /* 344 * We have an npx, now divide by 0 to see if exception 345 * 16 works. 346 */ 347 control &= ~(1 << 2); /* enable divide by 0 trap */ 348 fldcw(&control); 349#ifdef FPU_ERROR_BROKEN 350 /* 351 * FPU error signal doesn't work on some CPU 352 * accelerator board. 353 */ 354 npx_ex16 = 1; 355 return (0); 356#endif 357 npx_traps_while_probing = npx_intrs_while_probing = 0; 358 fp_divide_by_0(); 359 DELAY(1000); /* wait for any IRQ13 */ 360 if (npx_traps_while_probing != 0) { 361 /* 362 * Good, exception 16 works. 363 */ 364 npx_ex16 = 1; 365 goto no_irq13; 366 } 367 if (npx_intrs_while_probing != 0) { 368 /* 369 * Bad, we are stuck with IRQ13. 370 */ 371 npx_irq13 = 1; 372 idt[IDT_MF] = save_idt_npxtrap; 373#ifdef SMP 374 if (mp_ncpus > 1) 375 panic("npx0 cannot use IRQ 13 on an SMP system"); 376#endif 377 return (0); 378 } 379 /* 380 * Worse, even IRQ13 is broken. Use emulator. 381 */ 382 } 383 } 384 /* 385 * Probe failed, but we want to get to npxattach to initialize the 386 * emulator and say that it has been installed. XXX handle devices 387 * that aren't really devices better. 388 */ 389#ifdef SMP 390 if (mp_ncpus > 1) 391 panic("npx0 cannot be emulated on an SMP system"); 392#endif 393 /* FALLTHROUGH */ 394no_irq13: 395 idt[IDT_MF] = save_idt_npxtrap; 396 if (irq_res != NULL) { 397 bus_teardown_intr(dev, irq_res, irq_cookie); 398 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 399 } 400 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 401 return (0); 402} 403 404/* 405 * Attach routine - announce which it is, and wire into system 406 */ 407static int 408npx_attach(dev) 409 device_t dev; 410{ 411 int flags; 412 register_t s; 413 414 flags = device_get_flags(dev); 415 416 if (npx_irq13) 417 device_printf(dev, "IRQ 13 interface\n"); 418 else if (!npx_ex16) 419 device_printf(dev, "WARNING: no FPU!\n"); 420 else if (!device_is_quiet(dev) || bootverbose) 421 device_printf(dev, "INT 16 interface\n"); 422 423 npxinit(__INITIAL_NPXCW__); 424 425 if (npx_cleanstate_ready == 0) { 426 s = intr_disable(); 427 stop_emulating(); 428 fpusave(&npx_cleanstate); 429 start_emulating(); 430#ifdef CPU_ENABLE_SSE 431 if (cpu_fxsr) { 432 if (npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask) 433 cpu_mxcsr_mask = 434 npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask; 435 else 436 cpu_mxcsr_mask = 0xFFBF; 437 } 438#endif 439 npx_cleanstate_ready = 1; 440 intr_restore(s); 441 } 442#ifdef I586_CPU_XXX 443 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 444 timezero("i586_bzero()", i586_bzero) < 445 timezero("bzero()", bzero) * 4 / 5) { 446 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 447 bcopy_vector = i586_bcopy; 448 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 449 bzero_vector = i586_bzero; 450 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 451 copyin_vector = i586_copyin; 452 copyout_vector = i586_copyout; 453 } 454 } 455#endif 456 457 return (0); /* XXX unused */ 458} 459 460/* 461 * Initialize floating point unit. 462 */ 463void 464npxinit(control) 465 u_short control; 466{ 467 static union savefpu dummy; 468 register_t savecrit; 469 470 if (!npx_exists) 471 return; 472 /* 473 * fninit has the same h/w bugs as fnsave. Use the detoxified 474 * fnsave to throw away any junk in the fpu. npxsave() initializes 475 * the fpu and sets fpcurthread = NULL as important side effects. 476 */ 477 savecrit = intr_disable(); 478 npxsave(&dummy); 479 stop_emulating(); 480#ifdef CPU_ENABLE_SSE 481 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 482 if (cpu_fxsr) 483 fninit(); 484#endif 485 fldcw(&control); 486 start_emulating(); 487 intr_restore(savecrit); 488} 489 490/* 491 * Free coprocessor (if we have it). 492 */ 493void 494npxexit(td) 495 struct thread *td; 496{ 497 register_t savecrit; 498 499 savecrit = intr_disable(); 500 if (curthread == PCPU_GET(fpcurthread)) 501 npxsave(&PCPU_GET(curpcb)->pcb_save); 502 intr_restore(savecrit); 503#ifdef NPX_DEBUG 504 if (npx_exists) { 505 u_int masked_exceptions; 506 507 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 508 /* 509 * Log exceptions that would have trapped with the old 510 * control word (overflow, divide by 0, and invalid operand). 511 */ 512 if (masked_exceptions & 0x0d) 513 log(LOG_ERR, 514 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 515 td->td_proc->p_pid, td->td_proc->p_comm, 516 masked_exceptions); 517 } 518#endif 519} 520 521int 522npxformat() 523{ 524 525 if (!npx_exists) 526 return (_MC_FPFMT_NODEV); 527#ifdef CPU_ENABLE_SSE 528 if (cpu_fxsr) 529 return (_MC_FPFMT_XMM); 530#endif 531 return (_MC_FPFMT_387); 532} 533 534/* 535 * The following mechanism is used to ensure that the FPE_... value 536 * that is passed as a trapcode to the signal handler of the user 537 * process does not have more than one bit set. 538 * 539 * Multiple bits may be set if the user process modifies the control 540 * word while a status word bit is already set. While this is a sign 541 * of bad coding, we have no choise than to narrow them down to one 542 * bit, since we must not send a trapcode that is not exactly one of 543 * the FPE_ macros. 544 * 545 * The mechanism has a static table with 127 entries. Each combination 546 * of the 7 FPU status word exception bits directly translates to a 547 * position in this table, where a single FPE_... value is stored. 548 * This FPE_... value stored there is considered the "most important" 549 * of the exception bits and will be sent as the signal code. The 550 * precedence of the bits is based upon Intel Document "Numerical 551 * Applications", Chapter "Special Computational Situations". 552 * 553 * The macro to choose one of these values does these steps: 1) Throw 554 * away status word bits that cannot be masked. 2) Throw away the bits 555 * currently masked in the control word, assuming the user isn't 556 * interested in them anymore. 3) Reinsert status word bit 7 (stack 557 * fault) if it is set, which cannot be masked but must be presered. 558 * 4) Use the remaining bits to point into the trapcode table. 559 * 560 * The 6 maskable bits in order of their preference, as stated in the 561 * above referenced Intel manual: 562 * 1 Invalid operation (FP_X_INV) 563 * 1a Stack underflow 564 * 1b Stack overflow 565 * 1c Operand of unsupported format 566 * 1d SNaN operand. 567 * 2 QNaN operand (not an exception, irrelavant here) 568 * 3 Any other invalid-operation not mentioned above or zero divide 569 * (FP_X_INV, FP_X_DZ) 570 * 4 Denormal operand (FP_X_DNML) 571 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 572 * 6 Inexact result (FP_X_IMP) 573 */ 574static char fpetable[128] = { 575 0, 576 FPE_FLTINV, /* 1 - INV */ 577 FPE_FLTUND, /* 2 - DNML */ 578 FPE_FLTINV, /* 3 - INV | DNML */ 579 FPE_FLTDIV, /* 4 - DZ */ 580 FPE_FLTINV, /* 5 - INV | DZ */ 581 FPE_FLTDIV, /* 6 - DNML | DZ */ 582 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 583 FPE_FLTOVF, /* 8 - OFL */ 584 FPE_FLTINV, /* 9 - INV | OFL */ 585 FPE_FLTUND, /* A - DNML | OFL */ 586 FPE_FLTINV, /* B - INV | DNML | OFL */ 587 FPE_FLTDIV, /* C - DZ | OFL */ 588 FPE_FLTINV, /* D - INV | DZ | OFL */ 589 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 590 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 591 FPE_FLTUND, /* 10 - UFL */ 592 FPE_FLTINV, /* 11 - INV | UFL */ 593 FPE_FLTUND, /* 12 - DNML | UFL */ 594 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 595 FPE_FLTDIV, /* 14 - DZ | UFL */ 596 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 597 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 598 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 599 FPE_FLTOVF, /* 18 - OFL | UFL */ 600 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 601 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 602 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 603 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 604 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 605 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 606 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 607 FPE_FLTRES, /* 20 - IMP */ 608 FPE_FLTINV, /* 21 - INV | IMP */ 609 FPE_FLTUND, /* 22 - DNML | IMP */ 610 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 611 FPE_FLTDIV, /* 24 - DZ | IMP */ 612 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 613 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 614 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 615 FPE_FLTOVF, /* 28 - OFL | IMP */ 616 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 617 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 618 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 619 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 620 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 621 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 622 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 623 FPE_FLTUND, /* 30 - UFL | IMP */ 624 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 625 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 626 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 627 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 628 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 629 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 630 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 631 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 632 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 633 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 634 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 635 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 636 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 637 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 638 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 639 FPE_FLTSUB, /* 40 - STK */ 640 FPE_FLTSUB, /* 41 - INV | STK */ 641 FPE_FLTUND, /* 42 - DNML | STK */ 642 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 643 FPE_FLTDIV, /* 44 - DZ | STK */ 644 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 645 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 646 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 647 FPE_FLTOVF, /* 48 - OFL | STK */ 648 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 649 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 650 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 651 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 652 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 653 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 654 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 655 FPE_FLTUND, /* 50 - UFL | STK */ 656 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 657 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 658 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 659 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 660 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 661 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 662 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 663 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 664 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 665 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 666 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 667 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 668 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 669 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 670 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 671 FPE_FLTRES, /* 60 - IMP | STK */ 672 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 673 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 674 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 675 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 676 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 677 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 678 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 679 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 680 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 681 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 682 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 683 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 684 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 685 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 686 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 687 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 688 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 689 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 691 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 693 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 695 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 697 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 699 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 700 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 701 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 702 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 703}; 704 705/* 706 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 707 * 708 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 709 * depend on longjmp() restoring a usable state. Restoring the state 710 * or examining it might fail if we didn't clear exceptions. 711 * 712 * The error code chosen will be one of the FPE_... macros. It will be 713 * sent as the second argument to old BSD-style signal handlers and as 714 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 715 * 716 * XXX the FP state is not preserved across signal handlers. So signal 717 * handlers cannot afford to do FP unless they preserve the state or 718 * longjmp() out. Both preserving the state and longjmp()ing may be 719 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 720 * solution for signals other than SIGFPE. 721 */ 722int 723npxtrap() 724{ 725 register_t savecrit; 726 u_short control, status; 727 728 if (!npx_exists) { 729 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 730 PCPU_GET(fpcurthread), curthread, npx_exists); 731 panic("npxtrap from nowhere"); 732 } 733 savecrit = intr_disable(); 734 735 /* 736 * Interrupt handling (for another interrupt) may have pushed the 737 * state to memory. Fetch the relevant parts of the state from 738 * wherever they are. 739 */ 740 if (PCPU_GET(fpcurthread) != curthread) { 741 control = GET_FPU_CW(curthread); 742 status = GET_FPU_SW(curthread); 743 } else { 744 fnstcw(&control); 745 fnstsw(&status); 746 } 747 748 if (PCPU_GET(fpcurthread) == curthread) 749 fnclex(); 750 intr_restore(savecrit); 751 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 752} 753 754/* 755 * Implement device not available (DNA) exception 756 * 757 * It would be better to switch FP context here (if curthread != fpcurthread) 758 * and not necessarily for every context switch, but it is too hard to 759 * access foreign pcb's. 760 */ 761 762static int err_count = 0; 763 764int 765npxdna() 766{ 767 struct pcb *pcb; 768 register_t s; 769#ifdef CPU_ENABLE_SSE 770 int mxcsr; 771#endif 772 u_short control; 773 774 if (!npx_exists) 775 return (0); 776 if (PCPU_GET(fpcurthread) == curthread) { 777 printf("npxdna: fpcurthread == curthread %d times\n", 778 ++err_count); 779 stop_emulating(); 780 return (1); 781 } 782 if (PCPU_GET(fpcurthread) != NULL) { 783 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 784 PCPU_GET(fpcurthread), 785 PCPU_GET(fpcurthread)->td_proc->p_pid, 786 curthread, curthread->td_proc->p_pid); 787 panic("npxdna"); 788 } 789 s = intr_disable(); 790 stop_emulating(); 791 /* 792 * Record new context early in case frstor causes an IRQ13. 793 */ 794 PCPU_SET(fpcurthread, curthread); 795 pcb = PCPU_GET(curpcb); 796 797 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 798 /* 799 * This is the first time this thread has used the FPU or 800 * the PCB doesn't contain a clean FPU state. Explicitly 801 * initialize the FPU and load the default control word. 802 */ 803 fninit(); 804 control = __INITIAL_NPXCW__; 805 fldcw(&control); 806#ifdef CPU_ENABLE_SSE 807 if (cpu_fxsr) { 808 mxcsr = __INITIAL_MXCSR__; 809 ldmxcsr(mxcsr); 810 } 811#endif 812 pcb->pcb_flags |= PCB_NPXINITDONE; 813 } else { 814 /* 815 * The following frstor may cause an IRQ13 when the state 816 * being restored has a pending error. The error will 817 * appear to have been triggered by the current (npx) user 818 * instruction even when that instruction is a no-wait 819 * instruction that should not trigger an error (e.g., 820 * fnclex). On at least one 486 system all of the no-wait 821 * instructions are broken the same as frstor, so our 822 * treatment does not amplify the breakage. On at least 823 * one 386/Cyrix 387 system, fnclex works correctly while 824 * frstor and fnsave are broken, so our treatment breaks 825 * fnclex if it is the first FPU instruction after a context 826 * switch. 827 */ 828 fpurstor(&pcb->pcb_save); 829 } 830 intr_restore(s); 831 832 return (1); 833} 834 835/* 836 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 837 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 838 * no-wait npx instructions. See the Intel application note AP-578 for 839 * details. This doesn't cause any additional complications here. IRQ13's 840 * are inherently asynchronous unless the CPU is frozen to deliver them -- 841 * one that started in userland may be delivered many instructions later, 842 * after the process has entered the kernel. It may even be delivered after 843 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 844 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 845 * it is normally ignored at first because we set fpcurthread to NULL; it is 846 * normally retriggered in npxdna() after return to user mode. 847 * 848 * npxsave() must be called with interrupts disabled, so that it clears 849 * fpcurthread atomically with saving the state. We require callers to do the 850 * disabling, since most callers need to disable interrupts anyway to call 851 * npxsave() atomically with checking fpcurthread. 852 * 853 * A previous version of npxsave() went to great lengths to excecute fnsave 854 * with interrupts enabled in case executing it froze the CPU. This case 855 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 856 * spurious freezes. 857 */ 858void 859npxsave(addr) 860 union savefpu *addr; 861{ 862 863 stop_emulating(); 864 fpusave(addr); 865 866 start_emulating(); 867 PCPU_SET(fpcurthread, NULL); 868} 869 870/* 871 * This should be called with interrupts disabled and only when the owning 872 * FPU thread is non-null. 873 */ 874void 875npxdrop() 876{ 877 struct thread *td; 878 879 /* 880 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 881 * ones don't cause a panic on the next frstor. 882 */ 883#ifdef CPU_ENABLE_SSE 884 if (!cpu_fxsr) 885#endif 886 fnclex(); 887 888 td = PCPU_GET(fpcurthread); 889 PCPU_SET(fpcurthread, NULL); 890 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 891 start_emulating(); 892} 893 894/* 895 * Get the state of the FPU without dropping ownership (if possible). 896 * It returns the FPU ownership status. 897 */ 898int 899npxgetregs(td, addr) 900 struct thread *td; 901 union savefpu *addr; 902{ 903 register_t s; 904 905 if (!npx_exists) 906 return (_MC_FPOWNED_NONE); 907 908 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 909 if (npx_cleanstate_ready) 910 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 911 else 912 bzero(addr, sizeof(*addr)); 913 return (_MC_FPOWNED_NONE); 914 } 915 s = intr_disable(); 916 if (td == PCPU_GET(fpcurthread)) { 917 fpusave(addr); 918#ifdef CPU_ENABLE_SSE 919 if (!cpu_fxsr) 920#endif 921 /* 922 * fnsave initializes the FPU and destroys whatever 923 * context it contains. Make sure the FPU owner 924 * starts with a clean state next time. 925 */ 926 npxdrop(); 927 intr_restore(s); 928 return (_MC_FPOWNED_FPU); 929 } else { 930 intr_restore(s); 931 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 932 return (_MC_FPOWNED_PCB); 933 } 934} 935 936/* 937 * Set the state of the FPU. 938 */ 939void 940npxsetregs(td, addr) 941 struct thread *td; 942 union savefpu *addr; 943{ 944 register_t s; 945 946 if (!npx_exists) 947 return; 948 949 s = intr_disable(); 950 if (td == PCPU_GET(fpcurthread)) { 951#ifdef CPU_ENABLE_SSE 952 if (!cpu_fxsr) 953#endif 954 fnclex(); /* As in npxdrop(). */ 955 fpurstor(addr); 956 intr_restore(s); 957 } else { 958 intr_restore(s); 959 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 960 } 961 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 962} 963 964static void 965fpusave(addr) 966 union savefpu *addr; 967{ 968 969#ifdef CPU_ENABLE_SSE 970 if (cpu_fxsr) 971 fxsave(addr); 972 else 973#endif 974 fnsave(addr); 975} 976 977#ifdef CPU_ENABLE_SSE 978/* 979 * On AuthenticAMD processors, the fxrstor instruction does not restore 980 * the x87's stored last instruction pointer, last data pointer, and last 981 * opcode values, except in the rare case in which the exception summary 982 * (ES) bit in the x87 status word is set to 1. 983 * 984 * In order to avoid leaking this information across processes, we clean 985 * these values by performing a dummy load before executing fxrstor(). 986 */ 987static double dummy_variable = 0.0; 988static void 989fpu_clean_state(void) 990{ 991 u_short status; 992 993 /* 994 * Clear the ES bit in the x87 status word if it is currently 995 * set, in order to avoid causing a fault in the upcoming load. 996 */ 997 fnstsw(&status); 998 if (status & 0x80) 999 fnclex(); 1000 1001 /* 1002 * Load the dummy variable into the x87 stack. This mangles 1003 * the x87 stack, but we don't care since we're about to call 1004 * fxrstor() anyway. 1005 */ 1006 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable)); 1007} 1008#endif /* CPU_ENABLE_SSE */ 1009 1010static void 1011fpurstor(addr) 1012 union savefpu *addr; 1013{ 1014 1015#ifdef CPU_ENABLE_SSE 1016 if (cpu_fxsr) { 1017 fpu_clean_state(); 1018 fxrstor(addr); 1019 } else 1020#endif 1021 frstor(addr); 1022} 1023 1024#ifdef I586_CPU_XXX 1025static long 1026timezero(funcname, func) 1027 const char *funcname; 1028 void (*func)(void *buf, size_t len); 1029 1030{ 1031 void *buf; 1032#define BUFSIZE 1048576 1033 long usec; 1034 struct timeval finish, start; 1035 1036 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 1037 if (buf == NULL) 1038 return (BUFSIZE); 1039 microtime(&start); 1040 (*func)(buf, BUFSIZE); 1041 microtime(&finish); 1042 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1043 finish.tv_usec - start.tv_usec; 1044 if (usec <= 0) 1045 usec = 1; 1046 if (bootverbose) 1047 printf("%s bandwidth = %u kBps\n", funcname, 1048 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1049 free(buf, M_TEMP); 1050 return (usec); 1051} 1052#endif /* I586_CPU */ 1053 1054static device_method_t npx_methods[] = { 1055 /* Device interface */ 1056 DEVMETHOD(device_identify, npx_identify), 1057 DEVMETHOD(device_probe, npx_probe), 1058 DEVMETHOD(device_attach, npx_attach), 1059 DEVMETHOD(device_detach, bus_generic_detach), 1060 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1061 DEVMETHOD(device_suspend, bus_generic_suspend), 1062 DEVMETHOD(device_resume, bus_generic_resume), 1063 1064 { 0, 0 } 1065}; 1066 1067static driver_t npx_driver = { 1068 "npx", 1069 npx_methods, 1070 1, /* no softc */ 1071}; 1072 1073static devclass_t npx_devclass; 1074 1075/* 1076 * We prefer to attach to the root nexus so that the usual case (exception 16) 1077 * doesn't describe the processor as being `on isa'. 1078 */ 1079DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1080 1081#ifdef DEV_ISA 1082/* 1083 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1084 */ 1085static struct isa_pnp_id npxisa_ids[] = { 1086 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1087 { 0 } 1088}; 1089 1090static int 1091npxisa_probe(device_t dev) 1092{ 1093 int result; 1094 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1095 device_quiet(dev); 1096 } 1097 return(result); 1098} 1099 1100static int 1101npxisa_attach(device_t dev) 1102{ 1103 return (0); 1104} 1105 1106static device_method_t npxisa_methods[] = { 1107 /* Device interface */ 1108 DEVMETHOD(device_probe, npxisa_probe), 1109 DEVMETHOD(device_attach, npxisa_attach), 1110 DEVMETHOD(device_detach, bus_generic_detach), 1111 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1112 DEVMETHOD(device_suspend, bus_generic_suspend), 1113 DEVMETHOD(device_resume, bus_generic_resume), 1114 1115 { 0, 0 } 1116}; 1117 1118static driver_t npxisa_driver = { 1119 "npxisa", 1120 npxisa_methods, 1121 1, /* no softc */ 1122}; 1123 1124static devclass_t npxisa_devclass; 1125 1126DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1127#ifndef PC98 1128DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1129#endif 1130#endif /* DEV_ISA */ 1131