npx.c revision 147741
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 147741 2005-07-02 20:06:44Z delphij $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58 59#include <machine/asmacros.h> 60#include <machine/cputypes.h> 61#include <machine/frame.h> 62#include <machine/md_var.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#include <machine/clock.h> 66#include <machine/resource.h> 67#include <machine/specialreg.h> 68#include <machine/segments.h> 69#include <machine/ucontext.h> 70 71#include <machine/intr_machdep.h> 72#ifdef DEV_ISA 73#include <isa/isavar.h> 74#endif 75 76#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 77#define CPU_ENABLE_SSE 78#endif 79 80/* 81 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 82 */ 83 84/* Configuration flags. */ 85#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 86#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 87#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 88 89#if defined(__GNUCLIKE_ASM) && !defined(lint) 90 91#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 92#define fnclex() __asm("fnclex") 93#define fninit() __asm("fninit") 94#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 95#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 96#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 97#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 98#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 99#ifdef CPU_ENABLE_SSE 100#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 101#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 102#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 103#endif 104#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 105 : : "n" (CR0_TS) : "ax") 106#define stop_emulating() __asm("clts") 107 108#else /* !(__GNUCLIKE_ASM && !lint) */ 109 110void fldcw(caddr_t addr); 111void fnclex(void); 112void fninit(void); 113void fnsave(caddr_t addr); 114void fnstcw(caddr_t addr); 115void fnstsw(caddr_t addr); 116void fp_divide_by_0(void); 117void frstor(caddr_t addr); 118#ifdef CPU_ENABLE_SSE 119void fxsave(caddr_t addr); 120void fxrstor(caddr_t addr); 121#endif 122void start_emulating(void); 123void stop_emulating(void); 124 125#endif /* __GNUCLIKE_ASM && !lint */ 126 127#ifdef CPU_ENABLE_SSE 128#define GET_FPU_CW(thread) \ 129 (cpu_fxsr ? \ 130 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 131 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 132#define GET_FPU_SW(thread) \ 133 (cpu_fxsr ? \ 134 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 135 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 136#else /* CPU_ENABLE_SSE */ 137#define GET_FPU_CW(thread) \ 138 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 139#define GET_FPU_SW(thread) \ 140 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 141#endif /* CPU_ENABLE_SSE */ 142 143typedef u_char bool_t; 144 145static void fpusave(union savefpu *); 146static void fpurstor(union savefpu *); 147static int npx_attach(device_t dev); 148static void npx_identify(driver_t *driver, device_t parent); 149static void npx_intr(void *); 150static int npx_probe(device_t dev); 151#ifdef I586_CPU_XXX 152static long timezero(const char *funcname, 153 void (*func)(void *buf, size_t len)); 154#endif /* I586_CPU */ 155 156int hw_float; /* XXX currently just alias for npx_exists */ 157 158SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 159 CTLFLAG_RD, &hw_float, 0, 160 "Floatingpoint instructions executed in hardware"); 161 162static volatile u_int npx_intrs_while_probing; 163static volatile u_int npx_traps_while_probing; 164 165static union savefpu npx_cleanstate; 166static bool_t npx_cleanstate_ready; 167static bool_t npx_ex16; 168static bool_t npx_exists; 169static bool_t npx_irq13; 170 171alias_for_inthand_t probetrap; 172__asm(" \n\ 173 .text \n\ 174 .p2align 2,0x90 \n\ 175 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 176" __XSTRING(CNAME(probetrap)) ": \n\ 177 ss \n\ 178 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 179 fnclex \n\ 180 iret \n\ 181"); 182 183/* 184 * Identify routine. Create a connection point on our parent for probing. 185 */ 186static void 187npx_identify(driver, parent) 188 driver_t *driver; 189 device_t parent; 190{ 191 device_t child; 192 193 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 194 if (child == NULL) 195 panic("npx_identify"); 196} 197 198/* 199 * Do minimal handling of npx interrupts to convert them to traps. 200 */ 201static void 202npx_intr(dummy) 203 void *dummy; 204{ 205 struct thread *td; 206 207 npx_intrs_while_probing++; 208 209 /* 210 * The BUSY# latch must be cleared in all cases so that the next 211 * unmasked npx exception causes an interrupt. 212 */ 213 outb(IO_NPX, 0); 214 215 /* 216 * fpcurthread is normally non-null here. In that case, schedule an 217 * AST to finish the exception handling in the correct context 218 * (this interrupt may occur after the thread has entered the 219 * kernel via a syscall or an interrupt). Otherwise, the npx 220 * state of the thread that caused this interrupt must have been 221 * pushed to the thread's pcb, and clearing of the busy latch 222 * above has finished the (essentially null) handling of this 223 * interrupt. Control will eventually return to the instruction 224 * that caused it and it will repeat. We will eventually (usually 225 * soon) win the race to handle the interrupt properly. 226 */ 227 td = PCPU_GET(fpcurthread); 228 if (td != NULL) { 229 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 230 mtx_lock_spin(&sched_lock); 231 td->td_flags |= TDF_ASTPENDING; 232 mtx_unlock_spin(&sched_lock); 233 } 234} 235 236/* 237 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 238 * whether the device exists or not (XXX should be elsewhere). Set flags 239 * to tell npxattach() what to do. Modify device struct if npx doesn't 240 * need to use interrupts. Return 0 if device exists. 241 */ 242static int 243npx_probe(dev) 244 device_t dev; 245{ 246 struct gate_descriptor save_idt_npxtrap; 247 struct resource *ioport_res, *irq_res; 248 void *irq_cookie; 249 int ioport_rid, irq_num, irq_rid; 250 u_short control; 251 u_short status; 252 253 save_idt_npxtrap = idt[IDT_MF]; 254 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 255 GSEL(GCODE_SEL, SEL_KPL)); 256 ioport_rid = 0; 257 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 258 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 259 if (ioport_res == NULL) 260 panic("npx: can't get ports"); 261 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 262 irq_num = IRQ_NPX; 263 irq_rid = 0; 264 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 265 irq_num, 1, RF_ACTIVE); 266 if (irq_res == NULL) 267 panic("npx: can't get IRQ"); 268 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 269 NULL, &irq_cookie) != 0) 270 panic("npx: can't create intr"); 271 272 /* 273 * Partially reset the coprocessor, if any. Some BIOS's don't reset 274 * it after a warm boot. 275 */ 276 npx_full_reset(); 277 outb(IO_NPX, 0); 278 279 /* 280 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 281 * instructions. We must set the CR0_MP bit and use the CR0_TS 282 * bit to control the trap, because setting the CR0_EM bit does 283 * not cause WAIT instructions to trap. It's important to trap 284 * WAIT instructions - otherwise the "wait" variants of no-wait 285 * control instructions would degenerate to the "no-wait" variants 286 * after FP context switches but work correctly otherwise. It's 287 * particularly important to trap WAITs when there is no NPX - 288 * otherwise the "wait" variants would always degenerate. 289 * 290 * Try setting CR0_NE to get correct error reporting on 486DX's. 291 * Setting it should fail or do nothing on lesser processors. 292 */ 293 load_cr0(rcr0() | CR0_MP | CR0_NE); 294 /* 295 * But don't trap while we're probing. 296 */ 297 stop_emulating(); 298 /* 299 * Finish resetting the coprocessor, if any. If there is an error 300 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 301 * it OK. Bogus halts have never been observed, but we enabled 302 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 303 */ 304 fninit(); 305 306 device_set_desc(dev, "math processor"); 307 308 /* 309 * Don't use fwait here because it might hang. 310 * Don't use fnop here because it usually hangs if there is no FPU. 311 */ 312 DELAY(1000); /* wait for any IRQ13 */ 313#ifdef DIAGNOSTIC 314 if (npx_intrs_while_probing != 0) 315 printf("fninit caused %u bogus npx interrupt(s)\n", 316 npx_intrs_while_probing); 317 if (npx_traps_while_probing != 0) 318 printf("fninit caused %u bogus npx trap(s)\n", 319 npx_traps_while_probing); 320#endif 321 /* 322 * Check for a status of mostly zero. 323 */ 324 status = 0x5a5a; 325 fnstsw(&status); 326 if ((status & 0xb8ff) == 0) { 327 /* 328 * Good, now check for a proper control word. 329 */ 330 control = 0x5a5a; 331 fnstcw(&control); 332 if ((control & 0x1f3f) == 0x033f) { 333 hw_float = npx_exists = 1; 334 /* 335 * We have an npx, now divide by 0 to see if exception 336 * 16 works. 337 */ 338 control &= ~(1 << 2); /* enable divide by 0 trap */ 339 fldcw(&control); 340#ifdef FPU_ERROR_BROKEN 341 /* 342 * FPU error signal doesn't work on some CPU 343 * accelerator board. 344 */ 345 npx_ex16 = 1; 346 return (0); 347#endif 348 npx_traps_while_probing = npx_intrs_while_probing = 0; 349 fp_divide_by_0(); 350 DELAY(1000); /* wait for any IRQ13 */ 351 if (npx_traps_while_probing != 0) { 352 /* 353 * Good, exception 16 works. 354 */ 355 npx_ex16 = 1; 356 goto no_irq13; 357 } 358 if (npx_intrs_while_probing != 0) { 359 /* 360 * Bad, we are stuck with IRQ13. 361 */ 362 npx_irq13 = 1; 363 idt[IDT_MF] = save_idt_npxtrap; 364#ifdef SMP 365 if (mp_ncpus > 1) 366 panic("npx0 cannot use IRQ 13 on an SMP system"); 367#endif 368 return (0); 369 } 370 /* 371 * Worse, even IRQ13 is broken. Use emulator. 372 */ 373 } 374 } 375 /* 376 * Probe failed, but we want to get to npxattach to initialize the 377 * emulator and say that it has been installed. XXX handle devices 378 * that aren't really devices better. 379 */ 380#ifdef SMP 381 if (mp_ncpus > 1) 382 panic("npx0 cannot be emulated on an SMP system"); 383#endif 384 /* FALLTHROUGH */ 385no_irq13: 386 idt[IDT_MF] = save_idt_npxtrap; 387 bus_teardown_intr(dev, irq_res, irq_cookie); 388 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 389 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 390 return (0); 391} 392 393/* 394 * Attach routine - announce which it is, and wire into system 395 */ 396static int 397npx_attach(dev) 398 device_t dev; 399{ 400 int flags; 401 register_t s; 402 403 flags = device_get_flags(dev); 404 405 if (npx_irq13) 406 device_printf(dev, "IRQ 13 interface\n"); 407 else if (npx_ex16) 408 device_printf(dev, "INT 16 interface\n"); 409 else 410 device_printf(dev, "WARNING: no FPU!\n"); 411 412 npxinit(__INITIAL_NPXCW__); 413 414 if (npx_cleanstate_ready == 0) { 415 s = intr_disable(); 416 stop_emulating(); 417 fpusave(&npx_cleanstate); 418 start_emulating(); 419 npx_cleanstate_ready = 1; 420 intr_restore(s); 421 } 422#ifdef I586_CPU_XXX 423 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 424 timezero("i586_bzero()", i586_bzero) < 425 timezero("bzero()", bzero) * 4 / 5) { 426 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 427 bcopy_vector = i586_bcopy; 428 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 429 bzero_vector = i586_bzero; 430 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 431 copyin_vector = i586_copyin; 432 copyout_vector = i586_copyout; 433 } 434 } 435#endif 436 437 return (0); /* XXX unused */ 438} 439 440/* 441 * Initialize floating point unit. 442 */ 443void 444npxinit(control) 445 u_short control; 446{ 447 static union savefpu dummy; 448 register_t savecrit; 449 450 if (!npx_exists) 451 return; 452 /* 453 * fninit has the same h/w bugs as fnsave. Use the detoxified 454 * fnsave to throw away any junk in the fpu. npxsave() initializes 455 * the fpu and sets fpcurthread = NULL as important side effects. 456 */ 457 savecrit = intr_disable(); 458 npxsave(&dummy); 459 stop_emulating(); 460#ifdef CPU_ENABLE_SSE 461 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 462 if (cpu_fxsr) 463 fninit(); 464#endif 465 fldcw(&control); 466 start_emulating(); 467 intr_restore(savecrit); 468} 469 470/* 471 * Free coprocessor (if we have it). 472 */ 473void 474npxexit(td) 475 struct thread *td; 476{ 477 register_t savecrit; 478 479 savecrit = intr_disable(); 480 if (curthread == PCPU_GET(fpcurthread)) 481 npxsave(&PCPU_GET(curpcb)->pcb_save); 482 intr_restore(savecrit); 483#ifdef NPX_DEBUG 484 if (npx_exists) { 485 u_int masked_exceptions; 486 487 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 488 /* 489 * Log exceptions that would have trapped with the old 490 * control word (overflow, divide by 0, and invalid operand). 491 */ 492 if (masked_exceptions & 0x0d) 493 log(LOG_ERR, 494 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 495 td->td_proc->p_pid, td->td_proc->p_comm, 496 masked_exceptions); 497 } 498#endif 499} 500 501int 502npxformat() 503{ 504 505 if (!npx_exists) 506 return (_MC_FPFMT_NODEV); 507#ifdef CPU_ENABLE_SSE 508 if (cpu_fxsr) 509 return (_MC_FPFMT_XMM); 510#endif 511 return (_MC_FPFMT_387); 512} 513 514/* 515 * The following mechanism is used to ensure that the FPE_... value 516 * that is passed as a trapcode to the signal handler of the user 517 * process does not have more than one bit set. 518 * 519 * Multiple bits may be set if the user process modifies the control 520 * word while a status word bit is already set. While this is a sign 521 * of bad coding, we have no choise than to narrow them down to one 522 * bit, since we must not send a trapcode that is not exactly one of 523 * the FPE_ macros. 524 * 525 * The mechanism has a static table with 127 entries. Each combination 526 * of the 7 FPU status word exception bits directly translates to a 527 * position in this table, where a single FPE_... value is stored. 528 * This FPE_... value stored there is considered the "most important" 529 * of the exception bits and will be sent as the signal code. The 530 * precedence of the bits is based upon Intel Document "Numerical 531 * Applications", Chapter "Special Computational Situations". 532 * 533 * The macro to choose one of these values does these steps: 1) Throw 534 * away status word bits that cannot be masked. 2) Throw away the bits 535 * currently masked in the control word, assuming the user isn't 536 * interested in them anymore. 3) Reinsert status word bit 7 (stack 537 * fault) if it is set, which cannot be masked but must be presered. 538 * 4) Use the remaining bits to point into the trapcode table. 539 * 540 * The 6 maskable bits in order of their preference, as stated in the 541 * above referenced Intel manual: 542 * 1 Invalid operation (FP_X_INV) 543 * 1a Stack underflow 544 * 1b Stack overflow 545 * 1c Operand of unsupported format 546 * 1d SNaN operand. 547 * 2 QNaN operand (not an exception, irrelavant here) 548 * 3 Any other invalid-operation not mentioned above or zero divide 549 * (FP_X_INV, FP_X_DZ) 550 * 4 Denormal operand (FP_X_DNML) 551 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 552 * 6 Inexact result (FP_X_IMP) 553 */ 554static char fpetable[128] = { 555 0, 556 FPE_FLTINV, /* 1 - INV */ 557 FPE_FLTUND, /* 2 - DNML */ 558 FPE_FLTINV, /* 3 - INV | DNML */ 559 FPE_FLTDIV, /* 4 - DZ */ 560 FPE_FLTINV, /* 5 - INV | DZ */ 561 FPE_FLTDIV, /* 6 - DNML | DZ */ 562 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 563 FPE_FLTOVF, /* 8 - OFL */ 564 FPE_FLTINV, /* 9 - INV | OFL */ 565 FPE_FLTUND, /* A - DNML | OFL */ 566 FPE_FLTINV, /* B - INV | DNML | OFL */ 567 FPE_FLTDIV, /* C - DZ | OFL */ 568 FPE_FLTINV, /* D - INV | DZ | OFL */ 569 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 570 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 571 FPE_FLTUND, /* 10 - UFL */ 572 FPE_FLTINV, /* 11 - INV | UFL */ 573 FPE_FLTUND, /* 12 - DNML | UFL */ 574 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 575 FPE_FLTDIV, /* 14 - DZ | UFL */ 576 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 577 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 578 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 579 FPE_FLTOVF, /* 18 - OFL | UFL */ 580 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 581 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 582 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 583 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 584 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 585 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 586 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 587 FPE_FLTRES, /* 20 - IMP */ 588 FPE_FLTINV, /* 21 - INV | IMP */ 589 FPE_FLTUND, /* 22 - DNML | IMP */ 590 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 591 FPE_FLTDIV, /* 24 - DZ | IMP */ 592 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 593 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 594 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 595 FPE_FLTOVF, /* 28 - OFL | IMP */ 596 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 597 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 598 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 599 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 600 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 601 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 602 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 603 FPE_FLTUND, /* 30 - UFL | IMP */ 604 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 605 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 606 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 607 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 608 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 609 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 610 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 611 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 612 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 613 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 614 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 615 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 616 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 617 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 618 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 619 FPE_FLTSUB, /* 40 - STK */ 620 FPE_FLTSUB, /* 41 - INV | STK */ 621 FPE_FLTUND, /* 42 - DNML | STK */ 622 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 623 FPE_FLTDIV, /* 44 - DZ | STK */ 624 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 625 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 626 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 627 FPE_FLTOVF, /* 48 - OFL | STK */ 628 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 629 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 630 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 631 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 632 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 633 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 634 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 635 FPE_FLTUND, /* 50 - UFL | STK */ 636 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 637 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 638 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 639 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 640 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 641 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 642 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 643 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 644 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 645 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 646 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 647 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 648 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 649 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 650 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 651 FPE_FLTRES, /* 60 - IMP | STK */ 652 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 653 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 654 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 655 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 656 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 657 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 658 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 659 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 660 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 661 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 662 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 663 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 664 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 665 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 666 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 667 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 668 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 669 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 670 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 671 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 672 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 673 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 674 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 675 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 676 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 677 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 678 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 679 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 680 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 681 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 682 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 683}; 684 685/* 686 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 687 * 688 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 689 * depend on longjmp() restoring a usable state. Restoring the state 690 * or examining it might fail if we didn't clear exceptions. 691 * 692 * The error code chosen will be one of the FPE_... macros. It will be 693 * sent as the second argument to old BSD-style signal handlers and as 694 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 695 * 696 * XXX the FP state is not preserved across signal handlers. So signal 697 * handlers cannot afford to do FP unless they preserve the state or 698 * longjmp() out. Both preserving the state and longjmp()ing may be 699 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 700 * solution for signals other than SIGFPE. 701 */ 702int 703npxtrap() 704{ 705 register_t savecrit; 706 u_short control, status; 707 708 if (!npx_exists) { 709 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 710 PCPU_GET(fpcurthread), curthread, npx_exists); 711 panic("npxtrap from nowhere"); 712 } 713 savecrit = intr_disable(); 714 715 /* 716 * Interrupt handling (for another interrupt) may have pushed the 717 * state to memory. Fetch the relevant parts of the state from 718 * wherever they are. 719 */ 720 if (PCPU_GET(fpcurthread) != curthread) { 721 control = GET_FPU_CW(curthread); 722 status = GET_FPU_SW(curthread); 723 } else { 724 fnstcw(&control); 725 fnstsw(&status); 726 } 727 728 if (PCPU_GET(fpcurthread) == curthread) 729 fnclex(); 730 intr_restore(savecrit); 731 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 732} 733 734/* 735 * Implement device not available (DNA) exception 736 * 737 * It would be better to switch FP context here (if curthread != fpcurthread) 738 * and not necessarily for every context switch, but it is too hard to 739 * access foreign pcb's. 740 */ 741 742static int err_count = 0; 743 744int 745npxdna() 746{ 747 struct pcb *pcb; 748 register_t s; 749#ifdef CPU_ENABLE_SSE 750 int mxcsr; 751#endif 752 u_short control; 753 754 if (!npx_exists) 755 return (0); 756 if (PCPU_GET(fpcurthread) == curthread) { 757 printf("npxdna: fpcurthread == curthread %d times\n", 758 ++err_count); 759 stop_emulating(); 760 return (1); 761 } 762 if (PCPU_GET(fpcurthread) != NULL) { 763 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 764 PCPU_GET(fpcurthread), 765 PCPU_GET(fpcurthread)->td_proc->p_pid, 766 curthread, curthread->td_proc->p_pid); 767 panic("npxdna"); 768 } 769 s = intr_disable(); 770 stop_emulating(); 771 /* 772 * Record new context early in case frstor causes an IRQ13. 773 */ 774 PCPU_SET(fpcurthread, curthread); 775 pcb = PCPU_GET(curpcb); 776 777 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 778 /* 779 * This is the first time this thread has used the FPU or 780 * the PCB doesn't contain a clean FPU state. Explicitly 781 * initialize the FPU and load the default control word. 782 */ 783 fninit(); 784 control = __INITIAL_NPXCW__; 785 fldcw(&control); 786#ifdef CPU_ENABLE_SSE 787 if (cpu_fxsr) { 788 mxcsr = __INITIAL_MXCSR__; 789 ldmxcsr(mxcsr); 790 } 791#endif 792 pcb->pcb_flags |= PCB_NPXINITDONE; 793 } else { 794 /* 795 * The following frstor may cause an IRQ13 when the state 796 * being restored has a pending error. The error will 797 * appear to have been triggered by the current (npx) user 798 * instruction even when that instruction is a no-wait 799 * instruction that should not trigger an error (e.g., 800 * fnclex). On at least one 486 system all of the no-wait 801 * instructions are broken the same as frstor, so our 802 * treatment does not amplify the breakage. On at least 803 * one 386/Cyrix 387 system, fnclex works correctly while 804 * frstor and fnsave are broken, so our treatment breaks 805 * fnclex if it is the first FPU instruction after a context 806 * switch. 807 */ 808 fpurstor(&pcb->pcb_save); 809 } 810 intr_restore(s); 811 812 return (1); 813} 814 815/* 816 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 817 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 818 * no-wait npx instructions. See the Intel application note AP-578 for 819 * details. This doesn't cause any additional complications here. IRQ13's 820 * are inherently asynchronous unless the CPU is frozen to deliver them -- 821 * one that started in userland may be delivered many instructions later, 822 * after the process has entered the kernel. It may even be delivered after 823 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 824 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 825 * it is normally ignored at first because we set fpcurthread to NULL; it is 826 * normally retriggered in npxdna() after return to user mode. 827 * 828 * npxsave() must be called with interrupts disabled, so that it clears 829 * fpcurthread atomically with saving the state. We require callers to do the 830 * disabling, since most callers need to disable interrupts anyway to call 831 * npxsave() atomically with checking fpcurthread. 832 * 833 * A previous version of npxsave() went to great lengths to excecute fnsave 834 * with interrupts enabled in case executing it froze the CPU. This case 835 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 836 * spurious freezes. 837 */ 838void 839npxsave(addr) 840 union savefpu *addr; 841{ 842 843 stop_emulating(); 844 fpusave(addr); 845 846 start_emulating(); 847 PCPU_SET(fpcurthread, NULL); 848} 849 850/* 851 * This should be called with interrupts disabled and only when the owning 852 * FPU thread is non-null. 853 */ 854void 855npxdrop() 856{ 857 struct thread *td; 858 859 /* 860 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 861 * ones don't cause a panic on the next frstor. 862 */ 863#ifdef CPU_ENABLE_SSE 864 if (!cpu_fxsr) 865#endif 866 fnclex(); 867 868 td = PCPU_GET(fpcurthread); 869 PCPU_SET(fpcurthread, NULL); 870 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 871 start_emulating(); 872} 873 874/* 875 * Get the state of the FPU without dropping ownership (if possible). 876 * It returns the FPU ownership status. 877 */ 878int 879npxgetregs(td, addr) 880 struct thread *td; 881 union savefpu *addr; 882{ 883 register_t s; 884 885 if (!npx_exists) 886 return (_MC_FPOWNED_NONE); 887 888 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 889 if (npx_cleanstate_ready) 890 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 891 else 892 bzero(addr, sizeof(*addr)); 893 return (_MC_FPOWNED_NONE); 894 } 895 s = intr_disable(); 896 if (td == PCPU_GET(fpcurthread)) { 897 fpusave(addr); 898#ifdef CPU_ENABLE_SSE 899 if (!cpu_fxsr) 900#endif 901 /* 902 * fnsave initializes the FPU and destroys whatever 903 * context it contains. Make sure the FPU owner 904 * starts with a clean state next time. 905 */ 906 npxdrop(); 907 intr_restore(s); 908 return (_MC_FPOWNED_FPU); 909 } else { 910 intr_restore(s); 911 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 912 return (_MC_FPOWNED_PCB); 913 } 914} 915 916/* 917 * Set the state of the FPU. 918 */ 919void 920npxsetregs(td, addr) 921 struct thread *td; 922 union savefpu *addr; 923{ 924 register_t s; 925 926 if (!npx_exists) 927 return; 928 929 s = intr_disable(); 930 if (td == PCPU_GET(fpcurthread)) { 931#ifdef CPU_ENABLE_SSE 932 if (!cpu_fxsr) 933#endif 934 fnclex(); /* As in npxdrop(). */ 935 fpurstor(addr); 936 intr_restore(s); 937 } else { 938 intr_restore(s); 939 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 940 } 941 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 942} 943 944static void 945fpusave(addr) 946 union savefpu *addr; 947{ 948 949#ifdef CPU_ENABLE_SSE 950 if (cpu_fxsr) 951 fxsave(addr); 952 else 953#endif 954 fnsave(addr); 955} 956 957static void 958fpurstor(addr) 959 union savefpu *addr; 960{ 961 962#ifdef CPU_ENABLE_SSE 963 if (cpu_fxsr) 964 fxrstor(addr); 965 else 966#endif 967 frstor(addr); 968} 969 970#ifdef I586_CPU_XXX 971static long 972timezero(funcname, func) 973 const char *funcname; 974 void (*func)(void *buf, size_t len); 975 976{ 977 void *buf; 978#define BUFSIZE 1048576 979 long usec; 980 struct timeval finish, start; 981 982 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 983 if (buf == NULL) 984 return (BUFSIZE); 985 microtime(&start); 986 (*func)(buf, BUFSIZE); 987 microtime(&finish); 988 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 989 finish.tv_usec - start.tv_usec; 990 if (usec <= 0) 991 usec = 1; 992 if (bootverbose) 993 printf("%s bandwidth = %u kBps\n", funcname, 994 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 995 free(buf, M_TEMP); 996 return (usec); 997} 998#endif /* I586_CPU */ 999 1000static device_method_t npx_methods[] = { 1001 /* Device interface */ 1002 DEVMETHOD(device_identify, npx_identify), 1003 DEVMETHOD(device_probe, npx_probe), 1004 DEVMETHOD(device_attach, npx_attach), 1005 DEVMETHOD(device_detach, bus_generic_detach), 1006 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1007 DEVMETHOD(device_suspend, bus_generic_suspend), 1008 DEVMETHOD(device_resume, bus_generic_resume), 1009 1010 { 0, 0 } 1011}; 1012 1013static driver_t npx_driver = { 1014 "npx", 1015 npx_methods, 1016 1, /* no softc */ 1017}; 1018 1019static devclass_t npx_devclass; 1020 1021/* 1022 * We prefer to attach to the root nexus so that the usual case (exception 16) 1023 * doesn't describe the processor as being `on isa'. 1024 */ 1025DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1026 1027#ifdef DEV_ISA 1028/* 1029 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1030 */ 1031static struct isa_pnp_id npxisa_ids[] = { 1032 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1033 { 0 } 1034}; 1035 1036static int 1037npxisa_probe(device_t dev) 1038{ 1039 int result; 1040 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1041 device_quiet(dev); 1042 } 1043 return(result); 1044} 1045 1046static int 1047npxisa_attach(device_t dev) 1048{ 1049 return (0); 1050} 1051 1052static device_method_t npxisa_methods[] = { 1053 /* Device interface */ 1054 DEVMETHOD(device_probe, npxisa_probe), 1055 DEVMETHOD(device_attach, npxisa_attach), 1056 DEVMETHOD(device_detach, bus_generic_detach), 1057 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1058 DEVMETHOD(device_suspend, bus_generic_suspend), 1059 DEVMETHOD(device_resume, bus_generic_resume), 1060 1061 { 0, 0 } 1062}; 1063 1064static driver_t npxisa_driver = { 1065 "npxisa", 1066 npxisa_methods, 1067 1, /* no softc */ 1068}; 1069 1070static devclass_t npxisa_devclass; 1071 1072DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1073#ifndef PC98 1074DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1075#endif 1076#endif /* DEV_ISA */ 1077