npx.c revision 146137
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 146137 2005-05-12 12:47:41Z nyan $"); 35 36#include "opt_cpu.h" 37#include "opt_isa.h" 38#include "opt_npx.h" 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/lock.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/mutex.h> 48#include <sys/mutex.h> 49#include <sys/proc.h> 50#include <sys/smp.h> 51#include <sys/sysctl.h> 52#include <machine/bus.h> 53#include <sys/rman.h> 54#ifdef NPX_DEBUG 55#include <sys/syslog.h> 56#endif 57#include <sys/signalvar.h> 58 59#include <machine/asmacros.h> 60#include <machine/cputypes.h> 61#include <machine/frame.h> 62#include <machine/md_var.h> 63#include <machine/pcb.h> 64#include <machine/psl.h> 65#include <machine/clock.h> 66#include <machine/resource.h> 67#include <machine/specialreg.h> 68#include <machine/segments.h> 69#include <machine/ucontext.h> 70 71#include <machine/intr_machdep.h> 72#ifdef DEV_ISA 73#include <isa/isavar.h> 74#endif 75 76#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 77#define CPU_ENABLE_SSE 78#endif 79#if defined(CPU_DISABLE_SSE) 80#undef CPU_ENABLE_SSE 81#endif 82 83/* 84 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 85 */ 86 87/* Configuration flags. */ 88#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 89#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 90#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 91 92#if defined(__GNUCLIKE_ASM) && !defined(lint) 93 94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 95#define fnclex() __asm("fnclex") 96#define fninit() __asm("fninit") 97#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 98#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 99#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 100#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 101#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 102#ifdef CPU_ENABLE_SSE 103#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 104#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 105#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 106#endif 107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 108 : : "n" (CR0_TS) : "ax") 109#define stop_emulating() __asm("clts") 110 111#else /* !(__GNUCLIKE_ASM && !lint) */ 112 113void fldcw(caddr_t addr); 114void fnclex(void); 115void fninit(void); 116void fnsave(caddr_t addr); 117void fnstcw(caddr_t addr); 118void fnstsw(caddr_t addr); 119void fp_divide_by_0(void); 120void frstor(caddr_t addr); 121#ifdef CPU_ENABLE_SSE 122void fxsave(caddr_t addr); 123void fxrstor(caddr_t addr); 124#endif 125void start_emulating(void); 126void stop_emulating(void); 127 128#endif /* __GNUCLIKE_ASM && !lint */ 129 130#ifdef CPU_ENABLE_SSE 131#define GET_FPU_CW(thread) \ 132 (cpu_fxsr ? \ 133 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 134 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 135#define GET_FPU_SW(thread) \ 136 (cpu_fxsr ? \ 137 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 138 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 139#else /* CPU_ENABLE_SSE */ 140#define GET_FPU_CW(thread) \ 141 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 142#define GET_FPU_SW(thread) \ 143 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 144#endif /* CPU_ENABLE_SSE */ 145 146typedef u_char bool_t; 147 148static void fpusave(union savefpu *); 149static void fpurstor(union savefpu *); 150static int npx_attach(device_t dev); 151static void npx_identify(driver_t *driver, device_t parent); 152static void npx_intr(void *); 153static int npx_probe(device_t dev); 154#ifdef I586_CPU_XXX 155static long timezero(const char *funcname, 156 void (*func)(void *buf, size_t len)); 157#endif /* I586_CPU */ 158 159int hw_float; /* XXX currently just alias for npx_exists */ 160 161SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 162 CTLFLAG_RD, &hw_float, 0, 163 "Floatingpoint instructions executed in hardware"); 164 165static volatile u_int npx_intrs_while_probing; 166static volatile u_int npx_traps_while_probing; 167 168static union savefpu npx_cleanstate; 169static bool_t npx_cleanstate_ready; 170static bool_t npx_ex16; 171static bool_t npx_exists; 172static bool_t npx_irq13; 173 174alias_for_inthand_t probetrap; 175__asm(" \n\ 176 .text \n\ 177 .p2align 2,0x90 \n\ 178 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 179" __XSTRING(CNAME(probetrap)) ": \n\ 180 ss \n\ 181 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 182 fnclex \n\ 183 iret \n\ 184"); 185 186/* 187 * Identify routine. Create a connection point on our parent for probing. 188 */ 189static void 190npx_identify(driver, parent) 191 driver_t *driver; 192 device_t parent; 193{ 194 device_t child; 195 196 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 197 if (child == NULL) 198 panic("npx_identify"); 199} 200 201/* 202 * Do minimal handling of npx interrupts to convert them to traps. 203 */ 204static void 205npx_intr(dummy) 206 void *dummy; 207{ 208 struct thread *td; 209 210 npx_intrs_while_probing++; 211 212 /* 213 * The BUSY# latch must be cleared in all cases so that the next 214 * unmasked npx exception causes an interrupt. 215 */ 216 outb(IO_NPX, 0); 217 218 /* 219 * fpcurthread is normally non-null here. In that case, schedule an 220 * AST to finish the exception handling in the correct context 221 * (this interrupt may occur after the thread has entered the 222 * kernel via a syscall or an interrupt). Otherwise, the npx 223 * state of the thread that caused this interrupt must have been 224 * pushed to the thread's pcb, and clearing of the busy latch 225 * above has finished the (essentially null) handling of this 226 * interrupt. Control will eventually return to the instruction 227 * that caused it and it will repeat. We will eventually (usually 228 * soon) win the race to handle the interrupt properly. 229 */ 230 td = PCPU_GET(fpcurthread); 231 if (td != NULL) { 232 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 233 mtx_lock_spin(&sched_lock); 234 td->td_flags |= TDF_ASTPENDING; 235 mtx_unlock_spin(&sched_lock); 236 } 237} 238 239/* 240 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 241 * whether the device exists or not (XXX should be elsewhere). Set flags 242 * to tell npxattach() what to do. Modify device struct if npx doesn't 243 * need to use interrupts. Return 0 if device exists. 244 */ 245static int 246npx_probe(dev) 247 device_t dev; 248{ 249 struct gate_descriptor save_idt_npxtrap; 250 struct resource *ioport_res, *irq_res; 251 void *irq_cookie; 252 int ioport_rid, irq_num, irq_rid; 253 u_short control; 254 u_short status; 255 256 save_idt_npxtrap = idt[IDT_MF]; 257 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 258 GSEL(GCODE_SEL, SEL_KPL)); 259 ioport_rid = 0; 260 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 261 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 262 if (ioport_res == NULL) 263 panic("npx: can't get ports"); 264 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 265 irq_num = IRQ_NPX; 266 irq_rid = 0; 267 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 268 irq_num, 1, RF_ACTIVE); 269 if (irq_res == NULL) 270 panic("npx: can't get IRQ"); 271 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 272 NULL, &irq_cookie) != 0) 273 panic("npx: can't create intr"); 274 275 /* 276 * Partially reset the coprocessor, if any. Some BIOS's don't reset 277 * it after a warm boot. 278 */ 279 npx_full_reset(); 280 outb(IO_NPX, 0); 281 282 /* 283 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 284 * instructions. We must set the CR0_MP bit and use the CR0_TS 285 * bit to control the trap, because setting the CR0_EM bit does 286 * not cause WAIT instructions to trap. It's important to trap 287 * WAIT instructions - otherwise the "wait" variants of no-wait 288 * control instructions would degenerate to the "no-wait" variants 289 * after FP context switches but work correctly otherwise. It's 290 * particularly important to trap WAITs when there is no NPX - 291 * otherwise the "wait" variants would always degenerate. 292 * 293 * Try setting CR0_NE to get correct error reporting on 486DX's. 294 * Setting it should fail or do nothing on lesser processors. 295 */ 296 load_cr0(rcr0() | CR0_MP | CR0_NE); 297 /* 298 * But don't trap while we're probing. 299 */ 300 stop_emulating(); 301 /* 302 * Finish resetting the coprocessor, if any. If there is an error 303 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 304 * it OK. Bogus halts have never been observed, but we enabled 305 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 306 */ 307 fninit(); 308 309 device_set_desc(dev, "math processor"); 310 311 /* 312 * Don't use fwait here because it might hang. 313 * Don't use fnop here because it usually hangs if there is no FPU. 314 */ 315 DELAY(1000); /* wait for any IRQ13 */ 316#ifdef DIAGNOSTIC 317 if (npx_intrs_while_probing != 0) 318 printf("fninit caused %u bogus npx interrupt(s)\n", 319 npx_intrs_while_probing); 320 if (npx_traps_while_probing != 0) 321 printf("fninit caused %u bogus npx trap(s)\n", 322 npx_traps_while_probing); 323#endif 324 /* 325 * Check for a status of mostly zero. 326 */ 327 status = 0x5a5a; 328 fnstsw(&status); 329 if ((status & 0xb8ff) == 0) { 330 /* 331 * Good, now check for a proper control word. 332 */ 333 control = 0x5a5a; 334 fnstcw(&control); 335 if ((control & 0x1f3f) == 0x033f) { 336 hw_float = npx_exists = 1; 337 /* 338 * We have an npx, now divide by 0 to see if exception 339 * 16 works. 340 */ 341 control &= ~(1 << 2); /* enable divide by 0 trap */ 342 fldcw(&control); 343#ifdef FPU_ERROR_BROKEN 344 /* 345 * FPU error signal doesn't work on some CPU 346 * accelerator board. 347 */ 348 npx_ex16 = 1; 349 return (0); 350#endif 351 npx_traps_while_probing = npx_intrs_while_probing = 0; 352 fp_divide_by_0(); 353 DELAY(1000); /* wait for any IRQ13 */ 354 if (npx_traps_while_probing != 0) { 355 /* 356 * Good, exception 16 works. 357 */ 358 npx_ex16 = 1; 359 goto no_irq13; 360 } 361 if (npx_intrs_while_probing != 0) { 362 /* 363 * Bad, we are stuck with IRQ13. 364 */ 365 npx_irq13 = 1; 366 idt[IDT_MF] = save_idt_npxtrap; 367#ifdef SMP 368 if (mp_ncpus > 1) 369 panic("npx0 cannot use IRQ 13 on an SMP system"); 370#endif 371 return (0); 372 } 373 /* 374 * Worse, even IRQ13 is broken. Use emulator. 375 */ 376 } 377 } 378 /* 379 * Probe failed, but we want to get to npxattach to initialize the 380 * emulator and say that it has been installed. XXX handle devices 381 * that aren't really devices better. 382 */ 383#ifdef SMP 384 if (mp_ncpus > 1) 385 panic("npx0 cannot be emulated on an SMP system"); 386#endif 387 /* FALLTHROUGH */ 388no_irq13: 389 idt[IDT_MF] = save_idt_npxtrap; 390 bus_teardown_intr(dev, irq_res, irq_cookie); 391 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 392 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 393 return (0); 394} 395 396/* 397 * Attach routine - announce which it is, and wire into system 398 */ 399static int 400npx_attach(dev) 401 device_t dev; 402{ 403 int flags; 404 register_t s; 405 406 flags = device_get_flags(dev); 407 408 if (npx_irq13) 409 device_printf(dev, "IRQ 13 interface\n"); 410 else if (npx_ex16) 411 device_printf(dev, "INT 16 interface\n"); 412 else 413 device_printf(dev, "WARNING: no FPU!\n"); 414 415 npxinit(__INITIAL_NPXCW__); 416 417 if (npx_cleanstate_ready == 0) { 418 s = intr_disable(); 419 stop_emulating(); 420 fpusave(&npx_cleanstate); 421 start_emulating(); 422 npx_cleanstate_ready = 1; 423 intr_restore(s); 424 } 425#ifdef I586_CPU_XXX 426 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 427 timezero("i586_bzero()", i586_bzero) < 428 timezero("bzero()", bzero) * 4 / 5) { 429 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 430 bcopy_vector = i586_bcopy; 431 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 432 bzero_vector = i586_bzero; 433 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 434 copyin_vector = i586_copyin; 435 copyout_vector = i586_copyout; 436 } 437 } 438#endif 439 440 return (0); /* XXX unused */ 441} 442 443/* 444 * Initialize floating point unit. 445 */ 446void 447npxinit(control) 448 u_short control; 449{ 450 static union savefpu dummy; 451 register_t savecrit; 452 453 if (!npx_exists) 454 return; 455 /* 456 * fninit has the same h/w bugs as fnsave. Use the detoxified 457 * fnsave to throw away any junk in the fpu. npxsave() initializes 458 * the fpu and sets fpcurthread = NULL as important side effects. 459 */ 460 savecrit = intr_disable(); 461 npxsave(&dummy); 462 stop_emulating(); 463#ifdef CPU_ENABLE_SSE 464 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 465 if (cpu_fxsr) 466 fninit(); 467#endif 468 fldcw(&control); 469 start_emulating(); 470 intr_restore(savecrit); 471} 472 473/* 474 * Free coprocessor (if we have it). 475 */ 476void 477npxexit(td) 478 struct thread *td; 479{ 480 register_t savecrit; 481 482 savecrit = intr_disable(); 483 if (curthread == PCPU_GET(fpcurthread)) 484 npxsave(&PCPU_GET(curpcb)->pcb_save); 485 intr_restore(savecrit); 486#ifdef NPX_DEBUG 487 if (npx_exists) { 488 u_int masked_exceptions; 489 490 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 491 /* 492 * Log exceptions that would have trapped with the old 493 * control word (overflow, divide by 0, and invalid operand). 494 */ 495 if (masked_exceptions & 0x0d) 496 log(LOG_ERR, 497 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 498 td->td_proc->p_pid, td->td_proc->p_comm, 499 masked_exceptions); 500 } 501#endif 502} 503 504int 505npxformat() 506{ 507 508 if (!npx_exists) 509 return (_MC_FPFMT_NODEV); 510#ifdef CPU_ENABLE_SSE 511 if (cpu_fxsr) 512 return (_MC_FPFMT_XMM); 513#endif 514 return (_MC_FPFMT_387); 515} 516 517/* 518 * The following mechanism is used to ensure that the FPE_... value 519 * that is passed as a trapcode to the signal handler of the user 520 * process does not have more than one bit set. 521 * 522 * Multiple bits may be set if the user process modifies the control 523 * word while a status word bit is already set. While this is a sign 524 * of bad coding, we have no choise than to narrow them down to one 525 * bit, since we must not send a trapcode that is not exactly one of 526 * the FPE_ macros. 527 * 528 * The mechanism has a static table with 127 entries. Each combination 529 * of the 7 FPU status word exception bits directly translates to a 530 * position in this table, where a single FPE_... value is stored. 531 * This FPE_... value stored there is considered the "most important" 532 * of the exception bits and will be sent as the signal code. The 533 * precedence of the bits is based upon Intel Document "Numerical 534 * Applications", Chapter "Special Computational Situations". 535 * 536 * The macro to choose one of these values does these steps: 1) Throw 537 * away status word bits that cannot be masked. 2) Throw away the bits 538 * currently masked in the control word, assuming the user isn't 539 * interested in them anymore. 3) Reinsert status word bit 7 (stack 540 * fault) if it is set, which cannot be masked but must be presered. 541 * 4) Use the remaining bits to point into the trapcode table. 542 * 543 * The 6 maskable bits in order of their preference, as stated in the 544 * above referenced Intel manual: 545 * 1 Invalid operation (FP_X_INV) 546 * 1a Stack underflow 547 * 1b Stack overflow 548 * 1c Operand of unsupported format 549 * 1d SNaN operand. 550 * 2 QNaN operand (not an exception, irrelavant here) 551 * 3 Any other invalid-operation not mentioned above or zero divide 552 * (FP_X_INV, FP_X_DZ) 553 * 4 Denormal operand (FP_X_DNML) 554 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 555 * 6 Inexact result (FP_X_IMP) 556 */ 557static char fpetable[128] = { 558 0, 559 FPE_FLTINV, /* 1 - INV */ 560 FPE_FLTUND, /* 2 - DNML */ 561 FPE_FLTINV, /* 3 - INV | DNML */ 562 FPE_FLTDIV, /* 4 - DZ */ 563 FPE_FLTINV, /* 5 - INV | DZ */ 564 FPE_FLTDIV, /* 6 - DNML | DZ */ 565 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 566 FPE_FLTOVF, /* 8 - OFL */ 567 FPE_FLTINV, /* 9 - INV | OFL */ 568 FPE_FLTUND, /* A - DNML | OFL */ 569 FPE_FLTINV, /* B - INV | DNML | OFL */ 570 FPE_FLTDIV, /* C - DZ | OFL */ 571 FPE_FLTINV, /* D - INV | DZ | OFL */ 572 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 573 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 574 FPE_FLTUND, /* 10 - UFL */ 575 FPE_FLTINV, /* 11 - INV | UFL */ 576 FPE_FLTUND, /* 12 - DNML | UFL */ 577 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 578 FPE_FLTDIV, /* 14 - DZ | UFL */ 579 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 580 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 581 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 582 FPE_FLTOVF, /* 18 - OFL | UFL */ 583 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 584 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 585 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 586 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 587 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 588 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 589 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 590 FPE_FLTRES, /* 20 - IMP */ 591 FPE_FLTINV, /* 21 - INV | IMP */ 592 FPE_FLTUND, /* 22 - DNML | IMP */ 593 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 594 FPE_FLTDIV, /* 24 - DZ | IMP */ 595 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 596 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 597 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 598 FPE_FLTOVF, /* 28 - OFL | IMP */ 599 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 600 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 601 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 602 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 603 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 604 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 605 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 606 FPE_FLTUND, /* 30 - UFL | IMP */ 607 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 608 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 609 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 610 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 611 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 612 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 613 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 614 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 615 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 616 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 617 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 618 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 619 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 620 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 621 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 622 FPE_FLTSUB, /* 40 - STK */ 623 FPE_FLTSUB, /* 41 - INV | STK */ 624 FPE_FLTUND, /* 42 - DNML | STK */ 625 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 626 FPE_FLTDIV, /* 44 - DZ | STK */ 627 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 628 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 629 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 630 FPE_FLTOVF, /* 48 - OFL | STK */ 631 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 632 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 633 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 634 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 635 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 636 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 637 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 638 FPE_FLTUND, /* 50 - UFL | STK */ 639 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 640 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 641 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 642 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 643 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 644 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 645 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 646 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 647 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 648 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 649 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 650 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 651 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 652 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 653 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 654 FPE_FLTRES, /* 60 - IMP | STK */ 655 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 656 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 657 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 658 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 659 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 660 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 661 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 662 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 663 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 664 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 665 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 666 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 667 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 668 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 669 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 670 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 671 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 672 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 673 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 674 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 675 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 676 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 677 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 678 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 679 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 680 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 681 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 682 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 683 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 684 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 685 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 686}; 687 688/* 689 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 690 * 691 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 692 * depend on longjmp() restoring a usable state. Restoring the state 693 * or examining it might fail if we didn't clear exceptions. 694 * 695 * The error code chosen will be one of the FPE_... macros. It will be 696 * sent as the second argument to old BSD-style signal handlers and as 697 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 698 * 699 * XXX the FP state is not preserved across signal handlers. So signal 700 * handlers cannot afford to do FP unless they preserve the state or 701 * longjmp() out. Both preserving the state and longjmp()ing may be 702 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 703 * solution for signals other than SIGFPE. 704 */ 705int 706npxtrap() 707{ 708 register_t savecrit; 709 u_short control, status; 710 711 if (!npx_exists) { 712 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 713 PCPU_GET(fpcurthread), curthread, npx_exists); 714 panic("npxtrap from nowhere"); 715 } 716 savecrit = intr_disable(); 717 718 /* 719 * Interrupt handling (for another interrupt) may have pushed the 720 * state to memory. Fetch the relevant parts of the state from 721 * wherever they are. 722 */ 723 if (PCPU_GET(fpcurthread) != curthread) { 724 control = GET_FPU_CW(curthread); 725 status = GET_FPU_SW(curthread); 726 } else { 727 fnstcw(&control); 728 fnstsw(&status); 729 } 730 731 if (PCPU_GET(fpcurthread) == curthread) 732 fnclex(); 733 intr_restore(savecrit); 734 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 735} 736 737/* 738 * Implement device not available (DNA) exception 739 * 740 * It would be better to switch FP context here (if curthread != fpcurthread) 741 * and not necessarily for every context switch, but it is too hard to 742 * access foreign pcb's. 743 */ 744 745static int err_count = 0; 746 747int 748npxdna() 749{ 750 struct pcb *pcb; 751 register_t s; 752#ifdef CPU_ENABLE_SSE 753 int mxcsr; 754#endif 755 u_short control; 756 757 if (!npx_exists) 758 return (0); 759 if (PCPU_GET(fpcurthread) == curthread) { 760 printf("npxdna: fpcurthread == curthread %d times\n", 761 ++err_count); 762 stop_emulating(); 763 return (1); 764 } 765 if (PCPU_GET(fpcurthread) != NULL) { 766 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 767 PCPU_GET(fpcurthread), 768 PCPU_GET(fpcurthread)->td_proc->p_pid, 769 curthread, curthread->td_proc->p_pid); 770 panic("npxdna"); 771 } 772 s = intr_disable(); 773 stop_emulating(); 774 /* 775 * Record new context early in case frstor causes an IRQ13. 776 */ 777 PCPU_SET(fpcurthread, curthread); 778 pcb = PCPU_GET(curpcb); 779 780 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 781 /* 782 * This is the first time this thread has used the FPU or 783 * the PCB doesn't contain a clean FPU state. Explicitly 784 * initialize the FPU and load the default control word. 785 */ 786 fninit(); 787 control = __INITIAL_NPXCW__; 788 fldcw(&control); 789#ifdef CPU_ENABLE_SSE 790 if (cpu_fxsr) { 791 mxcsr = __INITIAL_MXCSR__; 792 ldmxcsr(mxcsr); 793 } 794#endif 795 pcb->pcb_flags |= PCB_NPXINITDONE; 796 } else { 797 /* 798 * The following frstor may cause an IRQ13 when the state 799 * being restored has a pending error. The error will 800 * appear to have been triggered by the current (npx) user 801 * instruction even when that instruction is a no-wait 802 * instruction that should not trigger an error (e.g., 803 * fnclex). On at least one 486 system all of the no-wait 804 * instructions are broken the same as frstor, so our 805 * treatment does not amplify the breakage. On at least 806 * one 386/Cyrix 387 system, fnclex works correctly while 807 * frstor and fnsave are broken, so our treatment breaks 808 * fnclex if it is the first FPU instruction after a context 809 * switch. 810 */ 811 fpurstor(&pcb->pcb_save); 812 } 813 intr_restore(s); 814 815 return (1); 816} 817 818/* 819 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 820 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 821 * no-wait npx instructions. See the Intel application note AP-578 for 822 * details. This doesn't cause any additional complications here. IRQ13's 823 * are inherently asynchronous unless the CPU is frozen to deliver them -- 824 * one that started in userland may be delivered many instructions later, 825 * after the process has entered the kernel. It may even be delivered after 826 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 827 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 828 * it is normally ignored at first because we set fpcurthread to NULL; it is 829 * normally retriggered in npxdna() after return to user mode. 830 * 831 * npxsave() must be called with interrupts disabled, so that it clears 832 * fpcurthread atomically with saving the state. We require callers to do the 833 * disabling, since most callers need to disable interrupts anyway to call 834 * npxsave() atomically with checking fpcurthread. 835 * 836 * A previous version of npxsave() went to great lengths to excecute fnsave 837 * with interrupts enabled in case executing it froze the CPU. This case 838 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 839 * spurious freezes. 840 */ 841void 842npxsave(addr) 843 union savefpu *addr; 844{ 845 846 stop_emulating(); 847 fpusave(addr); 848 849 start_emulating(); 850 PCPU_SET(fpcurthread, NULL); 851} 852 853/* 854 * This should be called with interrupts disabled and only when the owning 855 * FPU thread is non-null. 856 */ 857void 858npxdrop() 859{ 860 struct thread *td; 861 862 /* 863 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 864 * ones don't cause a panic on the next frstor. 865 */ 866#ifdef CPU_ENABLE_SSE 867 if (!cpu_fxsr) 868#endif 869 fnclex(); 870 871 td = PCPU_GET(fpcurthread); 872 PCPU_SET(fpcurthread, NULL); 873 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 874 start_emulating(); 875} 876 877/* 878 * Get the state of the FPU without dropping ownership (if possible). 879 * It returns the FPU ownership status. 880 */ 881int 882npxgetregs(td, addr) 883 struct thread *td; 884 union savefpu *addr; 885{ 886 register_t s; 887 888 if (!npx_exists) 889 return (_MC_FPOWNED_NONE); 890 891 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 892 if (npx_cleanstate_ready) 893 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 894 else 895 bzero(addr, sizeof(*addr)); 896 return (_MC_FPOWNED_NONE); 897 } 898 s = intr_disable(); 899 if (td == PCPU_GET(fpcurthread)) { 900 fpusave(addr); 901#ifdef CPU_ENABLE_SSE 902 if (!cpu_fxsr) 903#endif 904 /* 905 * fnsave initializes the FPU and destroys whatever 906 * context it contains. Make sure the FPU owner 907 * starts with a clean state next time. 908 */ 909 npxdrop(); 910 intr_restore(s); 911 return (_MC_FPOWNED_FPU); 912 } else { 913 intr_restore(s); 914 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 915 return (_MC_FPOWNED_PCB); 916 } 917} 918 919/* 920 * Set the state of the FPU. 921 */ 922void 923npxsetregs(td, addr) 924 struct thread *td; 925 union savefpu *addr; 926{ 927 register_t s; 928 929 if (!npx_exists) 930 return; 931 932 s = intr_disable(); 933 if (td == PCPU_GET(fpcurthread)) { 934#ifdef CPU_ENABLE_SSE 935 if (!cpu_fxsr) 936#endif 937 fnclex(); /* As in npxdrop(). */ 938 fpurstor(addr); 939 intr_restore(s); 940 } else { 941 intr_restore(s); 942 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 943 } 944 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 945} 946 947static void 948fpusave(addr) 949 union savefpu *addr; 950{ 951 952#ifdef CPU_ENABLE_SSE 953 if (cpu_fxsr) 954 fxsave(addr); 955 else 956#endif 957 fnsave(addr); 958} 959 960static void 961fpurstor(addr) 962 union savefpu *addr; 963{ 964 965#ifdef CPU_ENABLE_SSE 966 if (cpu_fxsr) 967 fxrstor(addr); 968 else 969#endif 970 frstor(addr); 971} 972 973#ifdef I586_CPU_XXX 974static long 975timezero(funcname, func) 976 const char *funcname; 977 void (*func)(void *buf, size_t len); 978 979{ 980 void *buf; 981#define BUFSIZE 1048576 982 long usec; 983 struct timeval finish, start; 984 985 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 986 if (buf == NULL) 987 return (BUFSIZE); 988 microtime(&start); 989 (*func)(buf, BUFSIZE); 990 microtime(&finish); 991 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 992 finish.tv_usec - start.tv_usec; 993 if (usec <= 0) 994 usec = 1; 995 if (bootverbose) 996 printf("%s bandwidth = %u kBps\n", funcname, 997 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 998 free(buf, M_TEMP); 999 return (usec); 1000} 1001#endif /* I586_CPU */ 1002 1003static device_method_t npx_methods[] = { 1004 /* Device interface */ 1005 DEVMETHOD(device_identify, npx_identify), 1006 DEVMETHOD(device_probe, npx_probe), 1007 DEVMETHOD(device_attach, npx_attach), 1008 DEVMETHOD(device_detach, bus_generic_detach), 1009 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1010 DEVMETHOD(device_suspend, bus_generic_suspend), 1011 DEVMETHOD(device_resume, bus_generic_resume), 1012 1013 { 0, 0 } 1014}; 1015 1016static driver_t npx_driver = { 1017 "npx", 1018 npx_methods, 1019 1, /* no softc */ 1020}; 1021 1022static devclass_t npx_devclass; 1023 1024/* 1025 * We prefer to attach to the root nexus so that the usual case (exception 16) 1026 * doesn't describe the processor as being `on isa'. 1027 */ 1028DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1029 1030#ifdef DEV_ISA 1031/* 1032 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1033 */ 1034static struct isa_pnp_id npxisa_ids[] = { 1035 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1036 { 0 } 1037}; 1038 1039static int 1040npxisa_probe(device_t dev) 1041{ 1042 int result; 1043 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1044 device_quiet(dev); 1045 } 1046 return(result); 1047} 1048 1049static int 1050npxisa_attach(device_t dev) 1051{ 1052 return (0); 1053} 1054 1055static device_method_t npxisa_methods[] = { 1056 /* Device interface */ 1057 DEVMETHOD(device_probe, npxisa_probe), 1058 DEVMETHOD(device_attach, npxisa_attach), 1059 DEVMETHOD(device_detach, bus_generic_detach), 1060 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1061 DEVMETHOD(device_suspend, bus_generic_suspend), 1062 DEVMETHOD(device_resume, bus_generic_resume), 1063 1064 { 0, 0 } 1065}; 1066 1067static driver_t npxisa_driver = { 1068 "npxisa", 1069 npxisa_methods, 1070 1, /* no softc */ 1071}; 1072 1073static devclass_t npxisa_devclass; 1074 1075DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1076#ifndef PC98 1077DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1078#endif 1079#endif /* DEV_ISA */ 1080