npx.c revision 143768
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 143768 2005-03-17 22:21:36Z das $"); 35 36#include "opt_cpu.h" 37#include "opt_debug_npx.h" 38#include "opt_isa.h" 39#include "opt_npx.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/module.h> 48#include <sys/mutex.h> 49#include <sys/mutex.h> 50#include <sys/proc.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59 60#include <machine/asmacros.h> 61#include <machine/cputypes.h> 62#include <machine/frame.h> 63#include <machine/md_var.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/clock.h> 67#include <machine/resource.h> 68#include <machine/specialreg.h> 69#include <machine/segments.h> 70#include <machine/ucontext.h> 71 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#else 75#include <i386/isa/isa.h> 76#endif 77#include <machine/intr_machdep.h> 78#ifdef DEV_ISA 79#include <isa/isavar.h> 80#endif 81 82#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 83#define CPU_ENABLE_SSE 84#endif 85#if defined(CPU_DISABLE_SSE) 86#undef CPU_ENABLE_SSE 87#endif 88 89/* 90 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 91 */ 92 93/* Configuration flags. */ 94#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 95#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 96#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 97 98#if defined(__GNUCLIKE_ASM) && !defined(lint) 99 100#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 101#define fnclex() __asm("fnclex") 102#define fninit() __asm("fninit") 103#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 104#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 105#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 106#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 107#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 108#ifdef CPU_ENABLE_SSE 109#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 110#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 111#define ldmxcsr(__csr) __asm __volatile("ldmxcsr %0" : : "m" (__csr)) 112#endif 113#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 114 : : "n" (CR0_TS) : "ax") 115#define stop_emulating() __asm("clts") 116 117#else /* !(__GNUCLIKE_ASM && !lint) */ 118 119void fldcw(caddr_t addr); 120void fnclex(void); 121void fninit(void); 122void fnsave(caddr_t addr); 123void fnstcw(caddr_t addr); 124void fnstsw(caddr_t addr); 125void fp_divide_by_0(void); 126void frstor(caddr_t addr); 127#ifdef CPU_ENABLE_SSE 128void fxsave(caddr_t addr); 129void fxrstor(caddr_t addr); 130#endif 131void start_emulating(void); 132void stop_emulating(void); 133 134#endif /* __GNUCLIKE_ASM && !lint */ 135 136#ifdef CPU_ENABLE_SSE 137#define GET_FPU_CW(thread) \ 138 (cpu_fxsr ? \ 139 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 140 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 141#define GET_FPU_SW(thread) \ 142 (cpu_fxsr ? \ 143 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 144 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 145#else /* CPU_ENABLE_SSE */ 146#define GET_FPU_CW(thread) \ 147 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 148#define GET_FPU_SW(thread) \ 149 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 150#endif /* CPU_ENABLE_SSE */ 151 152typedef u_char bool_t; 153 154static void fpusave(union savefpu *); 155static void fpurstor(union savefpu *); 156static int npx_attach(device_t dev); 157static void npx_identify(driver_t *driver, device_t parent); 158static void npx_intr(void *); 159static int npx_probe(device_t dev); 160#ifdef I586_CPU_XXX 161static long timezero(const char *funcname, 162 void (*func)(void *buf, size_t len)); 163#endif /* I586_CPU */ 164 165int hw_float; /* XXX currently just alias for npx_exists */ 166 167SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 168 CTLFLAG_RD, &hw_float, 0, 169 "Floatingpoint instructions executed in hardware"); 170 171static volatile u_int npx_intrs_while_probing; 172static volatile u_int npx_traps_while_probing; 173 174static union savefpu npx_cleanstate; 175static bool_t npx_cleanstate_ready; 176static bool_t npx_ex16; 177static bool_t npx_exists; 178static bool_t npx_irq13; 179 180alias_for_inthand_t probetrap; 181__asm(" \n\ 182 .text \n\ 183 .p2align 2,0x90 \n\ 184 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 185" __XSTRING(CNAME(probetrap)) ": \n\ 186 ss \n\ 187 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 188 fnclex \n\ 189 iret \n\ 190"); 191 192/* 193 * Identify routine. Create a connection point on our parent for probing. 194 */ 195static void 196npx_identify(driver, parent) 197 driver_t *driver; 198 device_t parent; 199{ 200 device_t child; 201 202 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 203 if (child == NULL) 204 panic("npx_identify"); 205} 206 207/* 208 * Do minimal handling of npx interrupts to convert them to traps. 209 */ 210static void 211npx_intr(dummy) 212 void *dummy; 213{ 214 struct thread *td; 215 216 npx_intrs_while_probing++; 217 218 /* 219 * The BUSY# latch must be cleared in all cases so that the next 220 * unmasked npx exception causes an interrupt. 221 */ 222 outb(IO_NPX, 0); 223 224 /* 225 * fpcurthread is normally non-null here. In that case, schedule an 226 * AST to finish the exception handling in the correct context 227 * (this interrupt may occur after the thread has entered the 228 * kernel via a syscall or an interrupt). Otherwise, the npx 229 * state of the thread that caused this interrupt must have been 230 * pushed to the thread's pcb, and clearing of the busy latch 231 * above has finished the (essentially null) handling of this 232 * interrupt. Control will eventually return to the instruction 233 * that caused it and it will repeat. We will eventually (usually 234 * soon) win the race to handle the interrupt properly. 235 */ 236 td = PCPU_GET(fpcurthread); 237 if (td != NULL) { 238 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 239 mtx_lock_spin(&sched_lock); 240 td->td_flags |= TDF_ASTPENDING; 241 mtx_unlock_spin(&sched_lock); 242 } 243} 244 245/* 246 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 247 * whether the device exists or not (XXX should be elsewhere). Set flags 248 * to tell npxattach() what to do. Modify device struct if npx doesn't 249 * need to use interrupts. Return 0 if device exists. 250 */ 251static int 252npx_probe(dev) 253 device_t dev; 254{ 255 struct gate_descriptor save_idt_npxtrap; 256 struct resource *ioport_res, *irq_res; 257 void *irq_cookie; 258 int ioport_rid, irq_num, irq_rid; 259 u_short control; 260 u_short status; 261 262 save_idt_npxtrap = idt[IDT_MF]; 263 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 264 GSEL(GCODE_SEL, SEL_KPL)); 265 ioport_rid = 0; 266 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 267 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 268 if (ioport_res == NULL) 269 panic("npx: can't get ports"); 270 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 271 irq_num = IRQ_NPX; 272 irq_rid = 0; 273 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 274 irq_num, 1, RF_ACTIVE); 275 if (irq_res == NULL) 276 panic("npx: can't get IRQ"); 277 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 278 NULL, &irq_cookie) != 0) 279 panic("npx: can't create intr"); 280 281 /* 282 * Partially reset the coprocessor, if any. Some BIOS's don't reset 283 * it after a warm boot. 284 */ 285 npx_full_reset(); 286 outb(IO_NPX, 0); 287 288 /* 289 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 290 * instructions. We must set the CR0_MP bit and use the CR0_TS 291 * bit to control the trap, because setting the CR0_EM bit does 292 * not cause WAIT instructions to trap. It's important to trap 293 * WAIT instructions - otherwise the "wait" variants of no-wait 294 * control instructions would degenerate to the "no-wait" variants 295 * after FP context switches but work correctly otherwise. It's 296 * particularly important to trap WAITs when there is no NPX - 297 * otherwise the "wait" variants would always degenerate. 298 * 299 * Try setting CR0_NE to get correct error reporting on 486DX's. 300 * Setting it should fail or do nothing on lesser processors. 301 */ 302 load_cr0(rcr0() | CR0_MP | CR0_NE); 303 /* 304 * But don't trap while we're probing. 305 */ 306 stop_emulating(); 307 /* 308 * Finish resetting the coprocessor, if any. If there is an error 309 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 310 * it OK. Bogus halts have never been observed, but we enabled 311 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 312 */ 313 fninit(); 314 315 device_set_desc(dev, "math processor"); 316 317 /* 318 * Don't use fwait here because it might hang. 319 * Don't use fnop here because it usually hangs if there is no FPU. 320 */ 321 DELAY(1000); /* wait for any IRQ13 */ 322#ifdef DIAGNOSTIC 323 if (npx_intrs_while_probing != 0) 324 printf("fninit caused %u bogus npx interrupt(s)\n", 325 npx_intrs_while_probing); 326 if (npx_traps_while_probing != 0) 327 printf("fninit caused %u bogus npx trap(s)\n", 328 npx_traps_while_probing); 329#endif 330 /* 331 * Check for a status of mostly zero. 332 */ 333 status = 0x5a5a; 334 fnstsw(&status); 335 if ((status & 0xb8ff) == 0) { 336 /* 337 * Good, now check for a proper control word. 338 */ 339 control = 0x5a5a; 340 fnstcw(&control); 341 if ((control & 0x1f3f) == 0x033f) { 342 hw_float = npx_exists = 1; 343 /* 344 * We have an npx, now divide by 0 to see if exception 345 * 16 works. 346 */ 347 control &= ~(1 << 2); /* enable divide by 0 trap */ 348 fldcw(&control); 349#ifdef FPU_ERROR_BROKEN 350 /* 351 * FPU error signal doesn't work on some CPU 352 * accelerator board. 353 */ 354 npx_ex16 = 1; 355 return (0); 356#endif 357 npx_traps_while_probing = npx_intrs_while_probing = 0; 358 fp_divide_by_0(); 359 DELAY(1000); /* wait for any IRQ13 */ 360 if (npx_traps_while_probing != 0) { 361 /* 362 * Good, exception 16 works. 363 */ 364 npx_ex16 = 1; 365 goto no_irq13; 366 } 367 if (npx_intrs_while_probing != 0) { 368 /* 369 * Bad, we are stuck with IRQ13. 370 */ 371 npx_irq13 = 1; 372 idt[IDT_MF] = save_idt_npxtrap; 373#ifdef SMP 374 if (mp_ncpus > 1) 375 panic("npx0 cannot use IRQ 13 on an SMP system"); 376#endif 377 return (0); 378 } 379 /* 380 * Worse, even IRQ13 is broken. Use emulator. 381 */ 382 } 383 } 384 /* 385 * Probe failed, but we want to get to npxattach to initialize the 386 * emulator and say that it has been installed. XXX handle devices 387 * that aren't really devices better. 388 */ 389#ifdef SMP 390 if (mp_ncpus > 1) 391 panic("npx0 cannot be emulated on an SMP system"); 392#endif 393 /* FALLTHROUGH */ 394no_irq13: 395 idt[IDT_MF] = save_idt_npxtrap; 396 bus_teardown_intr(dev, irq_res, irq_cookie); 397 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 398 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 399 return (0); 400} 401 402/* 403 * Attach routine - announce which it is, and wire into system 404 */ 405static int 406npx_attach(dev) 407 device_t dev; 408{ 409 int flags; 410 register_t s; 411 412 flags = device_get_flags(dev); 413 414 if (npx_irq13) 415 device_printf(dev, "IRQ 13 interface\n"); 416 else if (npx_ex16) 417 device_printf(dev, "INT 16 interface\n"); 418 else 419 device_printf(dev, "WARNING: no FPU!\n"); 420 421 npxinit(__INITIAL_NPXCW__); 422 423 if (npx_cleanstate_ready == 0) { 424 s = intr_disable(); 425 stop_emulating(); 426 fpusave(&npx_cleanstate); 427 start_emulating(); 428 npx_cleanstate_ready = 1; 429 intr_restore(s); 430 } 431#ifdef I586_CPU_XXX 432 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 433 timezero("i586_bzero()", i586_bzero) < 434 timezero("bzero()", bzero) * 4 / 5) { 435 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 436 bcopy_vector = i586_bcopy; 437 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 438 bzero_vector = i586_bzero; 439 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 440 copyin_vector = i586_copyin; 441 copyout_vector = i586_copyout; 442 } 443 } 444#endif 445 446 return (0); /* XXX unused */ 447} 448 449/* 450 * Initialize floating point unit. 451 */ 452void 453npxinit(control) 454 u_short control; 455{ 456 static union savefpu dummy; 457 register_t savecrit; 458 459 if (!npx_exists) 460 return; 461 /* 462 * fninit has the same h/w bugs as fnsave. Use the detoxified 463 * fnsave to throw away any junk in the fpu. npxsave() initializes 464 * the fpu and sets fpcurthread = NULL as important side effects. 465 */ 466 savecrit = intr_disable(); 467 npxsave(&dummy); 468 stop_emulating(); 469#ifdef CPU_ENABLE_SSE 470 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 471 if (cpu_fxsr) 472 fninit(); 473#endif 474 fldcw(&control); 475 start_emulating(); 476 intr_restore(savecrit); 477} 478 479/* 480 * Free coprocessor (if we have it). 481 */ 482void 483npxexit(td) 484 struct thread *td; 485{ 486 register_t savecrit; 487 488 savecrit = intr_disable(); 489 if (curthread == PCPU_GET(fpcurthread)) 490 npxsave(&PCPU_GET(curpcb)->pcb_save); 491 intr_restore(savecrit); 492#ifdef NPX_DEBUG 493 if (npx_exists) { 494 u_int masked_exceptions; 495 496 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 497 /* 498 * Log exceptions that would have trapped with the old 499 * control word (overflow, divide by 0, and invalid operand). 500 */ 501 if (masked_exceptions & 0x0d) 502 log(LOG_ERR, 503 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 504 td->td_proc->p_pid, td->td_proc->p_comm, 505 masked_exceptions); 506 } 507#endif 508} 509 510int 511npxformat() 512{ 513 514 if (!npx_exists) 515 return (_MC_FPFMT_NODEV); 516#ifdef CPU_ENABLE_SSE 517 if (cpu_fxsr) 518 return (_MC_FPFMT_XMM); 519#endif 520 return (_MC_FPFMT_387); 521} 522 523/* 524 * The following mechanism is used to ensure that the FPE_... value 525 * that is passed as a trapcode to the signal handler of the user 526 * process does not have more than one bit set. 527 * 528 * Multiple bits may be set if the user process modifies the control 529 * word while a status word bit is already set. While this is a sign 530 * of bad coding, we have no choise than to narrow them down to one 531 * bit, since we must not send a trapcode that is not exactly one of 532 * the FPE_ macros. 533 * 534 * The mechanism has a static table with 127 entries. Each combination 535 * of the 7 FPU status word exception bits directly translates to a 536 * position in this table, where a single FPE_... value is stored. 537 * This FPE_... value stored there is considered the "most important" 538 * of the exception bits and will be sent as the signal code. The 539 * precedence of the bits is based upon Intel Document "Numerical 540 * Applications", Chapter "Special Computational Situations". 541 * 542 * The macro to choose one of these values does these steps: 1) Throw 543 * away status word bits that cannot be masked. 2) Throw away the bits 544 * currently masked in the control word, assuming the user isn't 545 * interested in them anymore. 3) Reinsert status word bit 7 (stack 546 * fault) if it is set, which cannot be masked but must be presered. 547 * 4) Use the remaining bits to point into the trapcode table. 548 * 549 * The 6 maskable bits in order of their preference, as stated in the 550 * above referenced Intel manual: 551 * 1 Invalid operation (FP_X_INV) 552 * 1a Stack underflow 553 * 1b Stack overflow 554 * 1c Operand of unsupported format 555 * 1d SNaN operand. 556 * 2 QNaN operand (not an exception, irrelavant here) 557 * 3 Any other invalid-operation not mentioned above or zero divide 558 * (FP_X_INV, FP_X_DZ) 559 * 4 Denormal operand (FP_X_DNML) 560 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 561 * 6 Inexact result (FP_X_IMP) 562 */ 563static char fpetable[128] = { 564 0, 565 FPE_FLTINV, /* 1 - INV */ 566 FPE_FLTUND, /* 2 - DNML */ 567 FPE_FLTINV, /* 3 - INV | DNML */ 568 FPE_FLTDIV, /* 4 - DZ */ 569 FPE_FLTINV, /* 5 - INV | DZ */ 570 FPE_FLTDIV, /* 6 - DNML | DZ */ 571 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 572 FPE_FLTOVF, /* 8 - OFL */ 573 FPE_FLTINV, /* 9 - INV | OFL */ 574 FPE_FLTUND, /* A - DNML | OFL */ 575 FPE_FLTINV, /* B - INV | DNML | OFL */ 576 FPE_FLTDIV, /* C - DZ | OFL */ 577 FPE_FLTINV, /* D - INV | DZ | OFL */ 578 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 579 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 580 FPE_FLTUND, /* 10 - UFL */ 581 FPE_FLTINV, /* 11 - INV | UFL */ 582 FPE_FLTUND, /* 12 - DNML | UFL */ 583 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 584 FPE_FLTDIV, /* 14 - DZ | UFL */ 585 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 586 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 587 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 588 FPE_FLTOVF, /* 18 - OFL | UFL */ 589 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 590 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 591 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 592 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 593 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 594 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 595 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 596 FPE_FLTRES, /* 20 - IMP */ 597 FPE_FLTINV, /* 21 - INV | IMP */ 598 FPE_FLTUND, /* 22 - DNML | IMP */ 599 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 600 FPE_FLTDIV, /* 24 - DZ | IMP */ 601 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 602 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 603 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 604 FPE_FLTOVF, /* 28 - OFL | IMP */ 605 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 606 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 607 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 608 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 609 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 610 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 611 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 612 FPE_FLTUND, /* 30 - UFL | IMP */ 613 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 614 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 615 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 616 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 617 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 618 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 619 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 620 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 621 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 622 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 623 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 624 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 625 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 626 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 627 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 628 FPE_FLTSUB, /* 40 - STK */ 629 FPE_FLTSUB, /* 41 - INV | STK */ 630 FPE_FLTUND, /* 42 - DNML | STK */ 631 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 632 FPE_FLTDIV, /* 44 - DZ | STK */ 633 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 634 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 635 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 636 FPE_FLTOVF, /* 48 - OFL | STK */ 637 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 638 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 639 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 640 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 641 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 642 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 643 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 644 FPE_FLTUND, /* 50 - UFL | STK */ 645 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 646 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 647 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 648 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 649 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 650 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 651 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 652 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 653 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 654 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 655 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 656 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 657 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 658 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 659 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 660 FPE_FLTRES, /* 60 - IMP | STK */ 661 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 662 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 663 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 664 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 665 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 666 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 667 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 668 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 669 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 670 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 671 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 672 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 673 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 674 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 675 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 676 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 677 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 678 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 679 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 680 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 681 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 682 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 683 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 684 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 685 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 686 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 687 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 688 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 689 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 690 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 691 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 692}; 693 694/* 695 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 696 * 697 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 698 * depend on longjmp() restoring a usable state. Restoring the state 699 * or examining it might fail if we didn't clear exceptions. 700 * 701 * The error code chosen will be one of the FPE_... macros. It will be 702 * sent as the second argument to old BSD-style signal handlers and as 703 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 704 * 705 * XXX the FP state is not preserved across signal handlers. So signal 706 * handlers cannot afford to do FP unless they preserve the state or 707 * longjmp() out. Both preserving the state and longjmp()ing may be 708 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 709 * solution for signals other than SIGFPE. 710 */ 711int 712npxtrap() 713{ 714 register_t savecrit; 715 u_short control, status; 716 717 if (!npx_exists) { 718 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 719 PCPU_GET(fpcurthread), curthread, npx_exists); 720 panic("npxtrap from nowhere"); 721 } 722 savecrit = intr_disable(); 723 724 /* 725 * Interrupt handling (for another interrupt) may have pushed the 726 * state to memory. Fetch the relevant parts of the state from 727 * wherever they are. 728 */ 729 if (PCPU_GET(fpcurthread) != curthread) { 730 control = GET_FPU_CW(curthread); 731 status = GET_FPU_SW(curthread); 732 } else { 733 fnstcw(&control); 734 fnstsw(&status); 735 } 736 737 if (PCPU_GET(fpcurthread) == curthread) 738 fnclex(); 739 intr_restore(savecrit); 740 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 741} 742 743/* 744 * Implement device not available (DNA) exception 745 * 746 * It would be better to switch FP context here (if curthread != fpcurthread) 747 * and not necessarily for every context switch, but it is too hard to 748 * access foreign pcb's. 749 */ 750 751static int err_count = 0; 752 753int 754npxdna() 755{ 756 struct pcb *pcb; 757 register_t s; 758#ifdef CPU_ENABLE_SSE 759 int mxcsr; 760#endif 761 u_short control; 762 763 if (!npx_exists) 764 return (0); 765 if (PCPU_GET(fpcurthread) == curthread) { 766 printf("npxdna: fpcurthread == curthread %d times\n", 767 ++err_count); 768 stop_emulating(); 769 return (1); 770 } 771 if (PCPU_GET(fpcurthread) != NULL) { 772 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 773 PCPU_GET(fpcurthread), 774 PCPU_GET(fpcurthread)->td_proc->p_pid, 775 curthread, curthread->td_proc->p_pid); 776 panic("npxdna"); 777 } 778 s = intr_disable(); 779 stop_emulating(); 780 /* 781 * Record new context early in case frstor causes an IRQ13. 782 */ 783 PCPU_SET(fpcurthread, curthread); 784 pcb = PCPU_GET(curpcb); 785 786 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 787 /* 788 * This is the first time this thread has used the FPU or 789 * the PCB doesn't contain a clean FPU state. Explicitly 790 * initialize the FPU and load the default control word. 791 */ 792 fninit(); 793 control = __INITIAL_NPXCW__; 794 fldcw(&control); 795#ifdef CPU_ENABLE_SSE 796 if (cpu_fxsr) { 797 mxcsr = __INITIAL_MXCSR__; 798 ldmxcsr(mxcsr); 799 } 800#endif 801 pcb->pcb_flags |= PCB_NPXINITDONE; 802 } else { 803 /* 804 * The following frstor may cause an IRQ13 when the state 805 * being restored has a pending error. The error will 806 * appear to have been triggered by the current (npx) user 807 * instruction even when that instruction is a no-wait 808 * instruction that should not trigger an error (e.g., 809 * fnclex). On at least one 486 system all of the no-wait 810 * instructions are broken the same as frstor, so our 811 * treatment does not amplify the breakage. On at least 812 * one 386/Cyrix 387 system, fnclex works correctly while 813 * frstor and fnsave are broken, so our treatment breaks 814 * fnclex if it is the first FPU instruction after a context 815 * switch. 816 */ 817 fpurstor(&pcb->pcb_save); 818 } 819 intr_restore(s); 820 821 return (1); 822} 823 824/* 825 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 826 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 827 * no-wait npx instructions. See the Intel application note AP-578 for 828 * details. This doesn't cause any additional complications here. IRQ13's 829 * are inherently asynchronous unless the CPU is frozen to deliver them -- 830 * one that started in userland may be delivered many instructions later, 831 * after the process has entered the kernel. It may even be delivered after 832 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 833 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 834 * it is normally ignored at first because we set fpcurthread to NULL; it is 835 * normally retriggered in npxdna() after return to user mode. 836 * 837 * npxsave() must be called with interrupts disabled, so that it clears 838 * fpcurthread atomically with saving the state. We require callers to do the 839 * disabling, since most callers need to disable interrupts anyway to call 840 * npxsave() atomically with checking fpcurthread. 841 * 842 * A previous version of npxsave() went to great lengths to excecute fnsave 843 * with interrupts enabled in case executing it froze the CPU. This case 844 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 845 * spurious freezes. 846 */ 847void 848npxsave(addr) 849 union savefpu *addr; 850{ 851 852 stop_emulating(); 853 fpusave(addr); 854 855 start_emulating(); 856 PCPU_SET(fpcurthread, NULL); 857} 858 859/* 860 * This should be called with interrupts disabled and only when the owning 861 * FPU thread is non-null. 862 */ 863void 864npxdrop() 865{ 866 struct thread *td; 867 868 /* 869 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 870 * ones don't cause a panic on the next frstor. 871 */ 872#ifdef CPU_ENABLE_SSE 873 if (!cpu_fxsr) 874#endif 875 fnclex(); 876 877 td = PCPU_GET(fpcurthread); 878 PCPU_SET(fpcurthread, NULL); 879 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 880 start_emulating(); 881} 882 883/* 884 * Get the state of the FPU without dropping ownership (if possible). 885 * It returns the FPU ownership status. 886 */ 887int 888npxgetregs(td, addr) 889 struct thread *td; 890 union savefpu *addr; 891{ 892 register_t s; 893 894 if (!npx_exists) 895 return (_MC_FPOWNED_NONE); 896 897 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 898 if (npx_cleanstate_ready) 899 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 900 else 901 bzero(addr, sizeof(*addr)); 902 return (_MC_FPOWNED_NONE); 903 } 904 s = intr_disable(); 905 if (td == PCPU_GET(fpcurthread)) { 906 fpusave(addr); 907#ifdef CPU_ENABLE_SSE 908 if (!cpu_fxsr) 909#endif 910 /* 911 * fnsave initializes the FPU and destroys whatever 912 * context it contains. Make sure the FPU owner 913 * starts with a clean state next time. 914 */ 915 npxdrop(); 916 intr_restore(s); 917 return (_MC_FPOWNED_FPU); 918 } else { 919 intr_restore(s); 920 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 921 return (_MC_FPOWNED_PCB); 922 } 923} 924 925/* 926 * Set the state of the FPU. 927 */ 928void 929npxsetregs(td, addr) 930 struct thread *td; 931 union savefpu *addr; 932{ 933 register_t s; 934 935 if (!npx_exists) 936 return; 937 938 s = intr_disable(); 939 if (td == PCPU_GET(fpcurthread)) { 940#ifdef CPU_ENABLE_SSE 941 if (!cpu_fxsr) 942#endif 943 fnclex(); /* As in npxdrop(). */ 944 fpurstor(addr); 945 intr_restore(s); 946 } else { 947 intr_restore(s); 948 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 949 } 950 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 951} 952 953static void 954fpusave(addr) 955 union savefpu *addr; 956{ 957 958#ifdef CPU_ENABLE_SSE 959 if (cpu_fxsr) 960 fxsave(addr); 961 else 962#endif 963 fnsave(addr); 964} 965 966static void 967fpurstor(addr) 968 union savefpu *addr; 969{ 970 971#ifdef CPU_ENABLE_SSE 972 if (cpu_fxsr) 973 fxrstor(addr); 974 else 975#endif 976 frstor(addr); 977} 978 979#ifdef I586_CPU_XXX 980static long 981timezero(funcname, func) 982 const char *funcname; 983 void (*func)(void *buf, size_t len); 984 985{ 986 void *buf; 987#define BUFSIZE 1048576 988 long usec; 989 struct timeval finish, start; 990 991 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 992 if (buf == NULL) 993 return (BUFSIZE); 994 microtime(&start); 995 (*func)(buf, BUFSIZE); 996 microtime(&finish); 997 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 998 finish.tv_usec - start.tv_usec; 999 if (usec <= 0) 1000 usec = 1; 1001 if (bootverbose) 1002 printf("%s bandwidth = %u kBps\n", funcname, 1003 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1004 free(buf, M_TEMP); 1005 return (usec); 1006} 1007#endif /* I586_CPU */ 1008 1009static device_method_t npx_methods[] = { 1010 /* Device interface */ 1011 DEVMETHOD(device_identify, npx_identify), 1012 DEVMETHOD(device_probe, npx_probe), 1013 DEVMETHOD(device_attach, npx_attach), 1014 DEVMETHOD(device_detach, bus_generic_detach), 1015 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1016 DEVMETHOD(device_suspend, bus_generic_suspend), 1017 DEVMETHOD(device_resume, bus_generic_resume), 1018 1019 { 0, 0 } 1020}; 1021 1022static driver_t npx_driver = { 1023 "npx", 1024 npx_methods, 1025 1, /* no softc */ 1026}; 1027 1028static devclass_t npx_devclass; 1029 1030/* 1031 * We prefer to attach to the root nexus so that the usual case (exception 16) 1032 * doesn't describe the processor as being `on isa'. 1033 */ 1034DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1035 1036#ifdef DEV_ISA 1037/* 1038 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1039 */ 1040static struct isa_pnp_id npxisa_ids[] = { 1041 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1042 { 0 } 1043}; 1044 1045static int 1046npxisa_probe(device_t dev) 1047{ 1048 int result; 1049 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1050 device_quiet(dev); 1051 } 1052 return(result); 1053} 1054 1055static int 1056npxisa_attach(device_t dev) 1057{ 1058 return (0); 1059} 1060 1061static device_method_t npxisa_methods[] = { 1062 /* Device interface */ 1063 DEVMETHOD(device_probe, npxisa_probe), 1064 DEVMETHOD(device_attach, npxisa_attach), 1065 DEVMETHOD(device_detach, bus_generic_detach), 1066 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1067 DEVMETHOD(device_suspend, bus_generic_suspend), 1068 DEVMETHOD(device_resume, bus_generic_resume), 1069 1070 { 0, 0 } 1071}; 1072 1073static driver_t npxisa_driver = { 1074 "npxisa", 1075 npxisa_methods, 1076 1, /* no softc */ 1077}; 1078 1079static devclass_t npxisa_devclass; 1080 1081DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1082#ifndef PC98 1083DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1084#endif 1085#endif /* DEV_ISA */ 1086