npx.c revision 143712
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 143712 2005-03-16 20:31:46Z imp $"); 35 36#include "opt_cpu.h" 37#include "opt_debug_npx.h" 38#include "opt_isa.h" 39#include "opt_npx.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/module.h> 48#include <sys/mutex.h> 49#include <sys/mutex.h> 50#include <sys/proc.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59 60#include <machine/asmacros.h> 61#include <machine/cputypes.h> 62#include <machine/frame.h> 63#include <machine/md_var.h> 64#include <machine/pcb.h> 65#include <machine/psl.h> 66#include <machine/clock.h> 67#include <machine/resource.h> 68#include <machine/specialreg.h> 69#include <machine/segments.h> 70#include <machine/ucontext.h> 71 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#else 75#include <i386/isa/isa.h> 76#endif 77#include <machine/intr_machdep.h> 78#ifdef DEV_ISA 79#include <isa/isavar.h> 80#endif 81 82#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 83#define CPU_ENABLE_SSE 84#endif 85#if defined(CPU_DISABLE_SSE) 86#undef CPU_ENABLE_SSE 87#endif 88 89/* 90 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 91 */ 92 93/* Configuration flags. */ 94#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 95#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 96#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 97 98#if defined(__GNUCLIKE_ASM) && !defined(lint) 99 100#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 101#define fnclex() __asm("fnclex") 102#define fninit() __asm("fninit") 103#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 104#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 105#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 106#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 107#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 108#ifdef CPU_ENABLE_SSE 109#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 110#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 111#endif 112#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 113 : : "n" (CR0_TS) : "ax") 114#define stop_emulating() __asm("clts") 115 116#else /* !(__GNUCLIKE_ASM && !lint) */ 117 118void fldcw(caddr_t addr); 119void fnclex(void); 120void fninit(void); 121void fnsave(caddr_t addr); 122void fnstcw(caddr_t addr); 123void fnstsw(caddr_t addr); 124void fp_divide_by_0(void); 125void frstor(caddr_t addr); 126#ifdef CPU_ENABLE_SSE 127void fxsave(caddr_t addr); 128void fxrstor(caddr_t addr); 129#endif 130void start_emulating(void); 131void stop_emulating(void); 132 133#endif /* __GNUCLIKE_ASM && !lint */ 134 135#ifdef CPU_ENABLE_SSE 136#define GET_FPU_CW(thread) \ 137 (cpu_fxsr ? \ 138 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 139 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 140#define GET_FPU_SW(thread) \ 141 (cpu_fxsr ? \ 142 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 143 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 144#else /* CPU_ENABLE_SSE */ 145#define GET_FPU_CW(thread) \ 146 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 147#define GET_FPU_SW(thread) \ 148 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 149#endif /* CPU_ENABLE_SSE */ 150 151typedef u_char bool_t; 152 153static void fpusave(union savefpu *); 154static void fpurstor(union savefpu *); 155static int npx_attach(device_t dev); 156static void npx_identify(driver_t *driver, device_t parent); 157static void npx_intr(void *); 158static int npx_probe(device_t dev); 159#ifdef I586_CPU_XXX 160static long timezero(const char *funcname, 161 void (*func)(void *buf, size_t len)); 162#endif /* I586_CPU */ 163 164int hw_float; /* XXX currently just alias for npx_exists */ 165 166SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 167 CTLFLAG_RD, &hw_float, 0, 168 "Floatingpoint instructions executed in hardware"); 169 170static volatile u_int npx_intrs_while_probing; 171static volatile u_int npx_traps_while_probing; 172 173static union savefpu npx_cleanstate; 174static bool_t npx_cleanstate_ready; 175static bool_t npx_ex16; 176static bool_t npx_exists; 177static bool_t npx_irq13; 178 179alias_for_inthand_t probetrap; 180__asm(" \n\ 181 .text \n\ 182 .p2align 2,0x90 \n\ 183 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 184" __XSTRING(CNAME(probetrap)) ": \n\ 185 ss \n\ 186 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 187 fnclex \n\ 188 iret \n\ 189"); 190 191/* 192 * Identify routine. Create a connection point on our parent for probing. 193 */ 194static void 195npx_identify(driver, parent) 196 driver_t *driver; 197 device_t parent; 198{ 199 device_t child; 200 201 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 202 if (child == NULL) 203 panic("npx_identify"); 204} 205 206/* 207 * Do minimal handling of npx interrupts to convert them to traps. 208 */ 209static void 210npx_intr(dummy) 211 void *dummy; 212{ 213 struct thread *td; 214 215 npx_intrs_while_probing++; 216 217 /* 218 * The BUSY# latch must be cleared in all cases so that the next 219 * unmasked npx exception causes an interrupt. 220 */ 221#ifdef PC98 222 outb(0xf8, 0); 223#else 224 outb(0xf0, 0); 225#endif 226 227 /* 228 * fpcurthread is normally non-null here. In that case, schedule an 229 * AST to finish the exception handling in the correct context 230 * (this interrupt may occur after the thread has entered the 231 * kernel via a syscall or an interrupt). Otherwise, the npx 232 * state of the thread that caused this interrupt must have been 233 * pushed to the thread's pcb, and clearing of the busy latch 234 * above has finished the (essentially null) handling of this 235 * interrupt. Control will eventually return to the instruction 236 * that caused it and it will repeat. We will eventually (usually 237 * soon) win the race to handle the interrupt properly. 238 */ 239 td = PCPU_GET(fpcurthread); 240 if (td != NULL) { 241 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 242 mtx_lock_spin(&sched_lock); 243 td->td_flags |= TDF_ASTPENDING; 244 mtx_unlock_spin(&sched_lock); 245 } 246} 247 248/* 249 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 250 * whether the device exists or not (XXX should be elsewhere). Set flags 251 * to tell npxattach() what to do. Modify device struct if npx doesn't 252 * need to use interrupts. Return 0 if device exists. 253 */ 254static int 255npx_probe(dev) 256 device_t dev; 257{ 258 struct gate_descriptor save_idt_npxtrap; 259 struct resource *ioport_res, *irq_res; 260 void *irq_cookie; 261 int ioport_rid, irq_num, irq_rid; 262 u_short control; 263 u_short status; 264 265 save_idt_npxtrap = idt[IDT_MF]; 266 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 267 GSEL(GCODE_SEL, SEL_KPL)); 268 ioport_rid = 0; 269 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 270 IO_NPX, IO_NPX + IO_NPXSIZE - 1, IO_NPXSIZE, RF_ACTIVE); 271 if (ioport_res == NULL) 272 panic("npx: can't get ports"); 273#ifdef PC98 274 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 275 irq_num = 8; 276#else 277 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 278 irq_num = 13; 279#endif 280 irq_rid = 0; 281 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 282 irq_num, 1, RF_ACTIVE); 283 if (irq_res == NULL) 284 panic("npx: can't get IRQ"); 285 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 286 NULL, &irq_cookie) != 0) 287 panic("npx: can't create intr"); 288 289 /* 290 * Partially reset the coprocessor, if any. Some BIOS's don't reset 291 * it after a warm boot. 292 */ 293#ifdef PC98 294 outb(0xf8,0); 295#else 296 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 297 outb(0xf0, 0); /* clear BUSY# latch */ 298#endif 299 /* 300 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 301 * instructions. We must set the CR0_MP bit and use the CR0_TS 302 * bit to control the trap, because setting the CR0_EM bit does 303 * not cause WAIT instructions to trap. It's important to trap 304 * WAIT instructions - otherwise the "wait" variants of no-wait 305 * control instructions would degenerate to the "no-wait" variants 306 * after FP context switches but work correctly otherwise. It's 307 * particularly important to trap WAITs when there is no NPX - 308 * otherwise the "wait" variants would always degenerate. 309 * 310 * Try setting CR0_NE to get correct error reporting on 486DX's. 311 * Setting it should fail or do nothing on lesser processors. 312 */ 313 load_cr0(rcr0() | CR0_MP | CR0_NE); 314 /* 315 * But don't trap while we're probing. 316 */ 317 stop_emulating(); 318 /* 319 * Finish resetting the coprocessor, if any. If there is an error 320 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 321 * it OK. Bogus halts have never been observed, but we enabled 322 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 323 */ 324 fninit(); 325 326 device_set_desc(dev, "math processor"); 327 328 /* 329 * Don't use fwait here because it might hang. 330 * Don't use fnop here because it usually hangs if there is no FPU. 331 */ 332 DELAY(1000); /* wait for any IRQ13 */ 333#ifdef DIAGNOSTIC 334 if (npx_intrs_while_probing != 0) 335 printf("fninit caused %u bogus npx interrupt(s)\n", 336 npx_intrs_while_probing); 337 if (npx_traps_while_probing != 0) 338 printf("fninit caused %u bogus npx trap(s)\n", 339 npx_traps_while_probing); 340#endif 341 /* 342 * Check for a status of mostly zero. 343 */ 344 status = 0x5a5a; 345 fnstsw(&status); 346 if ((status & 0xb8ff) == 0) { 347 /* 348 * Good, now check for a proper control word. 349 */ 350 control = 0x5a5a; 351 fnstcw(&control); 352 if ((control & 0x1f3f) == 0x033f) { 353 hw_float = npx_exists = 1; 354 /* 355 * We have an npx, now divide by 0 to see if exception 356 * 16 works. 357 */ 358 control &= ~(1 << 2); /* enable divide by 0 trap */ 359 fldcw(&control); 360#ifdef FPU_ERROR_BROKEN 361 /* 362 * FPU error signal doesn't work on some CPU 363 * accelerator board. 364 */ 365 npx_ex16 = 1; 366 return (0); 367#endif 368 npx_traps_while_probing = npx_intrs_while_probing = 0; 369 fp_divide_by_0(); 370 DELAY(1000); /* wait for any IRQ13 */ 371 if (npx_traps_while_probing != 0) { 372 /* 373 * Good, exception 16 works. 374 */ 375 npx_ex16 = 1; 376 goto no_irq13; 377 } 378 if (npx_intrs_while_probing != 0) { 379 /* 380 * Bad, we are stuck with IRQ13. 381 */ 382 npx_irq13 = 1; 383 idt[IDT_MF] = save_idt_npxtrap; 384#ifdef SMP 385 if (mp_ncpus > 1) 386 panic("npx0 cannot use IRQ 13 on an SMP system"); 387#endif 388 return (0); 389 } 390 /* 391 * Worse, even IRQ13 is broken. Use emulator. 392 */ 393 } 394 } 395 /* 396 * Probe failed, but we want to get to npxattach to initialize the 397 * emulator and say that it has been installed. XXX handle devices 398 * that aren't really devices better. 399 */ 400#ifdef SMP 401 if (mp_ncpus > 1) 402 panic("npx0 cannot be emulated on an SMP system"); 403#endif 404 /* FALLTHROUGH */ 405no_irq13: 406 idt[IDT_MF] = save_idt_npxtrap; 407 bus_teardown_intr(dev, irq_res, irq_cookie); 408 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 409 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 410 return (0); 411} 412 413/* 414 * Attach routine - announce which it is, and wire into system 415 */ 416static int 417npx_attach(dev) 418 device_t dev; 419{ 420 int flags; 421 register_t s; 422 423 flags = device_get_flags(dev); 424 425 if (npx_irq13) 426 device_printf(dev, "IRQ 13 interface\n"); 427 else if (npx_ex16) 428 device_printf(dev, "INT 16 interface\n"); 429 else 430 device_printf(dev, "WARNING: no FPU!\n"); 431 432 npxinit(__INITIAL_NPXCW__); 433 434 if (npx_cleanstate_ready == 0) { 435 s = intr_disable(); 436 stop_emulating(); 437 fpusave(&npx_cleanstate); 438 start_emulating(); 439 npx_cleanstate_ready = 1; 440 intr_restore(s); 441 } 442#ifdef I586_CPU_XXX 443 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 444 timezero("i586_bzero()", i586_bzero) < 445 timezero("bzero()", bzero) * 4 / 5) { 446 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 447 bcopy_vector = i586_bcopy; 448 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 449 bzero_vector = i586_bzero; 450 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 451 copyin_vector = i586_copyin; 452 copyout_vector = i586_copyout; 453 } 454 } 455#endif 456 457 return (0); /* XXX unused */ 458} 459 460/* 461 * Initialize floating point unit. 462 */ 463void 464npxinit(control) 465 u_short control; 466{ 467 static union savefpu dummy; 468 register_t savecrit; 469 470 if (!npx_exists) 471 return; 472 /* 473 * fninit has the same h/w bugs as fnsave. Use the detoxified 474 * fnsave to throw away any junk in the fpu. npxsave() initializes 475 * the fpu and sets fpcurthread = NULL as important side effects. 476 */ 477 savecrit = intr_disable(); 478 npxsave(&dummy); 479 stop_emulating(); 480#ifdef CPU_ENABLE_SSE 481 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 482 if (cpu_fxsr) 483 fninit(); 484#endif 485 fldcw(&control); 486 start_emulating(); 487 intr_restore(savecrit); 488} 489 490/* 491 * Free coprocessor (if we have it). 492 */ 493void 494npxexit(td) 495 struct thread *td; 496{ 497 register_t savecrit; 498 499 savecrit = intr_disable(); 500 if (curthread == PCPU_GET(fpcurthread)) 501 npxsave(&PCPU_GET(curpcb)->pcb_save); 502 intr_restore(savecrit); 503#ifdef NPX_DEBUG 504 if (npx_exists) { 505 u_int masked_exceptions; 506 507 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 508 /* 509 * Log exceptions that would have trapped with the old 510 * control word (overflow, divide by 0, and invalid operand). 511 */ 512 if (masked_exceptions & 0x0d) 513 log(LOG_ERR, 514 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 515 td->td_proc->p_pid, td->td_proc->p_comm, 516 masked_exceptions); 517 } 518#endif 519} 520 521int 522npxformat() 523{ 524 525 if (!npx_exists) 526 return (_MC_FPFMT_NODEV); 527#ifdef CPU_ENABLE_SSE 528 if (cpu_fxsr) 529 return (_MC_FPFMT_XMM); 530#endif 531 return (_MC_FPFMT_387); 532} 533 534/* 535 * The following mechanism is used to ensure that the FPE_... value 536 * that is passed as a trapcode to the signal handler of the user 537 * process does not have more than one bit set. 538 * 539 * Multiple bits may be set if the user process modifies the control 540 * word while a status word bit is already set. While this is a sign 541 * of bad coding, we have no choise than to narrow them down to one 542 * bit, since we must not send a trapcode that is not exactly one of 543 * the FPE_ macros. 544 * 545 * The mechanism has a static table with 127 entries. Each combination 546 * of the 7 FPU status word exception bits directly translates to a 547 * position in this table, where a single FPE_... value is stored. 548 * This FPE_... value stored there is considered the "most important" 549 * of the exception bits and will be sent as the signal code. The 550 * precedence of the bits is based upon Intel Document "Numerical 551 * Applications", Chapter "Special Computational Situations". 552 * 553 * The macro to choose one of these values does these steps: 1) Throw 554 * away status word bits that cannot be masked. 2) Throw away the bits 555 * currently masked in the control word, assuming the user isn't 556 * interested in them anymore. 3) Reinsert status word bit 7 (stack 557 * fault) if it is set, which cannot be masked but must be presered. 558 * 4) Use the remaining bits to point into the trapcode table. 559 * 560 * The 6 maskable bits in order of their preference, as stated in the 561 * above referenced Intel manual: 562 * 1 Invalid operation (FP_X_INV) 563 * 1a Stack underflow 564 * 1b Stack overflow 565 * 1c Operand of unsupported format 566 * 1d SNaN operand. 567 * 2 QNaN operand (not an exception, irrelavant here) 568 * 3 Any other invalid-operation not mentioned above or zero divide 569 * (FP_X_INV, FP_X_DZ) 570 * 4 Denormal operand (FP_X_DNML) 571 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 572 * 6 Inexact result (FP_X_IMP) 573 */ 574static char fpetable[128] = { 575 0, 576 FPE_FLTINV, /* 1 - INV */ 577 FPE_FLTUND, /* 2 - DNML */ 578 FPE_FLTINV, /* 3 - INV | DNML */ 579 FPE_FLTDIV, /* 4 - DZ */ 580 FPE_FLTINV, /* 5 - INV | DZ */ 581 FPE_FLTDIV, /* 6 - DNML | DZ */ 582 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 583 FPE_FLTOVF, /* 8 - OFL */ 584 FPE_FLTINV, /* 9 - INV | OFL */ 585 FPE_FLTUND, /* A - DNML | OFL */ 586 FPE_FLTINV, /* B - INV | DNML | OFL */ 587 FPE_FLTDIV, /* C - DZ | OFL */ 588 FPE_FLTINV, /* D - INV | DZ | OFL */ 589 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 590 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 591 FPE_FLTUND, /* 10 - UFL */ 592 FPE_FLTINV, /* 11 - INV | UFL */ 593 FPE_FLTUND, /* 12 - DNML | UFL */ 594 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 595 FPE_FLTDIV, /* 14 - DZ | UFL */ 596 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 597 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 598 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 599 FPE_FLTOVF, /* 18 - OFL | UFL */ 600 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 601 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 602 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 603 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 604 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 605 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 606 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 607 FPE_FLTRES, /* 20 - IMP */ 608 FPE_FLTINV, /* 21 - INV | IMP */ 609 FPE_FLTUND, /* 22 - DNML | IMP */ 610 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 611 FPE_FLTDIV, /* 24 - DZ | IMP */ 612 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 613 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 614 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 615 FPE_FLTOVF, /* 28 - OFL | IMP */ 616 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 617 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 618 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 619 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 620 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 621 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 622 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 623 FPE_FLTUND, /* 30 - UFL | IMP */ 624 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 625 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 626 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 627 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 628 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 629 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 630 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 631 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 632 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 633 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 634 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 635 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 636 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 637 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 638 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 639 FPE_FLTSUB, /* 40 - STK */ 640 FPE_FLTSUB, /* 41 - INV | STK */ 641 FPE_FLTUND, /* 42 - DNML | STK */ 642 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 643 FPE_FLTDIV, /* 44 - DZ | STK */ 644 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 645 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 646 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 647 FPE_FLTOVF, /* 48 - OFL | STK */ 648 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 649 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 650 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 651 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 652 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 653 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 654 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 655 FPE_FLTUND, /* 50 - UFL | STK */ 656 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 657 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 658 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 659 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 660 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 661 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 662 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 663 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 664 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 665 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 666 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 667 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 668 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 669 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 670 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 671 FPE_FLTRES, /* 60 - IMP | STK */ 672 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 673 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 674 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 675 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 676 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 677 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 678 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 679 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 680 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 681 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 682 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 683 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 684 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 685 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 686 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 687 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 688 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 689 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 691 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 693 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 695 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 697 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 699 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 700 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 701 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 702 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 703}; 704 705/* 706 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 707 * 708 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 709 * depend on longjmp() restoring a usable state. Restoring the state 710 * or examining it might fail if we didn't clear exceptions. 711 * 712 * The error code chosen will be one of the FPE_... macros. It will be 713 * sent as the second argument to old BSD-style signal handlers and as 714 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 715 * 716 * XXX the FP state is not preserved across signal handlers. So signal 717 * handlers cannot afford to do FP unless they preserve the state or 718 * longjmp() out. Both preserving the state and longjmp()ing may be 719 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 720 * solution for signals other than SIGFPE. 721 */ 722int 723npxtrap() 724{ 725 register_t savecrit; 726 u_short control, status; 727 728 if (!npx_exists) { 729 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 730 PCPU_GET(fpcurthread), curthread, npx_exists); 731 panic("npxtrap from nowhere"); 732 } 733 savecrit = intr_disable(); 734 735 /* 736 * Interrupt handling (for another interrupt) may have pushed the 737 * state to memory. Fetch the relevant parts of the state from 738 * wherever they are. 739 */ 740 if (PCPU_GET(fpcurthread) != curthread) { 741 control = GET_FPU_CW(curthread); 742 status = GET_FPU_SW(curthread); 743 } else { 744 fnstcw(&control); 745 fnstsw(&status); 746 } 747 748 if (PCPU_GET(fpcurthread) == curthread) 749 fnclex(); 750 intr_restore(savecrit); 751 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 752} 753 754/* 755 * Implement device not available (DNA) exception 756 * 757 * It would be better to switch FP context here (if curthread != fpcurthread) 758 * and not necessarily for every context switch, but it is too hard to 759 * access foreign pcb's. 760 */ 761 762static int err_count = 0; 763 764int 765npxdna() 766{ 767 struct pcb *pcb; 768 register_t s; 769 u_short control; 770 771 if (!npx_exists) 772 return (0); 773 if (PCPU_GET(fpcurthread) == curthread) { 774 printf("npxdna: fpcurthread == curthread %d times\n", 775 ++err_count); 776 stop_emulating(); 777 return (1); 778 } 779 if (PCPU_GET(fpcurthread) != NULL) { 780 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 781 PCPU_GET(fpcurthread), 782 PCPU_GET(fpcurthread)->td_proc->p_pid, 783 curthread, curthread->td_proc->p_pid); 784 panic("npxdna"); 785 } 786 s = intr_disable(); 787 stop_emulating(); 788 /* 789 * Record new context early in case frstor causes an IRQ13. 790 */ 791 PCPU_SET(fpcurthread, curthread); 792 pcb = PCPU_GET(curpcb); 793 794 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 795 /* 796 * This is the first time this thread has used the FPU or 797 * the PCB doesn't contain a clean FPU state. Explicitly 798 * initialize the FPU and load the default control word. 799 */ 800 fninit(); 801 control = __INITIAL_NPXCW__; 802 fldcw(&control); 803 pcb->pcb_flags |= PCB_NPXINITDONE; 804 } else { 805 /* 806 * The following frstor may cause an IRQ13 when the state 807 * being restored has a pending error. The error will 808 * appear to have been triggered by the current (npx) user 809 * instruction even when that instruction is a no-wait 810 * instruction that should not trigger an error (e.g., 811 * fnclex). On at least one 486 system all of the no-wait 812 * instructions are broken the same as frstor, so our 813 * treatment does not amplify the breakage. On at least 814 * one 386/Cyrix 387 system, fnclex works correctly while 815 * frstor and fnsave are broken, so our treatment breaks 816 * fnclex if it is the first FPU instruction after a context 817 * switch. 818 */ 819 fpurstor(&pcb->pcb_save); 820 } 821 intr_restore(s); 822 823 return (1); 824} 825 826/* 827 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 828 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 829 * no-wait npx instructions. See the Intel application note AP-578 for 830 * details. This doesn't cause any additional complications here. IRQ13's 831 * are inherently asynchronous unless the CPU is frozen to deliver them -- 832 * one that started in userland may be delivered many instructions later, 833 * after the process has entered the kernel. It may even be delivered after 834 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 835 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 836 * it is normally ignored at first because we set fpcurthread to NULL; it is 837 * normally retriggered in npxdna() after return to user mode. 838 * 839 * npxsave() must be called with interrupts disabled, so that it clears 840 * fpcurthread atomically with saving the state. We require callers to do the 841 * disabling, since most callers need to disable interrupts anyway to call 842 * npxsave() atomically with checking fpcurthread. 843 * 844 * A previous version of npxsave() went to great lengths to excecute fnsave 845 * with interrupts enabled in case executing it froze the CPU. This case 846 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 847 * spurious freezes. 848 */ 849void 850npxsave(addr) 851 union savefpu *addr; 852{ 853 854 stop_emulating(); 855 fpusave(addr); 856 857 start_emulating(); 858 PCPU_SET(fpcurthread, NULL); 859} 860 861/* 862 * This should be called with interrupts disabled and only when the owning 863 * FPU thread is non-null. 864 */ 865void 866npxdrop() 867{ 868 struct thread *td; 869 870 /* 871 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 872 * ones don't cause a panic on the next frstor. 873 */ 874#ifdef CPU_ENABLE_SSE 875 if (!cpu_fxsr) 876#endif 877 fnclex(); 878 879 td = PCPU_GET(fpcurthread); 880 PCPU_SET(fpcurthread, NULL); 881 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 882 start_emulating(); 883} 884 885/* 886 * Get the state of the FPU without dropping ownership (if possible). 887 * It returns the FPU ownership status. 888 */ 889int 890npxgetregs(td, addr) 891 struct thread *td; 892 union savefpu *addr; 893{ 894 register_t s; 895 896 if (!npx_exists) 897 return (_MC_FPOWNED_NONE); 898 899 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 900 if (npx_cleanstate_ready) 901 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 902 else 903 bzero(addr, sizeof(*addr)); 904 return (_MC_FPOWNED_NONE); 905 } 906 s = intr_disable(); 907 if (td == PCPU_GET(fpcurthread)) { 908 fpusave(addr); 909#ifdef CPU_ENABLE_SSE 910 if (!cpu_fxsr) 911#endif 912 /* 913 * fnsave initializes the FPU and destroys whatever 914 * context it contains. Make sure the FPU owner 915 * starts with a clean state next time. 916 */ 917 npxdrop(); 918 intr_restore(s); 919 return (_MC_FPOWNED_FPU); 920 } else { 921 intr_restore(s); 922 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 923 return (_MC_FPOWNED_PCB); 924 } 925} 926 927/* 928 * Set the state of the FPU. 929 */ 930void 931npxsetregs(td, addr) 932 struct thread *td; 933 union savefpu *addr; 934{ 935 register_t s; 936 937 if (!npx_exists) 938 return; 939 940 s = intr_disable(); 941 if (td == PCPU_GET(fpcurthread)) { 942#ifdef CPU_ENABLE_SSE 943 if (!cpu_fxsr) 944#endif 945 fnclex(); /* As in npxdrop(). */ 946 fpurstor(addr); 947 intr_restore(s); 948 } else { 949 intr_restore(s); 950 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 951 } 952 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 953} 954 955static void 956fpusave(addr) 957 union savefpu *addr; 958{ 959 960#ifdef CPU_ENABLE_SSE 961 if (cpu_fxsr) 962 fxsave(addr); 963 else 964#endif 965 fnsave(addr); 966} 967 968static void 969fpurstor(addr) 970 union savefpu *addr; 971{ 972 973#ifdef CPU_ENABLE_SSE 974 if (cpu_fxsr) 975 fxrstor(addr); 976 else 977#endif 978 frstor(addr); 979} 980 981#ifdef I586_CPU_XXX 982static long 983timezero(funcname, func) 984 const char *funcname; 985 void (*func)(void *buf, size_t len); 986 987{ 988 void *buf; 989#define BUFSIZE 1048576 990 long usec; 991 struct timeval finish, start; 992 993 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 994 if (buf == NULL) 995 return (BUFSIZE); 996 microtime(&start); 997 (*func)(buf, BUFSIZE); 998 microtime(&finish); 999 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1000 finish.tv_usec - start.tv_usec; 1001 if (usec <= 0) 1002 usec = 1; 1003 if (bootverbose) 1004 printf("%s bandwidth = %u kBps\n", funcname, 1005 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1006 free(buf, M_TEMP); 1007 return (usec); 1008} 1009#endif /* I586_CPU */ 1010 1011static device_method_t npx_methods[] = { 1012 /* Device interface */ 1013 DEVMETHOD(device_identify, npx_identify), 1014 DEVMETHOD(device_probe, npx_probe), 1015 DEVMETHOD(device_attach, npx_attach), 1016 DEVMETHOD(device_detach, bus_generic_detach), 1017 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1018 DEVMETHOD(device_suspend, bus_generic_suspend), 1019 DEVMETHOD(device_resume, bus_generic_resume), 1020 1021 { 0, 0 } 1022}; 1023 1024static driver_t npx_driver = { 1025 "npx", 1026 npx_methods, 1027 1, /* no softc */ 1028}; 1029 1030static devclass_t npx_devclass; 1031 1032/* 1033 * We prefer to attach to the root nexus so that the usual case (exception 16) 1034 * doesn't describe the processor as being `on isa'. 1035 */ 1036DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1037 1038#ifdef DEV_ISA 1039/* 1040 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1041 */ 1042static struct isa_pnp_id npxisa_ids[] = { 1043 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1044 { 0 } 1045}; 1046 1047static int 1048npxisa_probe(device_t dev) 1049{ 1050 int result; 1051 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1052 device_quiet(dev); 1053 } 1054 return(result); 1055} 1056 1057static int 1058npxisa_attach(device_t dev) 1059{ 1060 return (0); 1061} 1062 1063static device_method_t npxisa_methods[] = { 1064 /* Device interface */ 1065 DEVMETHOD(device_probe, npxisa_probe), 1066 DEVMETHOD(device_attach, npxisa_attach), 1067 DEVMETHOD(device_detach, bus_generic_detach), 1068 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1069 DEVMETHOD(device_suspend, bus_generic_suspend), 1070 DEVMETHOD(device_resume, bus_generic_resume), 1071 1072 { 0, 0 } 1073}; 1074 1075static driver_t npxisa_driver = { 1076 "npxisa", 1077 npxisa_methods, 1078 1, /* no softc */ 1079}; 1080 1081static devclass_t npxisa_devclass; 1082 1083DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1084#ifndef PC98 1085DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1086#endif 1087#endif /* DEV_ISA */ 1088