npx.c revision 136520
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 136520 2004-10-14 22:21:59Z njl $"); 35 36#include "opt_cpu.h" 37#include "opt_debug_npx.h" 38#include "opt_isa.h" 39#include "opt_npx.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/module.h> 48#include <sys/mutex.h> 49#include <sys/mutex.h> 50#include <sys/proc.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59#include <sys/user.h> 60 61#include <machine/asmacros.h> 62#include <machine/cputypes.h> 63#include <machine/frame.h> 64#include <machine/md_var.h> 65#include <machine/pcb.h> 66#include <machine/psl.h> 67#include <machine/clock.h> 68#include <machine/resource.h> 69#include <machine/specialreg.h> 70#include <machine/segments.h> 71#include <machine/ucontext.h> 72 73#ifdef PC98 74#include <pc98/pc98/pc98.h> 75#else 76#include <i386/isa/isa.h> 77#endif 78#include <machine/intr_machdep.h> 79#ifdef DEV_ISA 80#include <isa/isavar.h> 81#endif 82 83#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 84#define CPU_ENABLE_SSE 85#endif 86#if defined(CPU_DISABLE_SSE) 87#undef CPU_ENABLE_SSE 88#endif 89 90/* 91 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 92 */ 93 94/* Configuration flags. */ 95#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 96#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 97#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 98 99#if (defined(__GNUC__) && !defined(lint)) || defined(__INTEL_COMPILER) 100 101#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 102#define fnclex() __asm("fnclex") 103#define fninit() __asm("fninit") 104#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 105#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 106#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 107#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 108#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 109#ifdef CPU_ENABLE_SSE 110#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 111#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 112#endif 113#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 114 : : "n" (CR0_TS) : "ax") 115#define stop_emulating() __asm("clts") 116 117#else /* !((__GNUC__ && !lint ) || __INTEL_COMPILER) */ 118 119void fldcw(caddr_t addr); 120void fnclex(void); 121void fninit(void); 122void fnsave(caddr_t addr); 123void fnstcw(caddr_t addr); 124void fnstsw(caddr_t addr); 125void fp_divide_by_0(void); 126void frstor(caddr_t addr); 127#ifdef CPU_ENABLE_SSE 128void fxsave(caddr_t addr); 129void fxrstor(caddr_t addr); 130#endif 131void start_emulating(void); 132void stop_emulating(void); 133 134#endif /* (__GNUC__ && !lint ) || __INTEL_COMPILER */ 135 136#ifdef CPU_ENABLE_SSE 137#define GET_FPU_CW(thread) \ 138 (cpu_fxsr ? \ 139 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 140 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 141#define GET_FPU_SW(thread) \ 142 (cpu_fxsr ? \ 143 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 144 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 145#else /* CPU_ENABLE_SSE */ 146#define GET_FPU_CW(thread) \ 147 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 148#define GET_FPU_SW(thread) \ 149 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 150#endif /* CPU_ENABLE_SSE */ 151 152typedef u_char bool_t; 153 154static void fpusave(union savefpu *); 155static void fpurstor(union savefpu *); 156static int npx_attach(device_t dev); 157static void npx_identify(driver_t *driver, device_t parent); 158static void npx_intr(void *); 159static int npx_probe(device_t dev); 160#ifdef I586_CPU_XXX 161static long timezero(const char *funcname, 162 void (*func)(void *buf, size_t len)); 163#endif /* I586_CPU */ 164 165int hw_float; /* XXX currently just alias for npx_exists */ 166 167SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 168 CTLFLAG_RD, &hw_float, 0, 169 "Floatingpoint instructions executed in hardware"); 170 171static volatile u_int npx_intrs_while_probing; 172static volatile u_int npx_traps_while_probing; 173 174static union savefpu npx_cleanstate; 175static bool_t npx_cleanstate_ready; 176static bool_t npx_ex16; 177static bool_t npx_exists; 178static bool_t npx_irq13; 179 180alias_for_inthand_t probetrap; 181__asm(" \n\ 182 .text \n\ 183 .p2align 2,0x90 \n\ 184 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 185" __XSTRING(CNAME(probetrap)) ": \n\ 186 ss \n\ 187 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 188 fnclex \n\ 189 iret \n\ 190"); 191 192/* 193 * Identify routine. Create a connection point on our parent for probing. 194 */ 195static void 196npx_identify(driver, parent) 197 driver_t *driver; 198 device_t parent; 199{ 200 device_t child; 201 202 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 203 if (child == NULL) 204 panic("npx_identify"); 205} 206 207/* 208 * Do minimal handling of npx interrupts to convert them to traps. 209 */ 210static void 211npx_intr(dummy) 212 void *dummy; 213{ 214 struct thread *td; 215 216 npx_intrs_while_probing++; 217 218 /* 219 * The BUSY# latch must be cleared in all cases so that the next 220 * unmasked npx exception causes an interrupt. 221 */ 222#ifdef PC98 223 outb(0xf8, 0); 224#else 225 outb(0xf0, 0); 226#endif 227 228 /* 229 * fpcurthread is normally non-null here. In that case, schedule an 230 * AST to finish the exception handling in the correct context 231 * (this interrupt may occur after the thread has entered the 232 * kernel via a syscall or an interrupt). Otherwise, the npx 233 * state of the thread that caused this interrupt must have been 234 * pushed to the thread's pcb, and clearing of the busy latch 235 * above has finished the (essentially null) handling of this 236 * interrupt. Control will eventually return to the instruction 237 * that caused it and it will repeat. We will eventually (usually 238 * soon) win the race to handle the interrupt properly. 239 */ 240 td = PCPU_GET(fpcurthread); 241 if (td != NULL) { 242 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 243 mtx_lock_spin(&sched_lock); 244 td->td_flags |= TDF_ASTPENDING; 245 mtx_unlock_spin(&sched_lock); 246 } 247} 248 249/* 250 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 251 * whether the device exists or not (XXX should be elsewhere). Set flags 252 * to tell npxattach() what to do. Modify device struct if npx doesn't 253 * need to use interrupts. Return 0 if device exists. 254 */ 255static int 256npx_probe(dev) 257 device_t dev; 258{ 259 struct gate_descriptor save_idt_npxtrap; 260 struct resource *ioport_res, *irq_res; 261 void *irq_cookie; 262 int ioport_rid, irq_num, irq_rid; 263 u_short control; 264 u_short status; 265 266 save_idt_npxtrap = idt[IDT_MF]; 267 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 268 GSEL(GCODE_SEL, SEL_KPL)); 269 ioport_rid = 0; 270 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 271 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 272 if (ioport_res == NULL) 273 panic("npx: can't get ports"); 274#ifdef PC98 275 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 276 irq_num = 8; 277#else 278 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 279 irq_num = 13; 280#endif 281 irq_rid = 0; 282 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 283 irq_num, 1, RF_ACTIVE); 284 if (irq_res == NULL) 285 panic("npx: can't get IRQ"); 286 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 287 NULL, &irq_cookie) != 0) 288 panic("npx: can't create intr"); 289 290 /* 291 * Partially reset the coprocessor, if any. Some BIOS's don't reset 292 * it after a warm boot. 293 */ 294#ifdef PC98 295 outb(0xf8,0); 296#else 297 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 298 outb(0xf0, 0); /* clear BUSY# latch */ 299#endif 300 /* 301 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 302 * instructions. We must set the CR0_MP bit and use the CR0_TS 303 * bit to control the trap, because setting the CR0_EM bit does 304 * not cause WAIT instructions to trap. It's important to trap 305 * WAIT instructions - otherwise the "wait" variants of no-wait 306 * control instructions would degenerate to the "no-wait" variants 307 * after FP context switches but work correctly otherwise. It's 308 * particularly important to trap WAITs when there is no NPX - 309 * otherwise the "wait" variants would always degenerate. 310 * 311 * Try setting CR0_NE to get correct error reporting on 486DX's. 312 * Setting it should fail or do nothing on lesser processors. 313 */ 314 load_cr0(rcr0() | CR0_MP | CR0_NE); 315 /* 316 * But don't trap while we're probing. 317 */ 318 stop_emulating(); 319 /* 320 * Finish resetting the coprocessor, if any. If there is an error 321 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 322 * it OK. Bogus halts have never been observed, but we enabled 323 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 324 */ 325 fninit(); 326 327 device_set_desc(dev, "math processor"); 328 329 /* 330 * Don't use fwait here because it might hang. 331 * Don't use fnop here because it usually hangs if there is no FPU. 332 */ 333 DELAY(1000); /* wait for any IRQ13 */ 334#ifdef DIAGNOSTIC 335 if (npx_intrs_while_probing != 0) 336 printf("fninit caused %u bogus npx interrupt(s)\n", 337 npx_intrs_while_probing); 338 if (npx_traps_while_probing != 0) 339 printf("fninit caused %u bogus npx trap(s)\n", 340 npx_traps_while_probing); 341#endif 342 /* 343 * Check for a status of mostly zero. 344 */ 345 status = 0x5a5a; 346 fnstsw(&status); 347 if ((status & 0xb8ff) == 0) { 348 /* 349 * Good, now check for a proper control word. 350 */ 351 control = 0x5a5a; 352 fnstcw(&control); 353 if ((control & 0x1f3f) == 0x033f) { 354 hw_float = npx_exists = 1; 355 /* 356 * We have an npx, now divide by 0 to see if exception 357 * 16 works. 358 */ 359 control &= ~(1 << 2); /* enable divide by 0 trap */ 360 fldcw(&control); 361#ifdef FPU_ERROR_BROKEN 362 /* 363 * FPU error signal doesn't work on some CPU 364 * accelerator board. 365 */ 366 npx_ex16 = 1; 367 return (0); 368#endif 369 npx_traps_while_probing = npx_intrs_while_probing = 0; 370 fp_divide_by_0(); 371 DELAY(1000); /* wait for any IRQ13 */ 372 if (npx_traps_while_probing != 0) { 373 /* 374 * Good, exception 16 works. 375 */ 376 npx_ex16 = 1; 377 goto no_irq13; 378 } 379 if (npx_intrs_while_probing != 0) { 380 /* 381 * Bad, we are stuck with IRQ13. 382 */ 383 npx_irq13 = 1; 384 idt[IDT_MF] = save_idt_npxtrap; 385#ifdef SMP 386 if (mp_ncpus > 1) 387 panic("npx0 cannot use IRQ 13 on an SMP system"); 388#endif 389 return (0); 390 } 391 /* 392 * Worse, even IRQ13 is broken. Use emulator. 393 */ 394 } 395 } 396 /* 397 * Probe failed, but we want to get to npxattach to initialize the 398 * emulator and say that it has been installed. XXX handle devices 399 * that aren't really devices better. 400 */ 401#ifdef SMP 402 if (mp_ncpus > 1) 403 panic("npx0 cannot be emulated on an SMP system"); 404#endif 405 /* FALLTHROUGH */ 406no_irq13: 407 idt[IDT_MF] = save_idt_npxtrap; 408 bus_teardown_intr(dev, irq_res, irq_cookie); 409 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 410 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 411 return (0); 412} 413 414/* 415 * Attach routine - announce which it is, and wire into system 416 */ 417static int 418npx_attach(dev) 419 device_t dev; 420{ 421 int flags; 422 register_t s; 423 424 flags = device_get_flags(dev); 425 426 if (flags) 427 device_printf(dev, "flags 0x%x ", flags); 428 if (npx_irq13) { 429 device_printf(dev, "using IRQ 13 interface\n"); 430 } else { 431 if (npx_ex16) 432 device_printf(dev, "INT 16 interface\n"); 433 else 434 device_printf(dev, "WARNING: no FPU!\n"); 435 } 436 npxinit(__INITIAL_NPXCW__); 437 438 if (npx_cleanstate_ready == 0) { 439 s = intr_disable(); 440 stop_emulating(); 441 fpusave(&npx_cleanstate); 442 start_emulating(); 443 npx_cleanstate_ready = 1; 444 intr_restore(s); 445 } 446#ifdef I586_CPU_XXX 447 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 448 timezero("i586_bzero()", i586_bzero) < 449 timezero("bzero()", bzero) * 4 / 5) { 450 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 451 bcopy_vector = i586_bcopy; 452 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 453 bzero_vector = i586_bzero; 454 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 455 copyin_vector = i586_copyin; 456 copyout_vector = i586_copyout; 457 } 458 } 459#endif 460 461 return (0); /* XXX unused */ 462} 463 464/* 465 * Initialize floating point unit. 466 */ 467void 468npxinit(control) 469 u_short control; 470{ 471 static union savefpu dummy; 472 register_t savecrit; 473 474 if (!npx_exists) 475 return; 476 /* 477 * fninit has the same h/w bugs as fnsave. Use the detoxified 478 * fnsave to throw away any junk in the fpu. npxsave() initializes 479 * the fpu and sets fpcurthread = NULL as important side effects. 480 */ 481 savecrit = intr_disable(); 482 npxsave(&dummy); 483 stop_emulating(); 484#ifdef CPU_ENABLE_SSE 485 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 486 if (cpu_fxsr) 487 fninit(); 488#endif 489 fldcw(&control); 490 start_emulating(); 491 intr_restore(savecrit); 492} 493 494/* 495 * Free coprocessor (if we have it). 496 */ 497void 498npxexit(td) 499 struct thread *td; 500{ 501 register_t savecrit; 502 503 savecrit = intr_disable(); 504 if (curthread == PCPU_GET(fpcurthread)) 505 npxsave(&PCPU_GET(curpcb)->pcb_save); 506 intr_restore(savecrit); 507#ifdef NPX_DEBUG 508 if (npx_exists) { 509 u_int masked_exceptions; 510 511 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 512 /* 513 * Log exceptions that would have trapped with the old 514 * control word (overflow, divide by 0, and invalid operand). 515 */ 516 if (masked_exceptions & 0x0d) 517 log(LOG_ERR, 518 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 519 td->td_proc->p_pid, td->td_proc->p_comm, 520 masked_exceptions); 521 } 522#endif 523} 524 525int 526npxformat() 527{ 528 529 if (!npx_exists) 530 return (_MC_FPFMT_NODEV); 531#ifdef CPU_ENABLE_SSE 532 if (cpu_fxsr) 533 return (_MC_FPFMT_XMM); 534#endif 535 return (_MC_FPFMT_387); 536} 537 538/* 539 * The following mechanism is used to ensure that the FPE_... value 540 * that is passed as a trapcode to the signal handler of the user 541 * process does not have more than one bit set. 542 * 543 * Multiple bits may be set if the user process modifies the control 544 * word while a status word bit is already set. While this is a sign 545 * of bad coding, we have no choise than to narrow them down to one 546 * bit, since we must not send a trapcode that is not exactly one of 547 * the FPE_ macros. 548 * 549 * The mechanism has a static table with 127 entries. Each combination 550 * of the 7 FPU status word exception bits directly translates to a 551 * position in this table, where a single FPE_... value is stored. 552 * This FPE_... value stored there is considered the "most important" 553 * of the exception bits and will be sent as the signal code. The 554 * precedence of the bits is based upon Intel Document "Numerical 555 * Applications", Chapter "Special Computational Situations". 556 * 557 * The macro to choose one of these values does these steps: 1) Throw 558 * away status word bits that cannot be masked. 2) Throw away the bits 559 * currently masked in the control word, assuming the user isn't 560 * interested in them anymore. 3) Reinsert status word bit 7 (stack 561 * fault) if it is set, which cannot be masked but must be presered. 562 * 4) Use the remaining bits to point into the trapcode table. 563 * 564 * The 6 maskable bits in order of their preference, as stated in the 565 * above referenced Intel manual: 566 * 1 Invalid operation (FP_X_INV) 567 * 1a Stack underflow 568 * 1b Stack overflow 569 * 1c Operand of unsupported format 570 * 1d SNaN operand. 571 * 2 QNaN operand (not an exception, irrelavant here) 572 * 3 Any other invalid-operation not mentioned above or zero divide 573 * (FP_X_INV, FP_X_DZ) 574 * 4 Denormal operand (FP_X_DNML) 575 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 576 * 6 Inexact result (FP_X_IMP) 577 */ 578static char fpetable[128] = { 579 0, 580 FPE_FLTINV, /* 1 - INV */ 581 FPE_FLTUND, /* 2 - DNML */ 582 FPE_FLTINV, /* 3 - INV | DNML */ 583 FPE_FLTDIV, /* 4 - DZ */ 584 FPE_FLTINV, /* 5 - INV | DZ */ 585 FPE_FLTDIV, /* 6 - DNML | DZ */ 586 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 587 FPE_FLTOVF, /* 8 - OFL */ 588 FPE_FLTINV, /* 9 - INV | OFL */ 589 FPE_FLTUND, /* A - DNML | OFL */ 590 FPE_FLTINV, /* B - INV | DNML | OFL */ 591 FPE_FLTDIV, /* C - DZ | OFL */ 592 FPE_FLTINV, /* D - INV | DZ | OFL */ 593 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 594 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 595 FPE_FLTUND, /* 10 - UFL */ 596 FPE_FLTINV, /* 11 - INV | UFL */ 597 FPE_FLTUND, /* 12 - DNML | UFL */ 598 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 599 FPE_FLTDIV, /* 14 - DZ | UFL */ 600 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 601 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 602 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 603 FPE_FLTOVF, /* 18 - OFL | UFL */ 604 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 605 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 606 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 607 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 608 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 609 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 610 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 611 FPE_FLTRES, /* 20 - IMP */ 612 FPE_FLTINV, /* 21 - INV | IMP */ 613 FPE_FLTUND, /* 22 - DNML | IMP */ 614 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 615 FPE_FLTDIV, /* 24 - DZ | IMP */ 616 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 617 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 618 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 619 FPE_FLTOVF, /* 28 - OFL | IMP */ 620 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 621 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 622 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 623 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 624 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 625 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 626 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 627 FPE_FLTUND, /* 30 - UFL | IMP */ 628 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 629 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 630 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 631 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 632 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 633 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 634 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 635 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 636 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 637 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 638 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 639 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 640 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 641 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 642 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 643 FPE_FLTSUB, /* 40 - STK */ 644 FPE_FLTSUB, /* 41 - INV | STK */ 645 FPE_FLTUND, /* 42 - DNML | STK */ 646 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 647 FPE_FLTDIV, /* 44 - DZ | STK */ 648 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 649 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 650 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 651 FPE_FLTOVF, /* 48 - OFL | STK */ 652 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 653 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 654 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 655 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 656 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 657 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 658 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 659 FPE_FLTUND, /* 50 - UFL | STK */ 660 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 661 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 662 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 663 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 664 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 665 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 666 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 667 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 668 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 669 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 670 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 671 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 672 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 673 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 674 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 675 FPE_FLTRES, /* 60 - IMP | STK */ 676 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 677 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 678 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 679 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 680 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 681 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 682 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 683 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 684 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 685 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 686 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 687 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 688 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 689 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 690 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 691 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 692 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 693 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 695 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 697 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 699 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 700 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 701 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 702 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 703 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 704 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 705 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 706 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 707}; 708 709/* 710 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 711 * 712 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 713 * depend on longjmp() restoring a usable state. Restoring the state 714 * or examining it might fail if we didn't clear exceptions. 715 * 716 * The error code chosen will be one of the FPE_... macros. It will be 717 * sent as the second argument to old BSD-style signal handlers and as 718 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 719 * 720 * XXX the FP state is not preserved across signal handlers. So signal 721 * handlers cannot afford to do FP unless they preserve the state or 722 * longjmp() out. Both preserving the state and longjmp()ing may be 723 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 724 * solution for signals other than SIGFPE. 725 */ 726int 727npxtrap() 728{ 729 register_t savecrit; 730 u_short control, status; 731 732 if (!npx_exists) { 733 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 734 PCPU_GET(fpcurthread), curthread, npx_exists); 735 panic("npxtrap from nowhere"); 736 } 737 savecrit = intr_disable(); 738 739 /* 740 * Interrupt handling (for another interrupt) may have pushed the 741 * state to memory. Fetch the relevant parts of the state from 742 * wherever they are. 743 */ 744 if (PCPU_GET(fpcurthread) != curthread) { 745 control = GET_FPU_CW(curthread); 746 status = GET_FPU_SW(curthread); 747 } else { 748 fnstcw(&control); 749 fnstsw(&status); 750 } 751 752 if (PCPU_GET(fpcurthread) == curthread) 753 fnclex(); 754 intr_restore(savecrit); 755 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 756} 757 758/* 759 * Implement device not available (DNA) exception 760 * 761 * It would be better to switch FP context here (if curthread != fpcurthread) 762 * and not necessarily for every context switch, but it is too hard to 763 * access foreign pcb's. 764 */ 765 766static int err_count = 0; 767 768int 769npxdna() 770{ 771 struct pcb *pcb; 772 register_t s; 773 u_short control; 774 775 if (!npx_exists) 776 return (0); 777 if (PCPU_GET(fpcurthread) == curthread) { 778 printf("npxdna: fpcurthread == curthread %d times\n", 779 ++err_count); 780 stop_emulating(); 781 return (1); 782 } 783 if (PCPU_GET(fpcurthread) != NULL) { 784 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 785 PCPU_GET(fpcurthread), 786 PCPU_GET(fpcurthread)->td_proc->p_pid, 787 curthread, curthread->td_proc->p_pid); 788 panic("npxdna"); 789 } 790 s = intr_disable(); 791 stop_emulating(); 792 /* 793 * Record new context early in case frstor causes an IRQ13. 794 */ 795 PCPU_SET(fpcurthread, curthread); 796 pcb = PCPU_GET(curpcb); 797 798 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 799 /* 800 * This is the first time this thread has used the FPU or 801 * the PCB doesn't contain a clean FPU state. Explicitly 802 * initialize the FPU and load the default control word. 803 */ 804 fninit(); 805 control = __INITIAL_NPXCW__; 806 fldcw(&control); 807 pcb->pcb_flags |= PCB_NPXINITDONE; 808 } else { 809 /* 810 * The following frstor may cause an IRQ13 when the state 811 * being restored has a pending error. The error will 812 * appear to have been triggered by the current (npx) user 813 * instruction even when that instruction is a no-wait 814 * instruction that should not trigger an error (e.g., 815 * fnclex). On at least one 486 system all of the no-wait 816 * instructions are broken the same as frstor, so our 817 * treatment does not amplify the breakage. On at least 818 * one 386/Cyrix 387 system, fnclex works correctly while 819 * frstor and fnsave are broken, so our treatment breaks 820 * fnclex if it is the first FPU instruction after a context 821 * switch. 822 */ 823 fpurstor(&pcb->pcb_save); 824 } 825 intr_restore(s); 826 827 return (1); 828} 829 830/* 831 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 832 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 833 * no-wait npx instructions. See the Intel application note AP-578 for 834 * details. This doesn't cause any additional complications here. IRQ13's 835 * are inherently asynchronous unless the CPU is frozen to deliver them -- 836 * one that started in userland may be delivered many instructions later, 837 * after the process has entered the kernel. It may even be delivered after 838 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 839 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 840 * it is normally ignored at first because we set fpcurthread to NULL; it is 841 * normally retriggered in npxdna() after return to user mode. 842 * 843 * npxsave() must be called with interrupts disabled, so that it clears 844 * fpcurthread atomically with saving the state. We require callers to do the 845 * disabling, since most callers need to disable interrupts anyway to call 846 * npxsave() atomically with checking fpcurthread. 847 * 848 * A previous version of npxsave() went to great lengths to excecute fnsave 849 * with interrupts enabled in case executing it froze the CPU. This case 850 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 851 * spurious freezes. 852 */ 853void 854npxsave(addr) 855 union savefpu *addr; 856{ 857 858 stop_emulating(); 859 fpusave(addr); 860 861 start_emulating(); 862 PCPU_SET(fpcurthread, NULL); 863} 864 865/* 866 * This should be called with interrupts disabled and only when the owning 867 * FPU thread is non-null. 868 */ 869void 870npxdrop() 871{ 872 struct thread *td; 873 874 /* 875 * Discard pending exceptions in the !cpu_fxsr case so that unmasked 876 * ones don't cause a panic on the next frstor. 877 */ 878#ifdef CPU_ENABLE_SSE 879 if (!cpu_fxsr) 880#endif 881 fnclex(); 882 883 td = PCPU_GET(fpcurthread); 884 PCPU_SET(fpcurthread, NULL); 885 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 886 start_emulating(); 887} 888 889/* 890 * Get the state of the FPU without dropping ownership (if possible). 891 * It returns the FPU ownership status. 892 */ 893int 894npxgetregs(td, addr) 895 struct thread *td; 896 union savefpu *addr; 897{ 898 register_t s; 899 900 if (!npx_exists) 901 return (_MC_FPOWNED_NONE); 902 903 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 904 if (npx_cleanstate_ready) 905 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 906 else 907 bzero(addr, sizeof(*addr)); 908 return (_MC_FPOWNED_NONE); 909 } 910 s = intr_disable(); 911 if (td == PCPU_GET(fpcurthread)) { 912 fpusave(addr); 913#ifdef CPU_ENABLE_SSE 914 if (!cpu_fxsr) 915#endif 916 /* 917 * fnsave initializes the FPU and destroys whatever 918 * context it contains. Make sure the FPU owner 919 * starts with a clean state next time. 920 */ 921 npxdrop(); 922 intr_restore(s); 923 return (_MC_FPOWNED_FPU); 924 } else { 925 intr_restore(s); 926 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 927 return (_MC_FPOWNED_PCB); 928 } 929} 930 931/* 932 * Set the state of the FPU. 933 */ 934void 935npxsetregs(td, addr) 936 struct thread *td; 937 union savefpu *addr; 938{ 939 register_t s; 940 941 if (!npx_exists) 942 return; 943 944 s = intr_disable(); 945 if (td == PCPU_GET(fpcurthread)) { 946#ifdef CPU_ENABLE_SSE 947 if (!cpu_fxsr) 948#endif 949 fnclex(); /* As in npxdrop(). */ 950 fpurstor(addr); 951 intr_restore(s); 952 } else { 953 intr_restore(s); 954 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 955 } 956 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 957} 958 959static void 960fpusave(addr) 961 union savefpu *addr; 962{ 963 964#ifdef CPU_ENABLE_SSE 965 if (cpu_fxsr) 966 fxsave(addr); 967 else 968#endif 969 fnsave(addr); 970} 971 972static void 973fpurstor(addr) 974 union savefpu *addr; 975{ 976 977#ifdef CPU_ENABLE_SSE 978 if (cpu_fxsr) 979 fxrstor(addr); 980 else 981#endif 982 frstor(addr); 983} 984 985#ifdef I586_CPU_XXX 986static long 987timezero(funcname, func) 988 const char *funcname; 989 void (*func)(void *buf, size_t len); 990 991{ 992 void *buf; 993#define BUFSIZE 1048576 994 long usec; 995 struct timeval finish, start; 996 997 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 998 if (buf == NULL) 999 return (BUFSIZE); 1000 microtime(&start); 1001 (*func)(buf, BUFSIZE); 1002 microtime(&finish); 1003 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1004 finish.tv_usec - start.tv_usec; 1005 if (usec <= 0) 1006 usec = 1; 1007 if (bootverbose) 1008 printf("%s bandwidth = %u kBps\n", funcname, 1009 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1010 free(buf, M_TEMP); 1011 return (usec); 1012} 1013#endif /* I586_CPU */ 1014 1015static device_method_t npx_methods[] = { 1016 /* Device interface */ 1017 DEVMETHOD(device_identify, npx_identify), 1018 DEVMETHOD(device_probe, npx_probe), 1019 DEVMETHOD(device_attach, npx_attach), 1020 DEVMETHOD(device_detach, bus_generic_detach), 1021 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1022 DEVMETHOD(device_suspend, bus_generic_suspend), 1023 DEVMETHOD(device_resume, bus_generic_resume), 1024 1025 { 0, 0 } 1026}; 1027 1028static driver_t npx_driver = { 1029 "npx", 1030 npx_methods, 1031 1, /* no softc */ 1032}; 1033 1034static devclass_t npx_devclass; 1035 1036/* 1037 * We prefer to attach to the root nexus so that the usual case (exception 16) 1038 * doesn't describe the processor as being `on isa'. 1039 */ 1040DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1041 1042#ifdef DEV_ISA 1043/* 1044 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1045 */ 1046static struct isa_pnp_id npxisa_ids[] = { 1047 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1048 { 0 } 1049}; 1050 1051static int 1052npxisa_probe(device_t dev) 1053{ 1054 int result; 1055 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1056 device_quiet(dev); 1057 } 1058 return(result); 1059} 1060 1061static int 1062npxisa_attach(device_t dev) 1063{ 1064 return (0); 1065} 1066 1067static device_method_t npxisa_methods[] = { 1068 /* Device interface */ 1069 DEVMETHOD(device_probe, npxisa_probe), 1070 DEVMETHOD(device_attach, npxisa_attach), 1071 DEVMETHOD(device_detach, bus_generic_detach), 1072 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1073 DEVMETHOD(device_suspend, bus_generic_suspend), 1074 DEVMETHOD(device_resume, bus_generic_resume), 1075 1076 { 0, 0 } 1077}; 1078 1079static driver_t npxisa_driver = { 1080 "npxisa", 1081 npxisa_methods, 1082 1, /* no softc */ 1083}; 1084 1085static devclass_t npxisa_devclass; 1086 1087DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1088#ifndef PC98 1089DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1090#endif 1091#endif /* DEV_ISA */ 1092