npx.c revision 128019
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 128019 2004-04-07 20:46:16Z imp $"); 35 36#include "opt_cpu.h" 37#include "opt_debug_npx.h" 38#include "opt_isa.h" 39#include "opt_npx.h" 40 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/bus.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/module.h> 48#include <sys/mutex.h> 49#include <sys/mutex.h> 50#include <sys/proc.h> 51#include <sys/smp.h> 52#include <sys/sysctl.h> 53#include <machine/bus.h> 54#include <sys/rman.h> 55#ifdef NPX_DEBUG 56#include <sys/syslog.h> 57#endif 58#include <sys/signalvar.h> 59#include <sys/user.h> 60 61#include <machine/asmacros.h> 62#include <machine/cputypes.h> 63#include <machine/frame.h> 64#include <machine/md_var.h> 65#include <machine/pcb.h> 66#include <machine/psl.h> 67#include <machine/clock.h> 68#include <machine/resource.h> 69#include <machine/specialreg.h> 70#include <machine/segments.h> 71#include <machine/ucontext.h> 72 73#include <i386/isa/icu.h> 74#ifdef PC98 75#include <pc98/pc98/pc98.h> 76#else 77#include <i386/isa/isa.h> 78#endif 79#include <machine/intr_machdep.h> 80#ifdef DEV_ISA 81#include <isa/isavar.h> 82#endif 83 84#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 85#define CPU_ENABLE_SSE 86#endif 87#if defined(CPU_DISABLE_SSE) 88#undef CPU_ENABLE_SSE 89#endif 90 91/* 92 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 93 */ 94 95/* Configuration flags. */ 96#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 97#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 98#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 99 100#if (defined(__GNUC__) && !defined(lint)) || defined(__INTEL_COMPILER) 101 102#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 103#define fnclex() __asm("fnclex") 104#define fninit() __asm("fninit") 105#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 106#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 107#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 108#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 109#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 110#ifdef CPU_ENABLE_SSE 111#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 112#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 113#endif 114#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 115 : : "n" (CR0_TS) : "ax") 116#define stop_emulating() __asm("clts") 117 118#else /* !((__GNUC__ && !lint ) || __INTEL_COMPILER) */ 119 120void fldcw(caddr_t addr); 121void fnclex(void); 122void fninit(void); 123void fnsave(caddr_t addr); 124void fnstcw(caddr_t addr); 125void fnstsw(caddr_t addr); 126void fp_divide_by_0(void); 127void frstor(caddr_t addr); 128#ifdef CPU_ENABLE_SSE 129void fxsave(caddr_t addr); 130void fxrstor(caddr_t addr); 131#endif 132void start_emulating(void); 133void stop_emulating(void); 134 135#endif /* (__GNUC__ && !lint ) || __INTEL_COMPILER */ 136 137#ifdef CPU_ENABLE_SSE 138#define GET_FPU_CW(thread) \ 139 (cpu_fxsr ? \ 140 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 141 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 142#define GET_FPU_SW(thread) \ 143 (cpu_fxsr ? \ 144 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 145 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 146#else /* CPU_ENABLE_SSE */ 147#define GET_FPU_CW(thread) \ 148 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 149#define GET_FPU_SW(thread) \ 150 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 151#endif /* CPU_ENABLE_SSE */ 152 153typedef u_char bool_t; 154 155static void fpusave(union savefpu *); 156static void fpurstor(union savefpu *); 157static int npx_attach(device_t dev); 158static void npx_identify(driver_t *driver, device_t parent); 159static void npx_intr(void *); 160static int npx_probe(device_t dev); 161#ifdef I586_CPU_XXX 162static long timezero(const char *funcname, 163 void (*func)(void *buf, size_t len)); 164#endif /* I586_CPU */ 165 166int hw_float; /* XXX currently just alias for npx_exists */ 167 168SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 169 CTLFLAG_RD, &hw_float, 0, 170 "Floatingpoint instructions executed in hardware"); 171 172static volatile u_int npx_intrs_while_probing; 173static volatile u_int npx_traps_while_probing; 174 175static union savefpu npx_cleanstate; 176static bool_t npx_cleanstate_ready; 177static bool_t npx_ex16; 178static bool_t npx_exists; 179static bool_t npx_irq13; 180 181alias_for_inthand_t probetrap; 182__asm(" \n\ 183 .text \n\ 184 .p2align 2,0x90 \n\ 185 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 186" __XSTRING(CNAME(probetrap)) ": \n\ 187 ss \n\ 188 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 189 fnclex \n\ 190 iret \n\ 191"); 192 193/* 194 * Identify routine. Create a connection point on our parent for probing. 195 */ 196static void 197npx_identify(driver, parent) 198 driver_t *driver; 199 device_t parent; 200{ 201 device_t child; 202 203 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 204 if (child == NULL) 205 panic("npx_identify"); 206} 207 208/* 209 * Do minimal handling of npx interrupts to convert them to traps. 210 */ 211static void 212npx_intr(dummy) 213 void *dummy; 214{ 215 struct thread *td; 216 217 npx_intrs_while_probing++; 218 219 /* 220 * The BUSY# latch must be cleared in all cases so that the next 221 * unmasked npx exception causes an interrupt. 222 */ 223#ifdef PC98 224 outb(0xf8, 0); 225#else 226 outb(0xf0, 0); 227#endif 228 229 /* 230 * fpcurthread is normally non-null here. In that case, schedule an 231 * AST to finish the exception handling in the correct context 232 * (this interrupt may occur after the thread has entered the 233 * kernel via a syscall or an interrupt). Otherwise, the npx 234 * state of the thread that caused this interrupt must have been 235 * pushed to the thread's pcb, and clearing of the busy latch 236 * above has finished the (essentially null) handling of this 237 * interrupt. Control will eventually return to the instruction 238 * that caused it and it will repeat. We will eventually (usually 239 * soon) win the race to handle the interrupt properly. 240 */ 241 td = PCPU_GET(fpcurthread); 242 if (td != NULL) { 243 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 244 mtx_lock_spin(&sched_lock); 245 td->td_flags |= TDF_ASTPENDING; 246 mtx_unlock_spin(&sched_lock); 247 } 248} 249 250/* 251 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 252 * whether the device exists or not (XXX should be elsewhere). Set flags 253 * to tell npxattach() what to do. Modify device struct if npx doesn't 254 * need to use interrupts. Return 0 if device exists. 255 */ 256static int 257npx_probe(dev) 258 device_t dev; 259{ 260 struct gate_descriptor save_idt_npxtrap; 261 struct resource *ioport_res, *irq_res; 262 void *irq_cookie; 263 int ioport_rid, irq_num, irq_rid; 264 u_short control; 265 u_short status; 266 267 save_idt_npxtrap = idt[IDT_MF]; 268 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 269 GSEL(GCODE_SEL, SEL_KPL)); 270 ioport_rid = 0; 271 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 272 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 273 if (ioport_res == NULL) 274 panic("npx: can't get ports"); 275#ifdef PC98 276 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 277 irq_num = 8; 278#else 279 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 280 irq_num = 13; 281#endif 282 irq_rid = 0; 283 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 284 irq_num, 1, RF_ACTIVE); 285 if (irq_res == NULL) 286 panic("npx: can't get IRQ"); 287 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 288 NULL, &irq_cookie) != 0) 289 panic("npx: can't create intr"); 290 291 /* 292 * Partially reset the coprocessor, if any. Some BIOS's don't reset 293 * it after a warm boot. 294 */ 295#ifdef PC98 296 outb(0xf8,0); 297#else 298 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 299 outb(0xf0, 0); /* clear BUSY# latch */ 300#endif 301 /* 302 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 303 * instructions. We must set the CR0_MP bit and use the CR0_TS 304 * bit to control the trap, because setting the CR0_EM bit does 305 * not cause WAIT instructions to trap. It's important to trap 306 * WAIT instructions - otherwise the "wait" variants of no-wait 307 * control instructions would degenerate to the "no-wait" variants 308 * after FP context switches but work correctly otherwise. It's 309 * particularly important to trap WAITs when there is no NPX - 310 * otherwise the "wait" variants would always degenerate. 311 * 312 * Try setting CR0_NE to get correct error reporting on 486DX's. 313 * Setting it should fail or do nothing on lesser processors. 314 */ 315 load_cr0(rcr0() | CR0_MP | CR0_NE); 316 /* 317 * But don't trap while we're probing. 318 */ 319 stop_emulating(); 320 /* 321 * Finish resetting the coprocessor, if any. If there is an error 322 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 323 * it OK. Bogus halts have never been observed, but we enabled 324 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 325 */ 326 fninit(); 327 328 device_set_desc(dev, "math processor"); 329 330 /* 331 * Don't use fwait here because it might hang. 332 * Don't use fnop here because it usually hangs if there is no FPU. 333 */ 334 DELAY(1000); /* wait for any IRQ13 */ 335#ifdef DIAGNOSTIC 336 if (npx_intrs_while_probing != 0) 337 printf("fninit caused %u bogus npx interrupt(s)\n", 338 npx_intrs_while_probing); 339 if (npx_traps_while_probing != 0) 340 printf("fninit caused %u bogus npx trap(s)\n", 341 npx_traps_while_probing); 342#endif 343 /* 344 * Check for a status of mostly zero. 345 */ 346 status = 0x5a5a; 347 fnstsw(&status); 348 if ((status & 0xb8ff) == 0) { 349 /* 350 * Good, now check for a proper control word. 351 */ 352 control = 0x5a5a; 353 fnstcw(&control); 354 if ((control & 0x1f3f) == 0x033f) { 355 hw_float = npx_exists = 1; 356 /* 357 * We have an npx, now divide by 0 to see if exception 358 * 16 works. 359 */ 360 control &= ~(1 << 2); /* enable divide by 0 trap */ 361 fldcw(&control); 362#ifdef FPU_ERROR_BROKEN 363 /* 364 * FPU error signal doesn't work on some CPU 365 * accelerator board. 366 */ 367 npx_ex16 = 1; 368 return (0); 369#endif 370 npx_traps_while_probing = npx_intrs_while_probing = 0; 371 fp_divide_by_0(); 372 if (npx_traps_while_probing != 0) { 373 /* 374 * Good, exception 16 works. 375 */ 376 npx_ex16 = 1; 377 goto no_irq13; 378 } 379 if (npx_intrs_while_probing != 0) { 380 /* 381 * Bad, we are stuck with IRQ13. 382 */ 383 npx_irq13 = 1; 384 idt[IDT_MF] = save_idt_npxtrap; 385#ifdef SMP 386 if (mp_ncpus > 1) 387 panic("npx0 cannot use IRQ 13 on an SMP system"); 388#endif 389 return (0); 390 } 391 /* 392 * Worse, even IRQ13 is broken. Use emulator. 393 */ 394 } 395 } 396 /* 397 * Probe failed, but we want to get to npxattach to initialize the 398 * emulator and say that it has been installed. XXX handle devices 399 * that aren't really devices better. 400 */ 401#ifdef SMP 402 if (mp_ncpus > 1) 403 panic("npx0 cannot be emulated on an SMP system"); 404#endif 405 /* FALLTHROUGH */ 406no_irq13: 407 idt[IDT_MF] = save_idt_npxtrap; 408 bus_teardown_intr(dev, irq_res, irq_cookie); 409 410 /* 411 * XXX hack around brokenness of bus_teardown_intr(). If we left the 412 * irq active then we would get it instead of exception 16. 413 */ 414 { 415 struct intsrc *isrc; 416 417 isrc = intr_lookup_source(irq_num); 418 isrc->is_pic->pic_disable_source(isrc); 419 } 420 421 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 422 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 423 return (0); 424} 425 426/* 427 * Attach routine - announce which it is, and wire into system 428 */ 429static int 430npx_attach(dev) 431 device_t dev; 432{ 433 int flags; 434 register_t s; 435 436 if (resource_int_value("npx", 0, "flags", &flags) != 0) 437 flags = 0; 438 439 if (flags) 440 device_printf(dev, "flags 0x%x ", flags); 441 if (npx_irq13) { 442 device_printf(dev, "using IRQ 13 interface\n"); 443 } else { 444 if (npx_ex16) 445 device_printf(dev, "INT 16 interface\n"); 446 else 447 device_printf(dev, "WARNING: no FPU!\n"); 448 } 449 npxinit(__INITIAL_NPXCW__); 450 451 if (npx_cleanstate_ready == 0) { 452 s = intr_disable(); 453 stop_emulating(); 454 fpusave(&npx_cleanstate); 455 start_emulating(); 456 npx_cleanstate_ready = 1; 457 intr_restore(s); 458 } 459#ifdef I586_CPU_XXX 460 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 461 timezero("i586_bzero()", i586_bzero) < 462 timezero("bzero()", bzero) * 4 / 5) { 463 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 464 bcopy_vector = i586_bcopy; 465 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 466 bzero_vector = i586_bzero; 467 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 468 copyin_vector = i586_copyin; 469 copyout_vector = i586_copyout; 470 } 471 } 472#endif 473 474 return (0); /* XXX unused */ 475} 476 477/* 478 * Initialize floating point unit. 479 */ 480void 481npxinit(control) 482 u_short control; 483{ 484 static union savefpu dummy; 485 register_t savecrit; 486 487 if (!npx_exists) 488 return; 489 /* 490 * fninit has the same h/w bugs as fnsave. Use the detoxified 491 * fnsave to throw away any junk in the fpu. npxsave() initializes 492 * the fpu and sets fpcurthread = NULL as important side effects. 493 */ 494 savecrit = intr_disable(); 495 npxsave(&dummy); 496 stop_emulating(); 497#ifdef CPU_ENABLE_SSE 498 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 499 if (cpu_fxsr) 500 fninit(); 501#endif 502 fldcw(&control); 503 start_emulating(); 504 intr_restore(savecrit); 505} 506 507/* 508 * Free coprocessor (if we have it). 509 */ 510void 511npxexit(td) 512 struct thread *td; 513{ 514 register_t savecrit; 515 516 savecrit = intr_disable(); 517 if (curthread == PCPU_GET(fpcurthread)) 518 npxsave(&PCPU_GET(curpcb)->pcb_save); 519 intr_restore(savecrit); 520#ifdef NPX_DEBUG 521 if (npx_exists) { 522 u_int masked_exceptions; 523 524 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 525 /* 526 * Log exceptions that would have trapped with the old 527 * control word (overflow, divide by 0, and invalid operand). 528 */ 529 if (masked_exceptions & 0x0d) 530 log(LOG_ERR, 531 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 532 td->td_proc->p_pid, td->td_proc->p_comm, 533 masked_exceptions); 534 } 535#endif 536} 537 538int 539npxformat() 540{ 541 542 if (!npx_exists) 543 return (_MC_FPFMT_NODEV); 544#ifdef CPU_ENABLE_SSE 545 if (cpu_fxsr) 546 return (_MC_FPFMT_XMM); 547#endif 548 return (_MC_FPFMT_387); 549} 550 551/* 552 * The following mechanism is used to ensure that the FPE_... value 553 * that is passed as a trapcode to the signal handler of the user 554 * process does not have more than one bit set. 555 * 556 * Multiple bits may be set if the user process modifies the control 557 * word while a status word bit is already set. While this is a sign 558 * of bad coding, we have no choise than to narrow them down to one 559 * bit, since we must not send a trapcode that is not exactly one of 560 * the FPE_ macros. 561 * 562 * The mechanism has a static table with 127 entries. Each combination 563 * of the 7 FPU status word exception bits directly translates to a 564 * position in this table, where a single FPE_... value is stored. 565 * This FPE_... value stored there is considered the "most important" 566 * of the exception bits and will be sent as the signal code. The 567 * precedence of the bits is based upon Intel Document "Numerical 568 * Applications", Chapter "Special Computational Situations". 569 * 570 * The macro to choose one of these values does these steps: 1) Throw 571 * away status word bits that cannot be masked. 2) Throw away the bits 572 * currently masked in the control word, assuming the user isn't 573 * interested in them anymore. 3) Reinsert status word bit 7 (stack 574 * fault) if it is set, which cannot be masked but must be presered. 575 * 4) Use the remaining bits to point into the trapcode table. 576 * 577 * The 6 maskable bits in order of their preference, as stated in the 578 * above referenced Intel manual: 579 * 1 Invalid operation (FP_X_INV) 580 * 1a Stack underflow 581 * 1b Stack overflow 582 * 1c Operand of unsupported format 583 * 1d SNaN operand. 584 * 2 QNaN operand (not an exception, irrelavant here) 585 * 3 Any other invalid-operation not mentioned above or zero divide 586 * (FP_X_INV, FP_X_DZ) 587 * 4 Denormal operand (FP_X_DNML) 588 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 589 * 6 Inexact result (FP_X_IMP) 590 */ 591static char fpetable[128] = { 592 0, 593 FPE_FLTINV, /* 1 - INV */ 594 FPE_FLTUND, /* 2 - DNML */ 595 FPE_FLTINV, /* 3 - INV | DNML */ 596 FPE_FLTDIV, /* 4 - DZ */ 597 FPE_FLTINV, /* 5 - INV | DZ */ 598 FPE_FLTDIV, /* 6 - DNML | DZ */ 599 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 600 FPE_FLTOVF, /* 8 - OFL */ 601 FPE_FLTINV, /* 9 - INV | OFL */ 602 FPE_FLTUND, /* A - DNML | OFL */ 603 FPE_FLTINV, /* B - INV | DNML | OFL */ 604 FPE_FLTDIV, /* C - DZ | OFL */ 605 FPE_FLTINV, /* D - INV | DZ | OFL */ 606 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 607 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 608 FPE_FLTUND, /* 10 - UFL */ 609 FPE_FLTINV, /* 11 - INV | UFL */ 610 FPE_FLTUND, /* 12 - DNML | UFL */ 611 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 612 FPE_FLTDIV, /* 14 - DZ | UFL */ 613 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 614 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 615 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 616 FPE_FLTOVF, /* 18 - OFL | UFL */ 617 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 618 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 619 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 620 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 621 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 622 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 623 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 624 FPE_FLTRES, /* 20 - IMP */ 625 FPE_FLTINV, /* 21 - INV | IMP */ 626 FPE_FLTUND, /* 22 - DNML | IMP */ 627 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 628 FPE_FLTDIV, /* 24 - DZ | IMP */ 629 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 630 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 631 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 632 FPE_FLTOVF, /* 28 - OFL | IMP */ 633 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 634 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 635 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 636 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 637 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 638 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 639 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 640 FPE_FLTUND, /* 30 - UFL | IMP */ 641 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 642 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 643 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 644 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 645 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 646 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 647 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 648 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 649 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 650 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 651 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 652 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 653 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 654 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 655 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 656 FPE_FLTSUB, /* 40 - STK */ 657 FPE_FLTSUB, /* 41 - INV | STK */ 658 FPE_FLTUND, /* 42 - DNML | STK */ 659 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 660 FPE_FLTDIV, /* 44 - DZ | STK */ 661 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 662 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 663 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 664 FPE_FLTOVF, /* 48 - OFL | STK */ 665 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 666 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 667 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 668 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 669 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 670 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 671 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 672 FPE_FLTUND, /* 50 - UFL | STK */ 673 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 674 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 675 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 676 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 677 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 678 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 679 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 680 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 681 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 682 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 683 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 684 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 685 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 686 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 687 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 688 FPE_FLTRES, /* 60 - IMP | STK */ 689 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 690 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 691 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 692 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 693 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 694 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 695 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 696 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 697 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 698 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 699 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 700 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 701 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 702 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 703 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 704 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 705 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 706 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 707 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 708 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 709 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 710 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 711 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 712 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 713 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 714 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 715 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 716 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 717 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 718 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 719 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 720}; 721 722/* 723 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 724 * 725 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 726 * depend on longjmp() restoring a usable state. Restoring the state 727 * or examining it might fail if we didn't clear exceptions. 728 * 729 * The error code chosen will be one of the FPE_... macros. It will be 730 * sent as the second argument to old BSD-style signal handlers and as 731 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 732 * 733 * XXX the FP state is not preserved across signal handlers. So signal 734 * handlers cannot afford to do FP unless they preserve the state or 735 * longjmp() out. Both preserving the state and longjmp()ing may be 736 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 737 * solution for signals other than SIGFPE. 738 */ 739int 740npxtrap() 741{ 742 register_t savecrit; 743 u_short control, status; 744 745 if (!npx_exists) { 746 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 747 PCPU_GET(fpcurthread), curthread, npx_exists); 748 panic("npxtrap from nowhere"); 749 } 750 savecrit = intr_disable(); 751 752 /* 753 * Interrupt handling (for another interrupt) may have pushed the 754 * state to memory. Fetch the relevant parts of the state from 755 * wherever they are. 756 */ 757 if (PCPU_GET(fpcurthread) != curthread) { 758 control = GET_FPU_CW(curthread); 759 status = GET_FPU_SW(curthread); 760 } else { 761 fnstcw(&control); 762 fnstsw(&status); 763 } 764 765 if (PCPU_GET(fpcurthread) == curthread) 766 fnclex(); 767 intr_restore(savecrit); 768 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 769} 770 771/* 772 * Implement device not available (DNA) exception 773 * 774 * It would be better to switch FP context here (if curthread != fpcurthread) 775 * and not necessarily for every context switch, but it is too hard to 776 * access foreign pcb's. 777 */ 778 779static int err_count = 0; 780 781int 782npxdna() 783{ 784 struct pcb *pcb; 785 register_t s; 786 u_short control; 787 788 if (!npx_exists) 789 return (0); 790 if (PCPU_GET(fpcurthread) == curthread) { 791 printf("npxdna: fpcurthread == curthread %d times\n", 792 ++err_count); 793 stop_emulating(); 794 return (1); 795 } 796 if (PCPU_GET(fpcurthread) != NULL) { 797 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 798 PCPU_GET(fpcurthread), 799 PCPU_GET(fpcurthread)->td_proc->p_pid, 800 curthread, curthread->td_proc->p_pid); 801 panic("npxdna"); 802 } 803 s = intr_disable(); 804 stop_emulating(); 805 /* 806 * Record new context early in case frstor causes an IRQ13. 807 */ 808 PCPU_SET(fpcurthread, curthread); 809 pcb = PCPU_GET(curpcb); 810 811 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 812 /* 813 * This is the first time this thread has used the FPU or 814 * the PCB doesn't contain a clean FPU state. Explicitly 815 * initialize the FPU and load the default control word. 816 */ 817 fninit(); 818 control = __INITIAL_NPXCW__; 819 fldcw(&control); 820 pcb->pcb_flags |= PCB_NPXINITDONE; 821 } else { 822 /* 823 * The following frstor may cause an IRQ13 when the state 824 * being restored has a pending error. The error will 825 * appear to have been triggered by the current (npx) user 826 * instruction even when that instruction is a no-wait 827 * instruction that should not trigger an error (e.g., 828 * fnclex). On at least one 486 system all of the no-wait 829 * instructions are broken the same as frstor, so our 830 * treatment does not amplify the breakage. On at least 831 * one 386/Cyrix 387 system, fnclex works correctly while 832 * frstor and fnsave are broken, so our treatment breaks 833 * fnclex if it is the first FPU instruction after a context 834 * switch. 835 */ 836 fpurstor(&pcb->pcb_save); 837 } 838 intr_restore(s); 839 840 return (1); 841} 842 843/* 844 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 845 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 846 * no-wait npx instructions. See the Intel application note AP-578 for 847 * details. This doesn't cause any additional complications here. IRQ13's 848 * are inherently asynchronous unless the CPU is frozen to deliver them -- 849 * one that started in userland may be delivered many instructions later, 850 * after the process has entered the kernel. It may even be delivered after 851 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 852 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 853 * it is normally ignored at first because we set fpcurthread to NULL; it is 854 * normally retriggered in npxdna() after return to user mode. 855 * 856 * npxsave() must be called with interrupts disabled, so that it clears 857 * fpcurthread atomically with saving the state. We require callers to do the 858 * disabling, since most callers need to disable interrupts anyway to call 859 * npxsave() atomically with checking fpcurthread. 860 * 861 * A previous version of npxsave() went to great lengths to excecute fnsave 862 * with interrupts enabled in case executing it froze the CPU. This case 863 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 864 * spurious freezes. 865 */ 866void 867npxsave(addr) 868 union savefpu *addr; 869{ 870 871 stop_emulating(); 872 fpusave(addr); 873 874 start_emulating(); 875 PCPU_SET(fpcurthread, NULL); 876} 877 878/* 879 * This should be called with interrupts disabled and only when the owning 880 * FPU thread is non-null. 881 */ 882void 883npxdrop() 884{ 885 struct thread *td; 886 887 td = PCPU_GET(fpcurthread); 888 PCPU_SET(fpcurthread, NULL); 889 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 890 start_emulating(); 891} 892 893/* 894 * Get the state of the FPU without dropping ownership (if possible). 895 * It returns the FPU ownership status. 896 */ 897int 898npxgetregs(td, addr) 899 struct thread *td; 900 union savefpu *addr; 901{ 902 register_t s; 903 904 if (!npx_exists) 905 return (_MC_FPOWNED_NONE); 906 907 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 908 if (npx_cleanstate_ready) 909 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 910 else 911 bzero(addr, sizeof(*addr)); 912 return (_MC_FPOWNED_NONE); 913 } 914 s = intr_disable(); 915 if (td == PCPU_GET(fpcurthread)) { 916 fpusave(addr); 917#ifdef CPU_ENABLE_SSE 918 if (!cpu_fxsr) 919#endif 920 /* 921 * fnsave initializes the FPU and destroys whatever 922 * context it contains. Make sure the FPU owner 923 * starts with a clean state next time. 924 */ 925 npxdrop(); 926 intr_restore(s); 927 return (_MC_FPOWNED_FPU); 928 } else { 929 intr_restore(s); 930 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 931 return (_MC_FPOWNED_PCB); 932 } 933} 934 935/* 936 * Set the state of the FPU. 937 */ 938void 939npxsetregs(td, addr) 940 struct thread *td; 941 union savefpu *addr; 942{ 943 register_t s; 944 945 if (!npx_exists) 946 return; 947 948 s = intr_disable(); 949 if (td == PCPU_GET(fpcurthread)) { 950 fpurstor(addr); 951 intr_restore(s); 952 } else { 953 intr_restore(s); 954 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 955 } 956 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 957} 958 959static void 960fpusave(addr) 961 union savefpu *addr; 962{ 963 964#ifdef CPU_ENABLE_SSE 965 if (cpu_fxsr) 966 fxsave(addr); 967 else 968#endif 969 fnsave(addr); 970} 971 972static void 973fpurstor(addr) 974 union savefpu *addr; 975{ 976 977#ifdef CPU_ENABLE_SSE 978 if (cpu_fxsr) 979 fxrstor(addr); 980 else 981#endif 982 frstor(addr); 983} 984 985#ifdef I586_CPU_XXX 986static long 987timezero(funcname, func) 988 const char *funcname; 989 void (*func)(void *buf, size_t len); 990 991{ 992 void *buf; 993#define BUFSIZE 1048576 994 long usec; 995 struct timeval finish, start; 996 997 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 998 if (buf == NULL) 999 return (BUFSIZE); 1000 microtime(&start); 1001 (*func)(buf, BUFSIZE); 1002 microtime(&finish); 1003 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1004 finish.tv_usec - start.tv_usec; 1005 if (usec <= 0) 1006 usec = 1; 1007 if (bootverbose) 1008 printf("%s bandwidth = %u kBps\n", funcname, 1009 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1010 free(buf, M_TEMP); 1011 return (usec); 1012} 1013#endif /* I586_CPU */ 1014 1015static device_method_t npx_methods[] = { 1016 /* Device interface */ 1017 DEVMETHOD(device_identify, npx_identify), 1018 DEVMETHOD(device_probe, npx_probe), 1019 DEVMETHOD(device_attach, npx_attach), 1020 DEVMETHOD(device_detach, bus_generic_detach), 1021 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1022 DEVMETHOD(device_suspend, bus_generic_suspend), 1023 DEVMETHOD(device_resume, bus_generic_resume), 1024 1025 { 0, 0 } 1026}; 1027 1028static driver_t npx_driver = { 1029 "npx", 1030 npx_methods, 1031 1, /* no softc */ 1032}; 1033 1034static devclass_t npx_devclass; 1035 1036/* 1037 * We prefer to attach to the root nexus so that the usual case (exception 16) 1038 * doesn't describe the processor as being `on isa'. 1039 */ 1040DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1041 1042#ifdef DEV_ISA 1043/* 1044 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1045 */ 1046static struct isa_pnp_id npxisa_ids[] = { 1047 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1048 { 0 } 1049}; 1050 1051static int 1052npxisa_probe(device_t dev) 1053{ 1054 int result; 1055 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1056 device_quiet(dev); 1057 } 1058 return(result); 1059} 1060 1061static int 1062npxisa_attach(device_t dev) 1063{ 1064 return (0); 1065} 1066 1067static device_method_t npxisa_methods[] = { 1068 /* Device interface */ 1069 DEVMETHOD(device_probe, npxisa_probe), 1070 DEVMETHOD(device_attach, npxisa_attach), 1071 DEVMETHOD(device_detach, bus_generic_detach), 1072 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1073 DEVMETHOD(device_suspend, bus_generic_suspend), 1074 DEVMETHOD(device_resume, bus_generic_resume), 1075 1076 { 0, 0 } 1077}; 1078 1079static driver_t npxisa_driver = { 1080 "npxisa", 1081 npxisa_methods, 1082 1, /* no softc */ 1083}; 1084 1085static devclass_t npxisa_devclass; 1086 1087DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1088#ifndef PC98 1089DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1090#endif 1091#endif /* DEV_ISA */ 1092