npx.c revision 125782
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 125782 2004-02-13 18:04:51Z bde $"); 39 40#include "opt_cpu.h" 41#include "opt_debug_npx.h" 42#include "opt_isa.h" 43#include "opt_npx.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/mutex.h> 54#include <sys/proc.h> 55#include <sys/smp.h> 56#include <sys/sysctl.h> 57#include <machine/bus.h> 58#include <sys/rman.h> 59#ifdef NPX_DEBUG 60#include <sys/syslog.h> 61#endif 62#include <sys/signalvar.h> 63#include <sys/user.h> 64 65#include <machine/asmacros.h> 66#include <machine/cputypes.h> 67#include <machine/frame.h> 68#include <machine/md_var.h> 69#include <machine/pcb.h> 70#include <machine/psl.h> 71#include <machine/clock.h> 72#include <machine/resource.h> 73#include <machine/specialreg.h> 74#include <machine/segments.h> 75#include <machine/ucontext.h> 76 77#include <i386/isa/icu.h> 78#ifdef PC98 79#include <pc98/pc98/pc98.h> 80#else 81#include <i386/isa/isa.h> 82#endif 83#include <machine/intr_machdep.h> 84#ifdef DEV_ISA 85#include <isa/isavar.h> 86#endif 87 88#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 89#define CPU_ENABLE_SSE 90#endif 91#if defined(CPU_DISABLE_SSE) 92#undef CPU_ENABLE_SSE 93#endif 94 95/* 96 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 97 */ 98 99/* Configuration flags. */ 100#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 101#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 102#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 103 104#if defined(__GNUC__) && !defined(lint) 105 106#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 107#define fnclex() __asm("fnclex") 108#define fninit() __asm("fninit") 109#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 110#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 111#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 112#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 113#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 114#ifdef CPU_ENABLE_SSE 115#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 116#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 117#endif 118#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 119 : : "n" (CR0_TS) : "ax") 120#define stop_emulating() __asm("clts") 121 122#else /* not __GNUC__ */ 123 124void fldcw(caddr_t addr); 125void fnclex(void); 126void fninit(void); 127void fnsave(caddr_t addr); 128void fnstcw(caddr_t addr); 129void fnstsw(caddr_t addr); 130void fp_divide_by_0(void); 131void frstor(caddr_t addr); 132#ifdef CPU_ENABLE_SSE 133void fxsave(caddr_t addr); 134void fxrstor(caddr_t addr); 135#endif 136void start_emulating(void); 137void stop_emulating(void); 138 139#endif /* __GNUC__ */ 140 141#ifdef CPU_ENABLE_SSE 142#define GET_FPU_CW(thread) \ 143 (cpu_fxsr ? \ 144 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 145 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 146#define GET_FPU_SW(thread) \ 147 (cpu_fxsr ? \ 148 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 149 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 150#else /* CPU_ENABLE_SSE */ 151#define GET_FPU_CW(thread) \ 152 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 153#define GET_FPU_SW(thread) \ 154 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 155#endif /* CPU_ENABLE_SSE */ 156 157typedef u_char bool_t; 158 159static void fpusave(union savefpu *); 160static void fpurstor(union savefpu *); 161static int npx_attach(device_t dev); 162static void npx_identify(driver_t *driver, device_t parent); 163static void npx_intr(void *); 164static int npx_probe(device_t dev); 165#ifdef I586_CPU_XXX 166static long timezero(const char *funcname, 167 void (*func)(void *buf, size_t len)); 168#endif /* I586_CPU */ 169 170int hw_float; /* XXX currently just alias for npx_exists */ 171 172SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 173 CTLFLAG_RD, &hw_float, 0, 174 "Floatingpoint instructions executed in hardware"); 175 176static volatile u_int npx_intrs_while_probing; 177static volatile u_int npx_traps_while_probing; 178 179static union savefpu npx_cleanstate; 180static bool_t npx_cleanstate_ready; 181static bool_t npx_ex16; 182static bool_t npx_exists; 183static bool_t npx_irq13; 184 185alias_for_inthand_t probetrap; 186__asm(" \n\ 187 .text \n\ 188 .p2align 2,0x90 \n\ 189 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 190" __XSTRING(CNAME(probetrap)) ": \n\ 191 ss \n\ 192 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 193 fnclex \n\ 194 iret \n\ 195"); 196 197/* 198 * Identify routine. Create a connection point on our parent for probing. 199 */ 200static void 201npx_identify(driver, parent) 202 driver_t *driver; 203 device_t parent; 204{ 205 device_t child; 206 207 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 208 if (child == NULL) 209 panic("npx_identify"); 210} 211 212/* 213 * Do minimal handling of npx interrupts to convert them to traps. 214 */ 215static void 216npx_intr(dummy) 217 void *dummy; 218{ 219 struct thread *td; 220 221 npx_intrs_while_probing++; 222 223 /* 224 * The BUSY# latch must be cleared in all cases so that the next 225 * unmasked npx exception causes an interrupt. 226 */ 227#ifdef PC98 228 outb(0xf8, 0); 229#else 230 outb(0xf0, 0); 231#endif 232 233 /* 234 * fpcurthread is normally non-null here. In that case, schedule an 235 * AST to finish the exception handling in the correct context 236 * (this interrupt may occur after the thread has entered the 237 * kernel via a syscall or an interrupt). Otherwise, the npx 238 * state of the thread that caused this interrupt must have been 239 * pushed to the thread's pcb, and clearing of the busy latch 240 * above has finished the (essentially null) handling of this 241 * interrupt. Control will eventually return to the instruction 242 * that caused it and it will repeat. We will eventually (usually 243 * soon) win the race to handle the interrupt properly. 244 */ 245 td = PCPU_GET(fpcurthread); 246 if (td != NULL) { 247 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 248 mtx_lock_spin(&sched_lock); 249 td->td_flags |= TDF_ASTPENDING; 250 mtx_unlock_spin(&sched_lock); 251 } 252} 253 254/* 255 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 256 * whether the device exists or not (XXX should be elsewhere). Set flags 257 * to tell npxattach() what to do. Modify device struct if npx doesn't 258 * need to use interrupts. Return 0 if device exists. 259 */ 260static int 261npx_probe(dev) 262 device_t dev; 263{ 264 struct gate_descriptor save_idt_npxtrap; 265 struct resource *ioport_res, *irq_res; 266 void *irq_cookie; 267 int ioport_rid, irq_num, irq_rid; 268 u_short control; 269 u_short status; 270 271 save_idt_npxtrap = idt[IDT_MF]; 272 setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL, 273 GSEL(GCODE_SEL, SEL_KPL)); 274 ioport_rid = 0; 275 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 276 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 277 if (ioport_res == NULL) 278 panic("npx: can't get ports"); 279#ifdef PC98 280 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 281 irq_num = 8; 282#else 283 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 284 irq_num = 13; 285#endif 286 irq_rid = 0; 287 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 288 irq_num, 1, RF_ACTIVE); 289 if (irq_res == NULL) 290 panic("npx: can't get IRQ"); 291 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 292 NULL, &irq_cookie) != 0) 293 panic("npx: can't create intr"); 294 295 /* 296 * Partially reset the coprocessor, if any. Some BIOS's don't reset 297 * it after a warm boot. 298 */ 299#ifdef PC98 300 outb(0xf8,0); 301#else 302 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 303 outb(0xf0, 0); /* clear BUSY# latch */ 304#endif 305 /* 306 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 307 * instructions. We must set the CR0_MP bit and use the CR0_TS 308 * bit to control the trap, because setting the CR0_EM bit does 309 * not cause WAIT instructions to trap. It's important to trap 310 * WAIT instructions - otherwise the "wait" variants of no-wait 311 * control instructions would degenerate to the "no-wait" variants 312 * after FP context switches but work correctly otherwise. It's 313 * particularly important to trap WAITs when there is no NPX - 314 * otherwise the "wait" variants would always degenerate. 315 * 316 * Try setting CR0_NE to get correct error reporting on 486DX's. 317 * Setting it should fail or do nothing on lesser processors. 318 */ 319 load_cr0(rcr0() | CR0_MP | CR0_NE); 320 /* 321 * But don't trap while we're probing. 322 */ 323 stop_emulating(); 324 /* 325 * Finish resetting the coprocessor, if any. If there is an error 326 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 327 * it OK. Bogus halts have never been observed, but we enabled 328 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 329 */ 330 fninit(); 331 332 device_set_desc(dev, "math processor"); 333 334 /* 335 * Don't use fwait here because it might hang. 336 * Don't use fnop here because it usually hangs if there is no FPU. 337 */ 338 DELAY(1000); /* wait for any IRQ13 */ 339#ifdef DIAGNOSTIC 340 if (npx_intrs_while_probing != 0) 341 printf("fninit caused %u bogus npx interrupt(s)\n", 342 npx_intrs_while_probing); 343 if (npx_traps_while_probing != 0) 344 printf("fninit caused %u bogus npx trap(s)\n", 345 npx_traps_while_probing); 346#endif 347 /* 348 * Check for a status of mostly zero. 349 */ 350 status = 0x5a5a; 351 fnstsw(&status); 352 if ((status & 0xb8ff) == 0) { 353 /* 354 * Good, now check for a proper control word. 355 */ 356 control = 0x5a5a; 357 fnstcw(&control); 358 if ((control & 0x1f3f) == 0x033f) { 359 hw_float = npx_exists = 1; 360 /* 361 * We have an npx, now divide by 0 to see if exception 362 * 16 works. 363 */ 364 control &= ~(1 << 2); /* enable divide by 0 trap */ 365 fldcw(&control); 366#ifdef FPU_ERROR_BROKEN 367 /* 368 * FPU error signal doesn't work on some CPU 369 * accelerator board. 370 */ 371 npx_ex16 = 1; 372 return (0); 373#endif 374 npx_traps_while_probing = npx_intrs_while_probing = 0; 375 fp_divide_by_0(); 376 if (npx_traps_while_probing != 0) { 377 /* 378 * Good, exception 16 works. 379 */ 380 npx_ex16 = 1; 381 goto no_irq13; 382 } 383 if (npx_intrs_while_probing != 0) { 384 /* 385 * Bad, we are stuck with IRQ13. 386 */ 387 npx_irq13 = 1; 388 idt[IDT_MF] = save_idt_npxtrap; 389#ifdef SMP 390 if (mp_ncpus > 1) 391 panic("npx0 cannot use IRQ 13 on an SMP system"); 392#endif 393 return (0); 394 } 395 /* 396 * Worse, even IRQ13 is broken. Use emulator. 397 */ 398 } 399 } 400 /* 401 * Probe failed, but we want to get to npxattach to initialize the 402 * emulator and say that it has been installed. XXX handle devices 403 * that aren't really devices better. 404 */ 405#ifdef SMP 406 if (mp_ncpus > 1) 407 panic("npx0 cannot be emulated on an SMP system"); 408#endif 409 /* FALLTHROUGH */ 410no_irq13: 411 idt[IDT_MF] = save_idt_npxtrap; 412 bus_teardown_intr(dev, irq_res, irq_cookie); 413 414 /* 415 * XXX hack around brokenness of bus_teardown_intr(). If we left the 416 * irq active then we would get it instead of exception 16. 417 */ 418 { 419 struct intsrc *isrc; 420 421 isrc = intr_lookup_source(irq_num); 422 isrc->is_pic->pic_disable_source(isrc); 423 } 424 425 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 426 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 427 return (0); 428} 429 430/* 431 * Attach routine - announce which it is, and wire into system 432 */ 433static int 434npx_attach(dev) 435 device_t dev; 436{ 437 int flags; 438 register_t s; 439 440 if (resource_int_value("npx", 0, "flags", &flags) != 0) 441 flags = 0; 442 443 if (flags) 444 device_printf(dev, "flags 0x%x ", flags); 445 if (npx_irq13) { 446 device_printf(dev, "using IRQ 13 interface\n"); 447 } else { 448 if (npx_ex16) 449 device_printf(dev, "INT 16 interface\n"); 450 else 451 device_printf(dev, "WARNING: no FPU!\n"); 452 } 453 npxinit(__INITIAL_NPXCW__); 454 455 if (npx_cleanstate_ready == 0) { 456 s = intr_disable(); 457 stop_emulating(); 458 fpusave(&npx_cleanstate); 459 start_emulating(); 460 npx_cleanstate_ready = 1; 461 intr_restore(s); 462 } 463#ifdef I586_CPU_XXX 464 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 465 timezero("i586_bzero()", i586_bzero) < 466 timezero("bzero()", bzero) * 4 / 5) { 467 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 468 bcopy_vector = i586_bcopy; 469 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 470 bzero_vector = i586_bzero; 471 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 472 copyin_vector = i586_copyin; 473 copyout_vector = i586_copyout; 474 } 475 } 476#endif 477 478 return (0); /* XXX unused */ 479} 480 481/* 482 * Initialize floating point unit. 483 */ 484void 485npxinit(control) 486 u_short control; 487{ 488 static union savefpu dummy; 489 register_t savecrit; 490 491 if (!npx_exists) 492 return; 493 /* 494 * fninit has the same h/w bugs as fnsave. Use the detoxified 495 * fnsave to throw away any junk in the fpu. npxsave() initializes 496 * the fpu and sets fpcurthread = NULL as important side effects. 497 */ 498 savecrit = intr_disable(); 499 npxsave(&dummy); 500 stop_emulating(); 501#ifdef CPU_ENABLE_SSE 502 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 503 if (cpu_fxsr) 504 fninit(); 505#endif 506 fldcw(&control); 507 start_emulating(); 508 intr_restore(savecrit); 509} 510 511/* 512 * Free coprocessor (if we have it). 513 */ 514void 515npxexit(td) 516 struct thread *td; 517{ 518 register_t savecrit; 519 520 savecrit = intr_disable(); 521 if (curthread == PCPU_GET(fpcurthread)) 522 npxsave(&PCPU_GET(curpcb)->pcb_save); 523 intr_restore(savecrit); 524#ifdef NPX_DEBUG 525 if (npx_exists) { 526 u_int masked_exceptions; 527 528 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 529 /* 530 * Log exceptions that would have trapped with the old 531 * control word (overflow, divide by 0, and invalid operand). 532 */ 533 if (masked_exceptions & 0x0d) 534 log(LOG_ERR, 535 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 536 td->td_proc->p_pid, td->td_proc->p_comm, 537 masked_exceptions); 538 } 539#endif 540} 541 542int 543npxformat() 544{ 545 546 if (!npx_exists) 547 return (_MC_FPFMT_NODEV); 548#ifdef CPU_ENABLE_SSE 549 if (cpu_fxsr) 550 return (_MC_FPFMT_XMM); 551#endif 552 return (_MC_FPFMT_387); 553} 554 555/* 556 * The following mechanism is used to ensure that the FPE_... value 557 * that is passed as a trapcode to the signal handler of the user 558 * process does not have more than one bit set. 559 * 560 * Multiple bits may be set if the user process modifies the control 561 * word while a status word bit is already set. While this is a sign 562 * of bad coding, we have no choise than to narrow them down to one 563 * bit, since we must not send a trapcode that is not exactly one of 564 * the FPE_ macros. 565 * 566 * The mechanism has a static table with 127 entries. Each combination 567 * of the 7 FPU status word exception bits directly translates to a 568 * position in this table, where a single FPE_... value is stored. 569 * This FPE_... value stored there is considered the "most important" 570 * of the exception bits and will be sent as the signal code. The 571 * precedence of the bits is based upon Intel Document "Numerical 572 * Applications", Chapter "Special Computational Situations". 573 * 574 * The macro to choose one of these values does these steps: 1) Throw 575 * away status word bits that cannot be masked. 2) Throw away the bits 576 * currently masked in the control word, assuming the user isn't 577 * interested in them anymore. 3) Reinsert status word bit 7 (stack 578 * fault) if it is set, which cannot be masked but must be presered. 579 * 4) Use the remaining bits to point into the trapcode table. 580 * 581 * The 6 maskable bits in order of their preference, as stated in the 582 * above referenced Intel manual: 583 * 1 Invalid operation (FP_X_INV) 584 * 1a Stack underflow 585 * 1b Stack overflow 586 * 1c Operand of unsupported format 587 * 1d SNaN operand. 588 * 2 QNaN operand (not an exception, irrelavant here) 589 * 3 Any other invalid-operation not mentioned above or zero divide 590 * (FP_X_INV, FP_X_DZ) 591 * 4 Denormal operand (FP_X_DNML) 592 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 593 * 6 Inexact result (FP_X_IMP) 594 */ 595static char fpetable[128] = { 596 0, 597 FPE_FLTINV, /* 1 - INV */ 598 FPE_FLTUND, /* 2 - DNML */ 599 FPE_FLTINV, /* 3 - INV | DNML */ 600 FPE_FLTDIV, /* 4 - DZ */ 601 FPE_FLTINV, /* 5 - INV | DZ */ 602 FPE_FLTDIV, /* 6 - DNML | DZ */ 603 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 604 FPE_FLTOVF, /* 8 - OFL */ 605 FPE_FLTINV, /* 9 - INV | OFL */ 606 FPE_FLTUND, /* A - DNML | OFL */ 607 FPE_FLTINV, /* B - INV | DNML | OFL */ 608 FPE_FLTDIV, /* C - DZ | OFL */ 609 FPE_FLTINV, /* D - INV | DZ | OFL */ 610 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 611 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 612 FPE_FLTUND, /* 10 - UFL */ 613 FPE_FLTINV, /* 11 - INV | UFL */ 614 FPE_FLTUND, /* 12 - DNML | UFL */ 615 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 616 FPE_FLTDIV, /* 14 - DZ | UFL */ 617 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 618 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 619 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 620 FPE_FLTOVF, /* 18 - OFL | UFL */ 621 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 622 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 623 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 624 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 625 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 626 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 627 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 628 FPE_FLTRES, /* 20 - IMP */ 629 FPE_FLTINV, /* 21 - INV | IMP */ 630 FPE_FLTUND, /* 22 - DNML | IMP */ 631 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 632 FPE_FLTDIV, /* 24 - DZ | IMP */ 633 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 634 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 635 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 636 FPE_FLTOVF, /* 28 - OFL | IMP */ 637 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 638 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 639 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 640 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 641 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 642 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 643 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 644 FPE_FLTUND, /* 30 - UFL | IMP */ 645 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 646 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 647 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 648 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 649 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 650 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 651 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 652 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 653 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 654 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 655 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 656 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 657 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 658 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 659 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 660 FPE_FLTSUB, /* 40 - STK */ 661 FPE_FLTSUB, /* 41 - INV | STK */ 662 FPE_FLTUND, /* 42 - DNML | STK */ 663 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 664 FPE_FLTDIV, /* 44 - DZ | STK */ 665 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 666 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 667 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 668 FPE_FLTOVF, /* 48 - OFL | STK */ 669 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 670 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 671 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 672 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 673 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 674 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 675 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 676 FPE_FLTUND, /* 50 - UFL | STK */ 677 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 678 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 679 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 680 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 681 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 682 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 683 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 684 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 685 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 686 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 687 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 688 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 689 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 690 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 691 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 692 FPE_FLTRES, /* 60 - IMP | STK */ 693 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 694 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 695 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 696 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 697 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 698 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 699 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 700 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 701 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 702 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 703 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 704 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 705 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 706 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 707 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 708 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 709 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 710 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 711 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 712 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 713 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 714 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 715 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 716 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 717 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 718 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 719 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 720 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 721 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 722 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 723 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 724}; 725 726/* 727 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 728 * 729 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 730 * depend on longjmp() restoring a usable state. Restoring the state 731 * or examining it might fail if we didn't clear exceptions. 732 * 733 * The error code chosen will be one of the FPE_... macros. It will be 734 * sent as the second argument to old BSD-style signal handlers and as 735 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 736 * 737 * XXX the FP state is not preserved across signal handlers. So signal 738 * handlers cannot afford to do FP unless they preserve the state or 739 * longjmp() out. Both preserving the state and longjmp()ing may be 740 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 741 * solution for signals other than SIGFPE. 742 */ 743int 744npxtrap() 745{ 746 register_t savecrit; 747 u_short control, status; 748 749 if (!npx_exists) { 750 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 751 PCPU_GET(fpcurthread), curthread, npx_exists); 752 panic("npxtrap from nowhere"); 753 } 754 savecrit = intr_disable(); 755 756 /* 757 * Interrupt handling (for another interrupt) may have pushed the 758 * state to memory. Fetch the relevant parts of the state from 759 * wherever they are. 760 */ 761 if (PCPU_GET(fpcurthread) != curthread) { 762 control = GET_FPU_CW(curthread); 763 status = GET_FPU_SW(curthread); 764 } else { 765 fnstcw(&control); 766 fnstsw(&status); 767 } 768 769 if (PCPU_GET(fpcurthread) == curthread) 770 fnclex(); 771 intr_restore(savecrit); 772 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 773} 774 775/* 776 * Implement device not available (DNA) exception 777 * 778 * It would be better to switch FP context here (if curthread != fpcurthread) 779 * and not necessarily for every context switch, but it is too hard to 780 * access foreign pcb's. 781 */ 782 783static int err_count = 0; 784 785int 786npxdna() 787{ 788 struct pcb *pcb; 789 register_t s; 790 u_short control; 791 792 if (!npx_exists) 793 return (0); 794 if (PCPU_GET(fpcurthread) == curthread) { 795 printf("npxdna: fpcurthread == curthread %d times\n", 796 ++err_count); 797 stop_emulating(); 798 return (1); 799 } 800 if (PCPU_GET(fpcurthread) != NULL) { 801 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 802 PCPU_GET(fpcurthread), 803 PCPU_GET(fpcurthread)->td_proc->p_pid, 804 curthread, curthread->td_proc->p_pid); 805 panic("npxdna"); 806 } 807 s = intr_disable(); 808 stop_emulating(); 809 /* 810 * Record new context early in case frstor causes an IRQ13. 811 */ 812 PCPU_SET(fpcurthread, curthread); 813 pcb = PCPU_GET(curpcb); 814 815 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 816 /* 817 * This is the first time this thread has used the FPU or 818 * the PCB doesn't contain a clean FPU state. Explicitly 819 * initialize the FPU and load the default control word. 820 */ 821 fninit(); 822 control = __INITIAL_NPXCW__; 823 fldcw(&control); 824 pcb->pcb_flags |= PCB_NPXINITDONE; 825 } else { 826 /* 827 * The following frstor may cause an IRQ13 when the state 828 * being restored has a pending error. The error will 829 * appear to have been triggered by the current (npx) user 830 * instruction even when that instruction is a no-wait 831 * instruction that should not trigger an error (e.g., 832 * fnclex). On at least one 486 system all of the no-wait 833 * instructions are broken the same as frstor, so our 834 * treatment does not amplify the breakage. On at least 835 * one 386/Cyrix 387 system, fnclex works correctly while 836 * frstor and fnsave are broken, so our treatment breaks 837 * fnclex if it is the first FPU instruction after a context 838 * switch. 839 */ 840 fpurstor(&pcb->pcb_save); 841 } 842 intr_restore(s); 843 844 return (1); 845} 846 847/* 848 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 849 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 850 * no-wait npx instructions. See the Intel application note AP-578 for 851 * details. This doesn't cause any additional complications here. IRQ13's 852 * are inherently asynchronous unless the CPU is frozen to deliver them -- 853 * one that started in userland may be delivered many instructions later, 854 * after the process has entered the kernel. It may even be delivered after 855 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 856 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 857 * it is normally ignored at first because we set fpcurthread to NULL; it is 858 * normally retriggered in npxdna() after return to user mode. 859 * 860 * npxsave() must be called with interrupts disabled, so that it clears 861 * fpcurthread atomically with saving the state. We require callers to do the 862 * disabling, since most callers need to disable interrupts anyway to call 863 * npxsave() atomically with checking fpcurthread. 864 * 865 * A previous version of npxsave() went to great lengths to excecute fnsave 866 * with interrupts enabled in case executing it froze the CPU. This case 867 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 868 * spurious freezes. 869 */ 870void 871npxsave(addr) 872 union savefpu *addr; 873{ 874 875 stop_emulating(); 876 fpusave(addr); 877 878 start_emulating(); 879 PCPU_SET(fpcurthread, NULL); 880} 881 882/* 883 * This should be called with interrupts disabled and only when the owning 884 * FPU thread is non-null. 885 */ 886void 887npxdrop() 888{ 889 struct thread *td; 890 891 td = PCPU_GET(fpcurthread); 892 PCPU_SET(fpcurthread, NULL); 893 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 894 start_emulating(); 895} 896 897/* 898 * Get the state of the FPU without dropping ownership (if possible). 899 * It returns the FPU ownership status. 900 */ 901int 902npxgetregs(td, addr) 903 struct thread *td; 904 union savefpu *addr; 905{ 906 register_t s; 907 908 if (!npx_exists) 909 return (_MC_FPOWNED_NONE); 910 911 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 912 if (npx_cleanstate_ready) 913 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 914 else 915 bzero(addr, sizeof(*addr)); 916 return (_MC_FPOWNED_NONE); 917 } 918 s = intr_disable(); 919 if (td == PCPU_GET(fpcurthread)) { 920 fpusave(addr); 921#ifdef CPU_ENABLE_SSE 922 if (!cpu_fxsr) 923#endif 924 /* 925 * fnsave initializes the FPU and destroys whatever 926 * context it contains. Make sure the FPU owner 927 * starts with a clean state next time. 928 */ 929 npxdrop(); 930 intr_restore(s); 931 return (_MC_FPOWNED_FPU); 932 } else { 933 intr_restore(s); 934 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 935 return (_MC_FPOWNED_PCB); 936 } 937} 938 939/* 940 * Set the state of the FPU. 941 */ 942void 943npxsetregs(td, addr) 944 struct thread *td; 945 union savefpu *addr; 946{ 947 register_t s; 948 949 if (!npx_exists) 950 return; 951 952 s = intr_disable(); 953 if (td == PCPU_GET(fpcurthread)) { 954 fpurstor(addr); 955 intr_restore(s); 956 } else { 957 intr_restore(s); 958 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 959 } 960 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 961} 962 963static void 964fpusave(addr) 965 union savefpu *addr; 966{ 967 968#ifdef CPU_ENABLE_SSE 969 if (cpu_fxsr) 970 fxsave(addr); 971 else 972#endif 973 fnsave(addr); 974} 975 976static void 977fpurstor(addr) 978 union savefpu *addr; 979{ 980 981#ifdef CPU_ENABLE_SSE 982 if (cpu_fxsr) 983 fxrstor(addr); 984 else 985#endif 986 frstor(addr); 987} 988 989#ifdef I586_CPU_XXX 990static long 991timezero(funcname, func) 992 const char *funcname; 993 void (*func)(void *buf, size_t len); 994 995{ 996 void *buf; 997#define BUFSIZE 1048576 998 long usec; 999 struct timeval finish, start; 1000 1001 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 1002 if (buf == NULL) 1003 return (BUFSIZE); 1004 microtime(&start); 1005 (*func)(buf, BUFSIZE); 1006 microtime(&finish); 1007 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1008 finish.tv_usec - start.tv_usec; 1009 if (usec <= 0) 1010 usec = 1; 1011 if (bootverbose) 1012 printf("%s bandwidth = %u kBps\n", funcname, 1013 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1014 free(buf, M_TEMP); 1015 return (usec); 1016} 1017#endif /* I586_CPU */ 1018 1019static device_method_t npx_methods[] = { 1020 /* Device interface */ 1021 DEVMETHOD(device_identify, npx_identify), 1022 DEVMETHOD(device_probe, npx_probe), 1023 DEVMETHOD(device_attach, npx_attach), 1024 DEVMETHOD(device_detach, bus_generic_detach), 1025 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1026 DEVMETHOD(device_suspend, bus_generic_suspend), 1027 DEVMETHOD(device_resume, bus_generic_resume), 1028 1029 { 0, 0 } 1030}; 1031 1032static driver_t npx_driver = { 1033 "npx", 1034 npx_methods, 1035 1, /* no softc */ 1036}; 1037 1038static devclass_t npx_devclass; 1039 1040/* 1041 * We prefer to attach to the root nexus so that the usual case (exception 16) 1042 * doesn't describe the processor as being `on isa'. 1043 */ 1044DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1045 1046#ifdef DEV_ISA 1047/* 1048 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1049 */ 1050static struct isa_pnp_id npxisa_ids[] = { 1051 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1052 { 0 } 1053}; 1054 1055static int 1056npxisa_probe(device_t dev) 1057{ 1058 int result; 1059 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1060 device_quiet(dev); 1061 } 1062 return(result); 1063} 1064 1065static int 1066npxisa_attach(device_t dev) 1067{ 1068 return (0); 1069} 1070 1071static device_method_t npxisa_methods[] = { 1072 /* Device interface */ 1073 DEVMETHOD(device_probe, npxisa_probe), 1074 DEVMETHOD(device_attach, npxisa_attach), 1075 DEVMETHOD(device_detach, bus_generic_detach), 1076 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1077 DEVMETHOD(device_suspend, bus_generic_suspend), 1078 DEVMETHOD(device_resume, bus_generic_resume), 1079 1080 { 0, 0 } 1081}; 1082 1083static driver_t npxisa_driver = { 1084 "npxisa", 1085 npxisa_methods, 1086 1, /* no softc */ 1087}; 1088 1089static devclass_t npxisa_devclass; 1090 1091DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1092#ifndef PC98 1093DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1094#endif 1095#endif /* DEV_ISA */ 1096