npx.c revision 117870
1/*- 2 * Copyright (c) 1990 William Jolitz. 3 * Copyright (c) 1991 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by the University of 17 * California, Berkeley and its contributors. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/i386/isa/npx.c 117870 2003-07-22 08:11:17Z peter $"); 39 40#include "opt_cpu.h" 41#include "opt_debug_npx.h" 42#include "opt_isa.h" 43#include "opt_npx.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/mutex.h> 54#include <sys/proc.h> 55#include <sys/sysctl.h> 56#include <machine/bus.h> 57#include <sys/rman.h> 58#ifdef NPX_DEBUG 59#include <sys/syslog.h> 60#endif 61#include <sys/signalvar.h> 62#include <sys/user.h> 63 64#ifndef SMP 65#include <machine/asmacros.h> 66#endif 67#include <machine/cputypes.h> 68#include <machine/frame.h> 69#include <machine/md_var.h> 70#include <machine/pcb.h> 71#include <machine/psl.h> 72#ifndef SMP 73#include <machine/clock.h> 74#endif 75#include <machine/resource.h> 76#include <machine/specialreg.h> 77#include <machine/segments.h> 78#include <machine/ucontext.h> 79 80#ifndef SMP 81#include <i386/isa/icu.h> 82#ifdef PC98 83#include <pc98/pc98/pc98.h> 84#else 85#include <i386/isa/isa.h> 86#endif 87#endif 88#include <i386/isa/intr_machdep.h> 89#ifdef DEV_ISA 90#include <isa/isavar.h> 91#endif 92 93#if !defined(CPU_ENABLE_SSE) && defined(I686_CPU) 94#define CPU_ENABLE_SSE 95#endif 96#if defined(CPU_DISABLE_SSE) 97#undef CPU_ENABLE_SSE 98#endif 99 100/* 101 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver. 102 */ 103 104/* Configuration flags. */ 105#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0) 106#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1) 107#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2) 108 109#if defined(__GNUC__) && !defined(lint) 110 111#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr))) 112#define fnclex() __asm("fnclex") 113#define fninit() __asm("fninit") 114#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr))) 115#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr))) 116#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr))) 117#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop") 118#define frstor(addr) __asm("frstor %0" : : "m" (*(addr))) 119#ifdef CPU_ENABLE_SSE 120#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr))) 121#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr))) 122#endif 123#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \ 124 : : "n" (CR0_TS) : "ax") 125#define stop_emulating() __asm("clts") 126 127#else /* not __GNUC__ */ 128 129void fldcw(caddr_t addr); 130void fnclex(void); 131void fninit(void); 132void fnsave(caddr_t addr); 133void fnstcw(caddr_t addr); 134void fnstsw(caddr_t addr); 135void fp_divide_by_0(void); 136void frstor(caddr_t addr); 137#ifdef CPU_ENABLE_SSE 138void fxsave(caddr_t addr); 139void fxrstor(caddr_t addr); 140#endif 141void start_emulating(void); 142void stop_emulating(void); 143 144#endif /* __GNUC__ */ 145 146#ifdef CPU_ENABLE_SSE 147#define GET_FPU_CW(thread) \ 148 (cpu_fxsr ? \ 149 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_cw : \ 150 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_cw) 151#define GET_FPU_SW(thread) \ 152 (cpu_fxsr ? \ 153 (thread)->td_pcb->pcb_save.sv_xmm.sv_env.en_sw : \ 154 (thread)->td_pcb->pcb_save.sv_87.sv_env.en_sw) 155#else /* CPU_ENABLE_SSE */ 156#define GET_FPU_CW(thread) \ 157 (thread->td_pcb->pcb_save.sv_87.sv_env.en_cw) 158#define GET_FPU_SW(thread) \ 159 (thread->td_pcb->pcb_save.sv_87.sv_env.en_sw) 160#endif /* CPU_ENABLE_SSE */ 161 162typedef u_char bool_t; 163 164static void fpusave(union savefpu *); 165static void fpurstor(union savefpu *); 166static int npx_attach(device_t dev); 167static void npx_identify(driver_t *driver, device_t parent); 168#ifndef SMP 169static void npx_intr(void *); 170#endif 171static int npx_probe(device_t dev); 172#ifdef I586_CPU_XXX 173static long timezero(const char *funcname, 174 void (*func)(void *buf, size_t len)); 175#endif /* I586_CPU */ 176 177int hw_float; /* XXX currently just alias for npx_exists */ 178 179SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint, 180 CTLFLAG_RD, &hw_float, 0, 181 "Floatingpoint instructions executed in hardware"); 182 183#ifndef SMP 184static volatile u_int npx_intrs_while_probing; 185static volatile u_int npx_traps_while_probing; 186#endif 187 188static union savefpu npx_cleanstate; 189static bool_t npx_cleanstate_ready; 190static bool_t npx_ex16; 191static bool_t npx_exists; 192static bool_t npx_irq13; 193 194#ifndef SMP 195alias_for_inthand_t probetrap; 196__asm(" \n\ 197 .text \n\ 198 .p2align 2,0x90 \n\ 199 .type " __XSTRING(CNAME(probetrap)) ",@function \n\ 200" __XSTRING(CNAME(probetrap)) ": \n\ 201 ss \n\ 202 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\ 203 fnclex \n\ 204 iret \n\ 205"); 206#endif /* SMP */ 207 208/* 209 * Identify routine. Create a connection point on our parent for probing. 210 */ 211static void 212npx_identify(driver, parent) 213 driver_t *driver; 214 device_t parent; 215{ 216 device_t child; 217 218 child = BUS_ADD_CHILD(parent, 0, "npx", 0); 219 if (child == NULL) 220 panic("npx_identify"); 221} 222 223#ifndef SMP 224/* 225 * Do minimal handling of npx interrupts to convert them to traps. 226 */ 227static void 228npx_intr(dummy) 229 void *dummy; 230{ 231 struct thread *td; 232 233#ifndef SMP 234 npx_intrs_while_probing++; 235#endif 236 237 /* 238 * The BUSY# latch must be cleared in all cases so that the next 239 * unmasked npx exception causes an interrupt. 240 */ 241#ifdef PC98 242 outb(0xf8, 0); 243#else 244 outb(0xf0, 0); 245#endif 246 247 /* 248 * fpcurthread is normally non-null here. In that case, schedule an 249 * AST to finish the exception handling in the correct context 250 * (this interrupt may occur after the thread has entered the 251 * kernel via a syscall or an interrupt). Otherwise, the npx 252 * state of the thread that caused this interrupt must have been 253 * pushed to the thread's pcb, and clearing of the busy latch 254 * above has finished the (essentially null) handling of this 255 * interrupt. Control will eventually return to the instruction 256 * that caused it and it will repeat. We will eventually (usually 257 * soon) win the race to handle the interrupt properly. 258 */ 259 td = PCPU_GET(fpcurthread); 260 if (td != NULL) { 261 td->td_pcb->pcb_flags |= PCB_NPXTRAP; 262 mtx_lock_spin(&sched_lock); 263 td->td_flags |= TDF_ASTPENDING; 264 mtx_unlock_spin(&sched_lock); 265 } 266} 267#endif /* !SMP */ 268 269/* 270 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait 271 * whether the device exists or not (XXX should be elsewhere). Set flags 272 * to tell npxattach() what to do. Modify device struct if npx doesn't 273 * need to use interrupts. Return 0 if device exists. 274 */ 275static int 276npx_probe(dev) 277 device_t dev; 278{ 279#ifndef SMP 280 struct gate_descriptor save_idt_npxtrap; 281 struct resource *ioport_res, *irq_res; 282 void *irq_cookie; 283 int ioport_rid, irq_num, irq_rid; 284 u_short control; 285 u_short status; 286 287 save_idt_npxtrap = idt[16]; 288 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 289 ioport_rid = 0; 290 ioport_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &ioport_rid, 291 IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE); 292 if (ioport_res == NULL) 293 panic("npx: can't get ports"); 294#ifdef PC98 295 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 296 irq_num = 8; 297#else 298 if (resource_int_value("npx", 0, "irq", &irq_num) != 0) 299 irq_num = 13; 300#endif 301 irq_rid = 0; 302 irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &irq_rid, irq_num, 303 irq_num, 1, RF_ACTIVE); 304 if (irq_res == NULL) 305 panic("npx: can't get IRQ"); 306 if (bus_setup_intr(dev, irq_res, INTR_TYPE_MISC | INTR_FAST, npx_intr, 307 NULL, &irq_cookie) != 0) 308 panic("npx: can't create intr"); 309#endif /* !SMP */ 310 311 /* 312 * Partially reset the coprocessor, if any. Some BIOS's don't reset 313 * it after a warm boot. 314 */ 315#ifdef PC98 316 outb(0xf8,0); 317#else 318 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 319 outb(0xf0, 0); /* clear BUSY# latch */ 320#endif 321 /* 322 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 323 * instructions. We must set the CR0_MP bit and use the CR0_TS 324 * bit to control the trap, because setting the CR0_EM bit does 325 * not cause WAIT instructions to trap. It's important to trap 326 * WAIT instructions - otherwise the "wait" variants of no-wait 327 * control instructions would degenerate to the "no-wait" variants 328 * after FP context switches but work correctly otherwise. It's 329 * particularly important to trap WAITs when there is no NPX - 330 * otherwise the "wait" variants would always degenerate. 331 * 332 * Try setting CR0_NE to get correct error reporting on 486DX's. 333 * Setting it should fail or do nothing on lesser processors. 334 */ 335 load_cr0(rcr0() | CR0_MP | CR0_NE); 336 /* 337 * But don't trap while we're probing. 338 */ 339 stop_emulating(); 340 /* 341 * Finish resetting the coprocessor, if any. If there is an error 342 * pending, then we may get a bogus IRQ13, but npx_intr() will handle 343 * it OK. Bogus halts have never been observed, but we enabled 344 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 345 */ 346 fninit(); 347 348 device_set_desc(dev, "math processor"); 349 350#ifdef SMP 351 352 /* 353 * Exception 16 MUST work for SMP. 354 */ 355 npx_ex16 = hw_float = npx_exists = 1; 356 return (0); 357 358#else /* !SMP */ 359 360 /* 361 * Don't use fwait here because it might hang. 362 * Don't use fnop here because it usually hangs if there is no FPU. 363 */ 364 DELAY(1000); /* wait for any IRQ13 */ 365#ifdef DIAGNOSTIC 366 if (npx_intrs_while_probing != 0) 367 printf("fninit caused %u bogus npx interrupt(s)\n", 368 npx_intrs_while_probing); 369 if (npx_traps_while_probing != 0) 370 printf("fninit caused %u bogus npx trap(s)\n", 371 npx_traps_while_probing); 372#endif 373 /* 374 * Check for a status of mostly zero. 375 */ 376 status = 0x5a5a; 377 fnstsw(&status); 378 if ((status & 0xb8ff) == 0) { 379 /* 380 * Good, now check for a proper control word. 381 */ 382 control = 0x5a5a; 383 fnstcw(&control); 384 if ((control & 0x1f3f) == 0x033f) { 385 hw_float = npx_exists = 1; 386 /* 387 * We have an npx, now divide by 0 to see if exception 388 * 16 works. 389 */ 390 control &= ~(1 << 2); /* enable divide by 0 trap */ 391 fldcw(&control); 392#ifdef FPU_ERROR_BROKEN 393 /* 394 * FPU error signal doesn't work on some CPU 395 * accelerator board. 396 */ 397 npx_ex16 = 1; 398 return (0); 399#endif 400 npx_traps_while_probing = npx_intrs_while_probing = 0; 401 fp_divide_by_0(); 402 if (npx_traps_while_probing != 0) { 403 /* 404 * Good, exception 16 works. 405 */ 406 npx_ex16 = 1; 407 goto no_irq13; 408 } 409 if (npx_intrs_while_probing != 0) { 410 /* 411 * Bad, we are stuck with IRQ13. 412 */ 413 npx_irq13 = 1; 414 idt[16] = save_idt_npxtrap; 415 return (0); 416 } 417 /* 418 * Worse, even IRQ13 is broken. Use emulator. 419 */ 420 } 421 } 422 /* 423 * Probe failed, but we want to get to npxattach to initialize the 424 * emulator and say that it has been installed. XXX handle devices 425 * that aren't really devices better. 426 */ 427 /* FALLTHROUGH */ 428no_irq13: 429 idt[16] = save_idt_npxtrap; 430 bus_teardown_intr(dev, irq_res, irq_cookie); 431 432 /* 433 * XXX hack around brokenness of bus_teardown_intr(). If we left the 434 * irq active then we would get it instead of exception 16. 435 */ 436 { 437 register_t crit; 438 439 crit = intr_disable(); 440 mtx_lock_spin(&icu_lock); 441 INTRDIS(1 << irq_num); 442 mtx_unlock_spin(&icu_lock); 443 intr_restore(crit); 444 } 445 446 bus_release_resource(dev, SYS_RES_IRQ, irq_rid, irq_res); 447 bus_release_resource(dev, SYS_RES_IOPORT, ioport_rid, ioport_res); 448 return (0); 449 450#endif /* SMP */ 451} 452 453/* 454 * Attach routine - announce which it is, and wire into system 455 */ 456static int 457npx_attach(dev) 458 device_t dev; 459{ 460 int flags; 461 register_t s; 462 463 if (resource_int_value("npx", 0, "flags", &flags) != 0) 464 flags = 0; 465 466 if (flags) 467 device_printf(dev, "flags 0x%x ", flags); 468 if (npx_irq13) { 469 device_printf(dev, "using IRQ 13 interface\n"); 470 } else { 471 if (npx_ex16) 472 device_printf(dev, "INT 16 interface\n"); 473 else 474 device_printf(dev, "WARNING: no FPU!\n"); 475 } 476 npxinit(__INITIAL_NPXCW__); 477 478 if (npx_cleanstate_ready == 0) { 479 s = intr_disable(); 480 stop_emulating(); 481 fpusave(&npx_cleanstate); 482 start_emulating(); 483 npx_cleanstate_ready = 1; 484 intr_restore(s); 485 } 486#ifdef I586_CPU_XXX 487 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 488 timezero("i586_bzero()", i586_bzero) < 489 timezero("bzero()", bzero) * 4 / 5) { 490 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) 491 bcopy_vector = i586_bcopy; 492 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 493 bzero_vector = i586_bzero; 494 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 495 copyin_vector = i586_copyin; 496 copyout_vector = i586_copyout; 497 } 498 } 499#endif 500 501 return (0); /* XXX unused */ 502} 503 504/* 505 * Initialize floating point unit. 506 */ 507void 508npxinit(control) 509 u_short control; 510{ 511 static union savefpu dummy; 512 register_t savecrit; 513 514 if (!npx_exists) 515 return; 516 /* 517 * fninit has the same h/w bugs as fnsave. Use the detoxified 518 * fnsave to throw away any junk in the fpu. npxsave() initializes 519 * the fpu and sets fpcurthread = NULL as important side effects. 520 */ 521 savecrit = intr_disable(); 522 npxsave(&dummy); 523 stop_emulating(); 524#ifdef CPU_ENABLE_SSE 525 /* XXX npxsave() doesn't actually initialize the fpu in the SSE case. */ 526 if (cpu_fxsr) 527 fninit(); 528#endif 529 fldcw(&control); 530 start_emulating(); 531 intr_restore(savecrit); 532} 533 534/* 535 * Free coprocessor (if we have it). 536 */ 537void 538npxexit(td) 539 struct thread *td; 540{ 541 register_t savecrit; 542 543 savecrit = intr_disable(); 544 if (curthread == PCPU_GET(fpcurthread)) 545 npxsave(&PCPU_GET(curpcb)->pcb_save); 546 intr_restore(savecrit); 547#ifdef NPX_DEBUG 548 if (npx_exists) { 549 u_int masked_exceptions; 550 551 masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f; 552 /* 553 * Log exceptions that would have trapped with the old 554 * control word (overflow, divide by 0, and invalid operand). 555 */ 556 if (masked_exceptions & 0x0d) 557 log(LOG_ERR, 558 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 559 td->td_proc->p_pid, td->td_proc->p_comm, 560 masked_exceptions); 561 } 562#endif 563} 564 565int 566npxformat() 567{ 568 569 if (!npx_exists) 570 return (_MC_FPFMT_NODEV); 571#ifdef CPU_ENABLE_SSE 572 if (cpu_fxsr) 573 return (_MC_FPFMT_XMM); 574#endif 575 return (_MC_FPFMT_387); 576} 577 578/* 579 * The following mechanism is used to ensure that the FPE_... value 580 * that is passed as a trapcode to the signal handler of the user 581 * process does not have more than one bit set. 582 * 583 * Multiple bits may be set if the user process modifies the control 584 * word while a status word bit is already set. While this is a sign 585 * of bad coding, we have no choise than to narrow them down to one 586 * bit, since we must not send a trapcode that is not exactly one of 587 * the FPE_ macros. 588 * 589 * The mechanism has a static table with 127 entries. Each combination 590 * of the 7 FPU status word exception bits directly translates to a 591 * position in this table, where a single FPE_... value is stored. 592 * This FPE_... value stored there is considered the "most important" 593 * of the exception bits and will be sent as the signal code. The 594 * precedence of the bits is based upon Intel Document "Numerical 595 * Applications", Chapter "Special Computational Situations". 596 * 597 * The macro to choose one of these values does these steps: 1) Throw 598 * away status word bits that cannot be masked. 2) Throw away the bits 599 * currently masked in the control word, assuming the user isn't 600 * interested in them anymore. 3) Reinsert status word bit 7 (stack 601 * fault) if it is set, which cannot be masked but must be presered. 602 * 4) Use the remaining bits to point into the trapcode table. 603 * 604 * The 6 maskable bits in order of their preference, as stated in the 605 * above referenced Intel manual: 606 * 1 Invalid operation (FP_X_INV) 607 * 1a Stack underflow 608 * 1b Stack overflow 609 * 1c Operand of unsupported format 610 * 1d SNaN operand. 611 * 2 QNaN operand (not an exception, irrelavant here) 612 * 3 Any other invalid-operation not mentioned above or zero divide 613 * (FP_X_INV, FP_X_DZ) 614 * 4 Denormal operand (FP_X_DNML) 615 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 616 * 6 Inexact result (FP_X_IMP) 617 */ 618static char fpetable[128] = { 619 0, 620 FPE_FLTINV, /* 1 - INV */ 621 FPE_FLTUND, /* 2 - DNML */ 622 FPE_FLTINV, /* 3 - INV | DNML */ 623 FPE_FLTDIV, /* 4 - DZ */ 624 FPE_FLTINV, /* 5 - INV | DZ */ 625 FPE_FLTDIV, /* 6 - DNML | DZ */ 626 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 627 FPE_FLTOVF, /* 8 - OFL */ 628 FPE_FLTINV, /* 9 - INV | OFL */ 629 FPE_FLTUND, /* A - DNML | OFL */ 630 FPE_FLTINV, /* B - INV | DNML | OFL */ 631 FPE_FLTDIV, /* C - DZ | OFL */ 632 FPE_FLTINV, /* D - INV | DZ | OFL */ 633 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 634 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 635 FPE_FLTUND, /* 10 - UFL */ 636 FPE_FLTINV, /* 11 - INV | UFL */ 637 FPE_FLTUND, /* 12 - DNML | UFL */ 638 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 639 FPE_FLTDIV, /* 14 - DZ | UFL */ 640 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 641 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 642 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 643 FPE_FLTOVF, /* 18 - OFL | UFL */ 644 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 645 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 646 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 647 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 648 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 649 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 650 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 651 FPE_FLTRES, /* 20 - IMP */ 652 FPE_FLTINV, /* 21 - INV | IMP */ 653 FPE_FLTUND, /* 22 - DNML | IMP */ 654 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 655 FPE_FLTDIV, /* 24 - DZ | IMP */ 656 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 657 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 658 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 659 FPE_FLTOVF, /* 28 - OFL | IMP */ 660 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 661 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 662 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 663 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 664 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 665 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 666 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 667 FPE_FLTUND, /* 30 - UFL | IMP */ 668 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 669 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 670 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 671 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 672 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 673 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 674 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 675 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 676 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 677 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 678 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 679 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 680 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 681 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 682 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 683 FPE_FLTSUB, /* 40 - STK */ 684 FPE_FLTSUB, /* 41 - INV | STK */ 685 FPE_FLTUND, /* 42 - DNML | STK */ 686 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 687 FPE_FLTDIV, /* 44 - DZ | STK */ 688 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 689 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 690 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 691 FPE_FLTOVF, /* 48 - OFL | STK */ 692 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 693 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 694 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 695 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 696 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 697 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 698 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 699 FPE_FLTUND, /* 50 - UFL | STK */ 700 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 701 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 702 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 703 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 704 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 705 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 706 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 707 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 708 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 709 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 710 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 711 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 712 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 713 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 714 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 715 FPE_FLTRES, /* 60 - IMP | STK */ 716 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 717 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 718 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 719 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 720 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 721 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 722 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 723 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 724 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 725 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 726 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 727 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 728 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 729 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 730 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 731 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 732 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 733 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 734 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 735 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 736 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 737 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 738 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 739 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 740 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 741 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 742 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 743 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 744 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 745 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 746 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 747}; 748 749/* 750 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 751 * 752 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 753 * depend on longjmp() restoring a usable state. Restoring the state 754 * or examining it might fail if we didn't clear exceptions. 755 * 756 * The error code chosen will be one of the FPE_... macros. It will be 757 * sent as the second argument to old BSD-style signal handlers and as 758 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 759 * 760 * XXX the FP state is not preserved across signal handlers. So signal 761 * handlers cannot afford to do FP unless they preserve the state or 762 * longjmp() out. Both preserving the state and longjmp()ing may be 763 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 764 * solution for signals other than SIGFPE. 765 */ 766int 767npxtrap() 768{ 769 register_t savecrit; 770 u_short control, status; 771 772 if (!npx_exists) { 773 printf("npxtrap: fpcurthread = %p, curthread = %p, npx_exists = %d\n", 774 PCPU_GET(fpcurthread), curthread, npx_exists); 775 panic("npxtrap from nowhere"); 776 } 777 savecrit = intr_disable(); 778 779 /* 780 * Interrupt handling (for another interrupt) may have pushed the 781 * state to memory. Fetch the relevant parts of the state from 782 * wherever they are. 783 */ 784 if (PCPU_GET(fpcurthread) != curthread) { 785 control = GET_FPU_CW(curthread); 786 status = GET_FPU_SW(curthread); 787 } else { 788 fnstcw(&control); 789 fnstsw(&status); 790 } 791 792 if (PCPU_GET(fpcurthread) == curthread) 793 fnclex(); 794 intr_restore(savecrit); 795 return (fpetable[status & ((~control & 0x3f) | 0x40)]); 796} 797 798/* 799 * Implement device not available (DNA) exception 800 * 801 * It would be better to switch FP context here (if curthread != fpcurthread) 802 * and not necessarily for every context switch, but it is too hard to 803 * access foreign pcb's. 804 */ 805 806static int err_count = 0; 807 808int 809npxdna() 810{ 811 struct pcb *pcb; 812 register_t s; 813 u_short control; 814 815 if (!npx_exists) 816 return (0); 817 if (PCPU_GET(fpcurthread) == curthread) { 818 printf("npxdna: fpcurthread == curthread %d times\n", 819 ++err_count); 820 stop_emulating(); 821 return (1); 822 } 823 if (PCPU_GET(fpcurthread) != NULL) { 824 printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n", 825 PCPU_GET(fpcurthread), 826 PCPU_GET(fpcurthread)->td_proc->p_pid, 827 curthread, curthread->td_proc->p_pid); 828 panic("npxdna"); 829 } 830 s = intr_disable(); 831 stop_emulating(); 832 /* 833 * Record new context early in case frstor causes an IRQ13. 834 */ 835 PCPU_SET(fpcurthread, curthread); 836 pcb = PCPU_GET(curpcb); 837 838 if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 839 /* 840 * This is the first time this thread has used the FPU or 841 * the PCB doesn't contain a clean FPU state. Explicitly 842 * initialize the FPU and load the default control word. 843 */ 844 fninit(); 845 control = __INITIAL_NPXCW__; 846 fldcw(&control); 847 pcb->pcb_flags |= PCB_NPXINITDONE; 848 } else { 849 /* 850 * The following frstor may cause an IRQ13 when the state 851 * being restored has a pending error. The error will 852 * appear to have been triggered by the current (npx) user 853 * instruction even when that instruction is a no-wait 854 * instruction that should not trigger an error (e.g., 855 * fnclex). On at least one 486 system all of the no-wait 856 * instructions are broken the same as frstor, so our 857 * treatment does not amplify the breakage. On at least 858 * one 386/Cyrix 387 system, fnclex works correctly while 859 * frstor and fnsave are broken, so our treatment breaks 860 * fnclex if it is the first FPU instruction after a context 861 * switch. 862 */ 863 fpurstor(&pcb->pcb_save); 864 } 865 intr_restore(s); 866 867 return (1); 868} 869 870/* 871 * Wrapper for fnsave instruction, partly to handle hardware bugs. When npx 872 * exceptions are reported via IRQ13, spurious IRQ13's may be triggered by 873 * no-wait npx instructions. See the Intel application note AP-578 for 874 * details. This doesn't cause any additional complications here. IRQ13's 875 * are inherently asynchronous unless the CPU is frozen to deliver them -- 876 * one that started in userland may be delivered many instructions later, 877 * after the process has entered the kernel. It may even be delivered after 878 * the fnsave here completes. A spurious IRQ13 for the fnsave is handled in 879 * the same way as a very-late-arriving non-spurious IRQ13 from user mode: 880 * it is normally ignored at first because we set fpcurthread to NULL; it is 881 * normally retriggered in npxdna() after return to user mode. 882 * 883 * npxsave() must be called with interrupts disabled, so that it clears 884 * fpcurthread atomically with saving the state. We require callers to do the 885 * disabling, since most callers need to disable interrupts anyway to call 886 * npxsave() atomically with checking fpcurthread. 887 * 888 * A previous version of npxsave() went to great lengths to excecute fnsave 889 * with interrupts enabled in case executing it froze the CPU. This case 890 * can't happen, at least for Intel CPU/NPX's. Spurious IRQ13's don't imply 891 * spurious freezes. 892 */ 893void 894npxsave(addr) 895 union savefpu *addr; 896{ 897 898 stop_emulating(); 899 fpusave(addr); 900 901 start_emulating(); 902 PCPU_SET(fpcurthread, NULL); 903} 904 905/* 906 * This should be called with interrupts disabled and only when the owning 907 * FPU thread is non-null. 908 */ 909void 910npxdrop() 911{ 912 struct thread *td; 913 914 td = PCPU_GET(fpcurthread); 915 PCPU_SET(fpcurthread, NULL); 916 td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE; 917 start_emulating(); 918} 919 920/* 921 * Get the state of the FPU without dropping ownership (if possible). 922 * It returns the FPU ownership status. 923 */ 924int 925npxgetregs(td, addr) 926 struct thread *td; 927 union savefpu *addr; 928{ 929 register_t s; 930 931 if (!npx_exists) 932 return (_MC_FPOWNED_NONE); 933 934 if ((td->td_pcb->pcb_flags & PCB_NPXINITDONE) == 0) { 935 if (npx_cleanstate_ready) 936 bcopy(&npx_cleanstate, addr, sizeof(npx_cleanstate)); 937 else 938 bzero(addr, sizeof(*addr)); 939 return (_MC_FPOWNED_NONE); 940 } 941 s = intr_disable(); 942 if (td == PCPU_GET(fpcurthread)) { 943 fpusave(addr); 944#ifdef CPU_ENABLE_SSE 945 if (!cpu_fxsr) 946#endif 947 /* 948 * fnsave initializes the FPU and destroys whatever 949 * context it contains. Make sure the FPU owner 950 * starts with a clean state next time. 951 */ 952 npxdrop(); 953 intr_restore(s); 954 return (_MC_FPOWNED_FPU); 955 } else { 956 intr_restore(s); 957 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr)); 958 return (_MC_FPOWNED_PCB); 959 } 960} 961 962/* 963 * Set the state of the FPU. 964 */ 965void 966npxsetregs(td, addr) 967 struct thread *td; 968 union savefpu *addr; 969{ 970 register_t s; 971 972 if (!npx_exists) 973 return; 974 975 s = intr_disable(); 976 if (td == PCPU_GET(fpcurthread)) { 977 fpurstor(addr); 978 intr_restore(s); 979 } else { 980 intr_restore(s); 981 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr)); 982 } 983 curthread->td_pcb->pcb_flags |= PCB_NPXINITDONE; 984} 985 986static void 987fpusave(addr) 988 union savefpu *addr; 989{ 990 991#ifdef CPU_ENABLE_SSE 992 if (cpu_fxsr) 993 fxsave(addr); 994 else 995#endif 996 fnsave(addr); 997} 998 999static void 1000fpurstor(addr) 1001 union savefpu *addr; 1002{ 1003 1004#ifdef CPU_ENABLE_SSE 1005 if (cpu_fxsr) 1006 fxrstor(addr); 1007 else 1008#endif 1009 frstor(addr); 1010} 1011 1012#ifdef I586_CPU_XXX 1013static long 1014timezero(funcname, func) 1015 const char *funcname; 1016 void (*func)(void *buf, size_t len); 1017 1018{ 1019 void *buf; 1020#define BUFSIZE 1048576 1021 long usec; 1022 struct timeval finish, start; 1023 1024 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 1025 if (buf == NULL) 1026 return (BUFSIZE); 1027 microtime(&start); 1028 (*func)(buf, BUFSIZE); 1029 microtime(&finish); 1030 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 1031 finish.tv_usec - start.tv_usec; 1032 if (usec <= 0) 1033 usec = 1; 1034 if (bootverbose) 1035 printf("%s bandwidth = %u kBps\n", funcname, 1036 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 1037 free(buf, M_TEMP); 1038 return (usec); 1039} 1040#endif /* I586_CPU */ 1041 1042static device_method_t npx_methods[] = { 1043 /* Device interface */ 1044 DEVMETHOD(device_identify, npx_identify), 1045 DEVMETHOD(device_probe, npx_probe), 1046 DEVMETHOD(device_attach, npx_attach), 1047 DEVMETHOD(device_detach, bus_generic_detach), 1048 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1049 DEVMETHOD(device_suspend, bus_generic_suspend), 1050 DEVMETHOD(device_resume, bus_generic_resume), 1051 1052 { 0, 0 } 1053}; 1054 1055static driver_t npx_driver = { 1056 "npx", 1057 npx_methods, 1058 1, /* no softc */ 1059}; 1060 1061static devclass_t npx_devclass; 1062 1063#ifdef DEV_ISA 1064/* 1065 * We prefer to attach to the root nexus so that the usual case (exception 16) 1066 * doesn't describe the processor as being `on isa'. 1067 */ 1068DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 1069 1070/* 1071 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI. 1072 */ 1073static struct isa_pnp_id npxisa_ids[] = { 1074 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 1075 { 0 } 1076}; 1077 1078static int 1079npxisa_probe(device_t dev) 1080{ 1081 int result; 1082 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 1083 device_quiet(dev); 1084 } 1085 return(result); 1086} 1087 1088static int 1089npxisa_attach(device_t dev) 1090{ 1091 return (0); 1092} 1093 1094static device_method_t npxisa_methods[] = { 1095 /* Device interface */ 1096 DEVMETHOD(device_probe, npxisa_probe), 1097 DEVMETHOD(device_attach, npxisa_attach), 1098 DEVMETHOD(device_detach, bus_generic_detach), 1099 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1100 DEVMETHOD(device_suspend, bus_generic_suspend), 1101 DEVMETHOD(device_resume, bus_generic_resume), 1102 1103 { 0, 0 } 1104}; 1105 1106static driver_t npxisa_driver = { 1107 "npxisa", 1108 npxisa_methods, 1109 1, /* no softc */ 1110}; 1111 1112static devclass_t npxisa_devclass; 1113 1114DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 1115#ifndef PC98 1116DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0); 1117#endif 1118#endif /* DEV_ISA */ 1119