if_wl_wavelan.h revision 33046
12061Sjkh/* $Id: if_wl_wavelan.h,v 1.2 1997/08/01 03:33:43 msmith Exp $ */
250479Speter/*
32061Sjkh * Redistribution and use in source and binary forms, with or without
438666Sjb * modification, are permitted provided that the following conditions
532427Sjb * are met:
638666Sjb * 1. Redistributions of source code must retain all copyright
738666Sjb *    notices, this list of conditions and the following disclaimer.
838666Sjb * 2. The names of the authors may not be used to endorse or promote products
938666Sjb *    derived from this software withough specific prior written permission
1064049Salex *
1164049Salex * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
1266071Smarkm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
1373504Sobrien * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
1438666Sjb * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
1544918Sjkh * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1638666Sjb * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
1738666Sjb * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
1838666Sjb * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1938666Sjb * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2038666Sjb * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2138666Sjb *
2238666Sjb */
2338978Sjb#ifndef	_CHIPS_WAVELAN_H
2438978Sjb#define _CHIPS_WAVELAN_H
2532427Sjb
2638666Sjb/* This file contains definitions that are common for all versions of
2738666Sjb * the NCR WaveLAN
2838666Sjb */
2938666Sjb
3038666Sjb#define WAVELAN_ADDR_SIZE	6	/* Size of a MAC address */
3138666Sjb#define WAVELAN_MTU		1500	/* Maximum size of Wavelan packet */
3217308Speter
3338666Sjb/* Modem Management Controler write commands */
3438666Sjb#define MMC_ENCR_KEY		0x00	/* to 0x07 */
3538666Sjb#define MMC_ENCR_ENABLE		0x08
3619175Sbde#define MMC_DES_IO_INVERT	0x0a
3738666Sjb#define MMC_LOOPT_SEL		0x10
3838666Sjb#define MMC_JABBER_ENABLE	0x11
3938042Sbde#define MMC_FREEZE		0x12
4039726Sjb#define MMC_ANTEN_SEL		0x13
4138666Sjb#define MMC_IFS			0x14
4238666Sjb#define MMC_MOD_DELAY		0x15
4338042Sbde#define MMC_JAM_TIME		0x16
4438666Sjb#define MMC_THR_PRE_SET		0x18
4549315Shoek#define MMC_DECAY_PRM		0x19
4617308Speter#define MMC_DECAY_UPDAT_PRM	0x1a
4738666Sjb#define MMC_QUALITY_THR		0x1b
4838666Sjb#define MMC_NETW_ID_L		0x1c
4938666Sjb#define MMC_NETW_ID_H		0x1d
5038666Sjb#define MMC_MODE_SEL		0x1e
5117308Speter#define	MMC_EECTRL		0x20	/* 2.4 Gz */
5245108Sobrien#define	MMC_EEADDR		0x21	/* 2.4 Gz */
5342128Speter#define MMC_EEDATAL		0x22	/* 2.4 Gz */
5442128Speter#define	MMC_EEDATAH		0x23	/* 2.4 Gz */
5538666Sjb#define	MMC_ANALCTRL		0x24	/* 2.4 Gz */
5651361Sjb
5738666Sjb/* fields in MMC registers that relate to EEPROM in WaveMODEM daughtercard */
5817308Speter#define MMC_EECTRL_EEPRE	0x10	/* 2.4 Gz EEPROM Protect Reg Enable */
5938666Sjb#define MMC_EECTRL_DWLD		0x08	/* 2.4 Gz EEPROM Download Synths   */
6017308Speter#define	MMC_EECTRL_EEOP		0x07	/* 2.4 Gz EEPROM Opcode mask	 */
6138666Sjb#define MMC_EECTRL_EEOP_READ	0x06	/* 2.4 Gz EEPROM Read Opcode	 */
6217308Speter#define	MMC_EEADDR_CHAN		0xf0	/* 2.4 Gz EEPROM Channel # mask	 */
6327910Sasami#define	MMC_EEADDR_WDCNT	0x0f	/* 2.4 Gz EEPROM DNLD WordCount-1 */
6443226Sjkh#define	MMC_ANALCTRL_ANTPOL	0x02	/* 2.4 Gz Antenna Polarity mask	 */
6543226Sjkh#define	MMC_ANALCTRL_EXTANT	0x01	/* 2.4 Gz External Antenna mask	 */
6643226Sjkh
6738666Sjb/* MMC read register names */
6827910Sasami#define MMC_DCE_STATUS		0x10
6938666Sjb#define MMC_CORRECT_NWID_L	0x14
7038666Sjb#define MMC_CORRECT_NWID_H	0x15
7138666Sjb#define MMC_WRONG_NWID_L	0x16
7227910Sasami#define MMC_WRONG_NWID_H	0x17
7338666Sjb#define MMC_THR_PRE_SET		0x18
7438666Sjb#define MMC_SIGNAL_LVL		0x19
7543226Sjkh#define MMC_SILENCE_LVL		0x1a
7643226Sjkh#define MMC_SIGN_QUAL		0x1b
7727910Sasami#define MMC_DES_AVAIL		0x09
7838666Sjb#define	MMC_EECTRLstat		0x20	/* 2.4 Gz  EEPROM r/w/dwld status */
7938666Sjb#define	MMC_EEDATALrv		0x22	/* 2.4 Gz  EEPROM read value	  */
8027910Sasami#define	MMC_EEDATAHrv		0x23	/* 2.4 Gz  EEPROM read value	  */
8138666Sjb
8227910Sasami/* fields in MMC registers that relate to EEPROM in WaveMODEM daughtercard */
8317308Speter#define	MMC_EECTRLstat_ID24	0xf0	/* 2.4 Gz  =A0 rev-A, =B0 rev-B   */
8438666Sjb#define	MMC_EECTRLstat_DWLD	0x08	/* 2.4 Gz  Synth/Tx-Pwr DWLD busy */
8538666Sjb#define	MMC_EECTRLstat_EEBUSY	0x04	/* 2.4 Gz  EEPROM busy		  */
8617308Speter
8774842Sru/* additional socket ioctl params for wl card
8868987Smarcel * see sys/sockio.h for numbers.  The 2nd params here
8969496Sjkh * must be greater than any values in sockio.h
9069496Sjkh */
9169496Sjkh
922061Sjkh#define SIOCGWLCNWID	_IOWR('i', 60, struct ifreq)	/* get wlan current nwid */
9355026Smarcel#define SIOCSWLCNWID	_IOWR('i', 61, struct ifreq)	/* set wlan current nwid */
9455026Smarcel#define SIOCGWLPSA	_IOWR('i', 62, struct ifreq)	/* get wlan PSA (all) */
9554324Smarcel#define SIOCSWLPSA	_IOWR('i', 63, struct ifreq)	/* set wlan PSA (all) */
9617308Speter#define	SIOCDWLCACHE	_IOW('i',  64, struct ifreq)	/* clear SNR cache    */
9738666Sjb#define SIOCSWLTHR	_IOW('i',  65, struct ifreq)	/* set new quality threshold */
9817308Speter#define	SIOCGWLEEPROM	_IOWR('i', 66, struct ifreq)	/* get modem EEPROM   */
9955678Smarcel#define	SIOCGWLCACHE	_IOWR('i', 67, struct ifreq)	/* get SNR cache */
10038666Sjb#define	SIOCGWLCITEM	_IOWR('i', 68, struct ifreq)	/* get cache element count */
10154324Smarcel
1022302Spaul/* PSA address definitions */
10339206Sjkh#define WLPSA_ID		0x0	/* ID byte (0 for ISA, 0x14 for MCA) */
10439206Sjkh#define WLPSA_IO1		0x1	/* I/O address 1 */
10539206Sjkh#define WLPSA_IO2		0x2	/* I/O address 2 */
10673349Sru#define WLPSA_IO3		0x3	/* I/O address 3 */
10717308Speter#define WLPSA_BR1		0x4	/* Bootrom address 1 */
10854324Smarcel#define WLPSA_BR2		0x5	/* Bootrom address 2 */
10954324Smarcel#define WLPSA_BR3		0x6	/* Bootrom address 3 */
11054324Smarcel#define WLPSA_HWCONF		0x7	/* HW config bits */
11154324Smarcel#define WLPSA_IRQNO		0x8	/* IRQ value */
11254324Smarcel#define WLPSA_UNIMAC		0x10	/* Universal MAC address */
11354324Smarcel#define WLPSA_LOCALMAC		0x16	/* Locally configured MAC address */
11454324Smarcel#define WLPSA_MACSEL		0x1c	/* MAC selector */
11569659Sobrien#define WLPSA_COMPATNO		0x1d	/* compatability number */
11654324Smarcel#define WLPSA_THRESH		0x1e	/* RF modem threshold preset */
11754324Smarcel#define WLPSA_FEATSEL		0x1f	/* feature select */
11854324Smarcel#define WLPSA_SUBBAND		0x20	/* subband selector */
11954324Smarcel#define WLPSA_QUALTHRESH	0x21	/* RF modem quality threshold preset */
12054324Smarcel#define WLPSA_HWVERSION		0x22	/* hardware version indicator */
12154324Smarcel#define WLPSA_NWID		0x23	/* network ID */
12254324Smarcel#define WLPSA_NWIDENABLE	0x24	/* network ID enable */
12354324Smarcel#define WLPSA_SECURITY		0x25	/* datalink security enable */
12454324Smarcel#define WLPSA_DESKEY		0x26	/* datalink security DES key */
12554324Smarcel#define WLPSA_DBWIDTH		0x2f	/* databus width select */
12654324Smarcel#define WLPSA_CALLCODE		0x30	/* call code (japan only) */
12754324Smarcel#define WLPSA_CONFIGURED	0x3c	/* configuration status */
12854324Smarcel#define WLPSA_CRCLOW		0x3d	/* CRC-16 (lowbyte) */
12954324Smarcel#define WLPSA_CRCHIGH		0x3e	/*        (highbyte) */
13054324Smarcel#define WLPSA_CRCOK		0x3f	/* CRC OK flag */
13154324Smarcel
13254324Smarcel#define WLPSA_COMPATNO_WL24B	0x04	/* 2.4 Gz WaveMODEM ISA rev-B  */
13354324Smarcel
13454324Smarcel/*
13573504Sobrien * signal strength cache
13654324Smarcel *
13754324Smarcel * driver (wlp only at the moment) keeps cache of last
13854324Smarcel * IP (only) packets to arrive including signal strength info.
13938666Sjb * daemons may read this with kvm.  See if_wlp.c for globals
14038666Sjb * that may be accessed through kvm.
14117308Speter *
14238666Sjb * Each entry in the w_sigcache has a unique macsrc and age.
14338666Sjb * Each entry is identified by its macsrc field.
14438666Sjb * Age of the packet is identified by its age field.
14517308Speter */
14655678Smarcel
14755678Smarcel#define  MAXCACHEITEMS	10
14855678Smarcel#ifndef INT_MAX
14955678Smarcel#define        INT_MAX         2147483647
15055678Smarcel#endif
15190395Sru#define  MAX_AGE        (INT_MAX - MAXCACHEITEMS)
15290395Sru
15390395Sru/* signal is 7 bits, 0..63, although it doesn't seem to get to 63.
15490395Sru * silence is 7 bits, 0..63
15590395Sru * quality is 4 bits, 0..15
1562061Sjkh */
15717308Speterstruct w_sigcache {
15838666Sjb        char   macsrc[6]; /* unique MAC address for entry */
15938666Sjb        int    ipsrc;     /* ip address associated with packet */
16017308Speter        int    signal;    /* signal strength of the packet */
16155678Smarcel        int    silence;   /* silence of the packet */
1623626Swollman        int    quality;   /* quality of the packet */
16317308Speter        int    snr;       /* packet has unique age between 1 to MAX_AGE - 1 */
16455678Smarcel};
16555678Smarcel
16655678Smarcel#endif /* _CHIPS_WAVELAN_H */
16755678Smarcel
16855678Smarcel