atomic.h revision 314210
1/*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/i386/include/atomic.h 314210 2017-02-24 16:02:01Z kib $ 27 */ 28#ifndef _MACHINE_ATOMIC_H_ 29#define _MACHINE_ATOMIC_H_ 30 31#ifndef _SYS_CDEFS_H_ 32#error this file needs sys/cdefs.h as a prerequisite 33#endif 34 35#ifdef _KERNEL 36#include <machine/md_var.h> 37#include <machine/specialreg.h> 38#endif 39 40#ifndef __OFFSETOF_MONITORBUF 41/* 42 * __OFFSETOF_MONITORBUF == __pcpu_offset(pc_monitorbuf). 43 * 44 * The open-coded number is used instead of the symbolic expression to 45 * avoid a dependency on sys/pcpu.h in machine/atomic.h consumers. 46 * An assertion in i386/vm_machdep.c ensures that the value is correct. 47 */ 48#define __OFFSETOF_MONITORBUF 0x180 49 50static __inline void 51__mbk(void) 52{ 53 54 __asm __volatile("lock; addl $0,%%fs:%0" 55 : "+m" (*(u_int *)__OFFSETOF_MONITORBUF) : : "memory", "cc"); 56} 57 58static __inline void 59__mbu(void) 60{ 61 62 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory", "cc"); 63} 64#endif 65 66/* 67 * Various simple operations on memory, each of which is atomic in the 68 * presence of interrupts and multiple processors. 69 * 70 * atomic_set_char(P, V) (*(u_char *)(P) |= (V)) 71 * atomic_clear_char(P, V) (*(u_char *)(P) &= ~(V)) 72 * atomic_add_char(P, V) (*(u_char *)(P) += (V)) 73 * atomic_subtract_char(P, V) (*(u_char *)(P) -= (V)) 74 * 75 * atomic_set_short(P, V) (*(u_short *)(P) |= (V)) 76 * atomic_clear_short(P, V) (*(u_short *)(P) &= ~(V)) 77 * atomic_add_short(P, V) (*(u_short *)(P) += (V)) 78 * atomic_subtract_short(P, V) (*(u_short *)(P) -= (V)) 79 * 80 * atomic_set_int(P, V) (*(u_int *)(P) |= (V)) 81 * atomic_clear_int(P, V) (*(u_int *)(P) &= ~(V)) 82 * atomic_add_int(P, V) (*(u_int *)(P) += (V)) 83 * atomic_subtract_int(P, V) (*(u_int *)(P) -= (V)) 84 * atomic_swap_int(P, V) (return (*(u_int *)(P)); *(u_int *)(P) = (V);) 85 * atomic_readandclear_int(P) (return (*(u_int *)(P)); *(u_int *)(P) = 0;) 86 * 87 * atomic_set_long(P, V) (*(u_long *)(P) |= (V)) 88 * atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V)) 89 * atomic_add_long(P, V) (*(u_long *)(P) += (V)) 90 * atomic_subtract_long(P, V) (*(u_long *)(P) -= (V)) 91 * atomic_swap_long(P, V) (return (*(u_long *)(P)); *(u_long *)(P) = (V);) 92 * atomic_readandclear_long(P) (return (*(u_long *)(P)); *(u_long *)(P) = 0;) 93 */ 94 95/* 96 * The above functions are expanded inline in the statically-linked 97 * kernel. Lock prefixes are generated if an SMP kernel is being 98 * built. 99 * 100 * Kernel modules call real functions which are built into the kernel. 101 * This allows kernel modules to be portable between UP and SMP systems. 102 */ 103#if defined(KLD_MODULE) || !defined(__GNUCLIKE_ASM) 104#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 105void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \ 106void atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 107 108int atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src); 109u_int atomic_fetchadd_int(volatile u_int *p, u_int v); 110int atomic_testandset_int(volatile u_int *p, u_int v); 111int atomic_testandclear_int(volatile u_int *p, u_int v); 112void atomic_thread_fence_acq(void); 113void atomic_thread_fence_acq_rel(void); 114void atomic_thread_fence_rel(void); 115void atomic_thread_fence_seq_cst(void); 116 117#define ATOMIC_LOAD(TYPE) \ 118u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p) 119#define ATOMIC_STORE(TYPE) \ 120void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) 121 122int atomic_cmpset_64(volatile uint64_t *, uint64_t, uint64_t); 123uint64_t atomic_load_acq_64(volatile uint64_t *); 124void atomic_store_rel_64(volatile uint64_t *, uint64_t); 125uint64_t atomic_swap_64(volatile uint64_t *, uint64_t); 126 127#else /* !KLD_MODULE && __GNUCLIKE_ASM */ 128 129/* 130 * For userland, always use lock prefixes so that the binaries will run 131 * on both SMP and !SMP systems. 132 */ 133#if defined(SMP) || !defined(_KERNEL) 134#define MPLOCKED "lock ; " 135#else 136#define MPLOCKED 137#endif 138 139/* 140 * The assembly is volatilized to avoid code chunk removal by the compiler. 141 * GCC aggressively reorders operations and memory clobbering is necessary 142 * in order to avoid that for memory barriers. 143 */ 144#define ATOMIC_ASM(NAME, TYPE, OP, CONS, V) \ 145static __inline void \ 146atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 147{ \ 148 __asm __volatile(MPLOCKED OP \ 149 : "+m" (*p) \ 150 : CONS (V) \ 151 : "cc"); \ 152} \ 153 \ 154static __inline void \ 155atomic_##NAME##_barr_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ 156{ \ 157 __asm __volatile(MPLOCKED OP \ 158 : "+m" (*p) \ 159 : CONS (V) \ 160 : "memory", "cc"); \ 161} \ 162struct __hack 163 164/* 165 * Atomic compare and set, used by the mutex functions 166 * 167 * if (*dst == expect) *dst = src (all 32 bit words) 168 * 169 * Returns 0 on failure, non-zero on success 170 */ 171 172static __inline int 173atomic_cmpset_int(volatile u_int *dst, u_int expect, u_int src) 174{ 175 u_char res; 176 177 __asm __volatile( 178 " " MPLOCKED " " 179 " cmpxchgl %3,%1 ; " 180 " sete %0 ; " 181 "# atomic_cmpset_int" 182 : "=q" (res), /* 0 */ 183 "+m" (*dst), /* 1 */ 184 "+a" (expect) /* 2 */ 185 : "r" (src) /* 3 */ 186 : "memory", "cc"); 187 return (res); 188} 189 190/* 191 * Atomically add the value of v to the integer pointed to by p and return 192 * the previous value of *p. 193 */ 194static __inline u_int 195atomic_fetchadd_int(volatile u_int *p, u_int v) 196{ 197 198 __asm __volatile( 199 " " MPLOCKED " " 200 " xaddl %0,%1 ; " 201 "# atomic_fetchadd_int" 202 : "+r" (v), /* 0 */ 203 "+m" (*p) /* 1 */ 204 : : "cc"); 205 return (v); 206} 207 208static __inline int 209atomic_testandset_int(volatile u_int *p, u_int v) 210{ 211 u_char res; 212 213 __asm __volatile( 214 " " MPLOCKED " " 215 " btsl %2,%1 ; " 216 " setc %0 ; " 217 "# atomic_testandset_int" 218 : "=q" (res), /* 0 */ 219 "+m" (*p) /* 1 */ 220 : "Ir" (v & 0x1f) /* 2 */ 221 : "cc"); 222 return (res); 223} 224 225static __inline int 226atomic_testandclear_int(volatile u_int *p, u_int v) 227{ 228 u_char res; 229 230 __asm __volatile( 231 " " MPLOCKED " " 232 " btrl %2,%1 ; " 233 " setc %0 ; " 234 "# atomic_testandclear_int" 235 : "=q" (res), /* 0 */ 236 "+m" (*p) /* 1 */ 237 : "Ir" (v & 0x1f) /* 2 */ 238 : "cc"); 239 return (res); 240} 241 242/* 243 * We assume that a = b will do atomic loads and stores. Due to the 244 * IA32 memory model, a simple store guarantees release semantics. 245 * 246 * However, a load may pass a store if they are performed on distinct 247 * addresses, so we need Store/Load barrier for sequentially 248 * consistent fences in SMP kernels. We use "lock addl $0,mem" for a 249 * Store/Load barrier, as recommended by the AMD Software Optimization 250 * Guide, and not mfence. In the kernel, we use a private per-cpu 251 * cache line for "mem", to avoid introducing false data 252 * dependencies. In user space, we use the word at the top of the 253 * stack. 254 * 255 * For UP kernels, however, the memory of the single processor is 256 * always consistent, so we only need to stop the compiler from 257 * reordering accesses in a way that violates the semantics of acquire 258 * and release. 259 */ 260 261#if defined(_KERNEL) 262#if defined(SMP) 263#define __storeload_barrier() __mbk() 264#else /* _KERNEL && UP */ 265#define __storeload_barrier() __compiler_membar() 266#endif /* SMP */ 267#else /* !_KERNEL */ 268#define __storeload_barrier() __mbu() 269#endif /* _KERNEL*/ 270 271#define ATOMIC_LOAD(TYPE) \ 272static __inline u_##TYPE \ 273atomic_load_acq_##TYPE(volatile u_##TYPE *p) \ 274{ \ 275 u_##TYPE res; \ 276 \ 277 res = *p; \ 278 __compiler_membar(); \ 279 return (res); \ 280} \ 281struct __hack 282 283#define ATOMIC_STORE(TYPE) \ 284static __inline void \ 285atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \ 286{ \ 287 \ 288 __compiler_membar(); \ 289 *p = v; \ 290} \ 291struct __hack 292 293static __inline void 294atomic_thread_fence_acq(void) 295{ 296 297 __compiler_membar(); 298} 299 300static __inline void 301atomic_thread_fence_rel(void) 302{ 303 304 __compiler_membar(); 305} 306 307static __inline void 308atomic_thread_fence_acq_rel(void) 309{ 310 311 __compiler_membar(); 312} 313 314static __inline void 315atomic_thread_fence_seq_cst(void) 316{ 317 318 __storeload_barrier(); 319} 320 321#ifdef _KERNEL 322 323#ifdef WANT_FUNCTIONS 324int atomic_cmpset_64_i386(volatile uint64_t *, uint64_t, uint64_t); 325int atomic_cmpset_64_i586(volatile uint64_t *, uint64_t, uint64_t); 326uint64_t atomic_load_acq_64_i386(volatile uint64_t *); 327uint64_t atomic_load_acq_64_i586(volatile uint64_t *); 328void atomic_store_rel_64_i386(volatile uint64_t *, uint64_t); 329void atomic_store_rel_64_i586(volatile uint64_t *, uint64_t); 330uint64_t atomic_swap_64_i386(volatile uint64_t *, uint64_t); 331uint64_t atomic_swap_64_i586(volatile uint64_t *, uint64_t); 332#endif 333 334/* I486 does not support SMP or CMPXCHG8B. */ 335static __inline int 336atomic_cmpset_64_i386(volatile uint64_t *dst, uint64_t expect, uint64_t src) 337{ 338 volatile uint32_t *p; 339 u_char res; 340 341 p = (volatile uint32_t *)dst; 342 __asm __volatile( 343 " pushfl ; " 344 " cli ; " 345 " xorl %1,%%eax ; " 346 " xorl %2,%%edx ; " 347 " orl %%edx,%%eax ; " 348 " jne 1f ; " 349 " movl %4,%1 ; " 350 " movl %5,%2 ; " 351 "1: " 352 " sete %3 ; " 353 " popfl" 354 : "+A" (expect), /* 0 */ 355 "+m" (*p), /* 1 */ 356 "+m" (*(p + 1)), /* 2 */ 357 "=q" (res) /* 3 */ 358 : "r" ((uint32_t)src), /* 4 */ 359 "r" ((uint32_t)(src >> 32)) /* 5 */ 360 : "memory", "cc"); 361 return (res); 362} 363 364static __inline uint64_t 365atomic_load_acq_64_i386(volatile uint64_t *p) 366{ 367 volatile uint32_t *q; 368 uint64_t res; 369 370 q = (volatile uint32_t *)p; 371 __asm __volatile( 372 " pushfl ; " 373 " cli ; " 374 " movl %1,%%eax ; " 375 " movl %2,%%edx ; " 376 " popfl" 377 : "=&A" (res) /* 0 */ 378 : "m" (*q), /* 1 */ 379 "m" (*(q + 1)) /* 2 */ 380 : "memory"); 381 return (res); 382} 383 384static __inline void 385atomic_store_rel_64_i386(volatile uint64_t *p, uint64_t v) 386{ 387 volatile uint32_t *q; 388 389 q = (volatile uint32_t *)p; 390 __asm __volatile( 391 " pushfl ; " 392 " cli ; " 393 " movl %%eax,%0 ; " 394 " movl %%edx,%1 ; " 395 " popfl" 396 : "=m" (*q), /* 0 */ 397 "=m" (*(q + 1)) /* 1 */ 398 : "A" (v) /* 2 */ 399 : "memory"); 400} 401 402static __inline uint64_t 403atomic_swap_64_i386(volatile uint64_t *p, uint64_t v) 404{ 405 volatile uint32_t *q; 406 uint64_t res; 407 408 q = (volatile uint32_t *)p; 409 __asm __volatile( 410 " pushfl ; " 411 " cli ; " 412 " movl %1,%%eax ; " 413 " movl %2,%%edx ; " 414 " movl %4,%2 ; " 415 " movl %3,%1 ; " 416 " popfl" 417 : "=&A" (res), /* 0 */ 418 "+m" (*q), /* 1 */ 419 "+m" (*(q + 1)) /* 2 */ 420 : "r" ((uint32_t)v), /* 3 */ 421 "r" ((uint32_t)(v >> 32))); /* 4 */ 422 return (res); 423} 424 425static __inline int 426atomic_cmpset_64_i586(volatile uint64_t *dst, uint64_t expect, uint64_t src) 427{ 428 u_char res; 429 430 __asm __volatile( 431 " " MPLOCKED " " 432 " cmpxchg8b %1 ; " 433 " sete %0" 434 : "=q" (res), /* 0 */ 435 "+m" (*dst), /* 1 */ 436 "+A" (expect) /* 2 */ 437 : "b" ((uint32_t)src), /* 3 */ 438 "c" ((uint32_t)(src >> 32)) /* 4 */ 439 : "memory", "cc"); 440 return (res); 441} 442 443static __inline uint64_t 444atomic_load_acq_64_i586(volatile uint64_t *p) 445{ 446 uint64_t res; 447 448 __asm __volatile( 449 " movl %%ebx,%%eax ; " 450 " movl %%ecx,%%edx ; " 451 " " MPLOCKED " " 452 " cmpxchg8b %1" 453 : "=&A" (res), /* 0 */ 454 "+m" (*p) /* 1 */ 455 : : "memory", "cc"); 456 return (res); 457} 458 459static __inline void 460atomic_store_rel_64_i586(volatile uint64_t *p, uint64_t v) 461{ 462 463 __asm __volatile( 464 " movl %%eax,%%ebx ; " 465 " movl %%edx,%%ecx ; " 466 "1: " 467 " " MPLOCKED " " 468 " cmpxchg8b %0 ; " 469 " jne 1b" 470 : "+m" (*p), /* 0 */ 471 "+A" (v) /* 1 */ 472 : : "ebx", "ecx", "memory", "cc"); 473} 474 475static __inline uint64_t 476atomic_swap_64_i586(volatile uint64_t *p, uint64_t v) 477{ 478 479 __asm __volatile( 480 " movl %%eax,%%ebx ; " 481 " movl %%edx,%%ecx ; " 482 "1: " 483 " " MPLOCKED " " 484 " cmpxchg8b %0 ; " 485 " jne 1b" 486 : "+m" (*p), /* 0 */ 487 "+A" (v) /* 1 */ 488 : : "ebx", "ecx", "memory", "cc"); 489 return (v); 490} 491 492static __inline int 493atomic_cmpset_64(volatile uint64_t *dst, uint64_t expect, uint64_t src) 494{ 495 496 if ((cpu_feature & CPUID_CX8) == 0) 497 return (atomic_cmpset_64_i386(dst, expect, src)); 498 else 499 return (atomic_cmpset_64_i586(dst, expect, src)); 500} 501 502static __inline uint64_t 503atomic_load_acq_64(volatile uint64_t *p) 504{ 505 506 if ((cpu_feature & CPUID_CX8) == 0) 507 return (atomic_load_acq_64_i386(p)); 508 else 509 return (atomic_load_acq_64_i586(p)); 510} 511 512static __inline void 513atomic_store_rel_64(volatile uint64_t *p, uint64_t v) 514{ 515 516 if ((cpu_feature & CPUID_CX8) == 0) 517 atomic_store_rel_64_i386(p, v); 518 else 519 atomic_store_rel_64_i586(p, v); 520} 521 522static __inline uint64_t 523atomic_swap_64(volatile uint64_t *p, uint64_t v) 524{ 525 526 if ((cpu_feature & CPUID_CX8) == 0) 527 return (atomic_swap_64_i386(p, v)); 528 else 529 return (atomic_swap_64_i586(p, v)); 530} 531 532#endif /* _KERNEL */ 533 534#endif /* KLD_MODULE || !__GNUCLIKE_ASM */ 535 536ATOMIC_ASM(set, char, "orb %b1,%0", "iq", v); 537ATOMIC_ASM(clear, char, "andb %b1,%0", "iq", ~v); 538ATOMIC_ASM(add, char, "addb %b1,%0", "iq", v); 539ATOMIC_ASM(subtract, char, "subb %b1,%0", "iq", v); 540 541ATOMIC_ASM(set, short, "orw %w1,%0", "ir", v); 542ATOMIC_ASM(clear, short, "andw %w1,%0", "ir", ~v); 543ATOMIC_ASM(add, short, "addw %w1,%0", "ir", v); 544ATOMIC_ASM(subtract, short, "subw %w1,%0", "ir", v); 545 546ATOMIC_ASM(set, int, "orl %1,%0", "ir", v); 547ATOMIC_ASM(clear, int, "andl %1,%0", "ir", ~v); 548ATOMIC_ASM(add, int, "addl %1,%0", "ir", v); 549ATOMIC_ASM(subtract, int, "subl %1,%0", "ir", v); 550 551ATOMIC_ASM(set, long, "orl %1,%0", "ir", v); 552ATOMIC_ASM(clear, long, "andl %1,%0", "ir", ~v); 553ATOMIC_ASM(add, long, "addl %1,%0", "ir", v); 554ATOMIC_ASM(subtract, long, "subl %1,%0", "ir", v); 555 556#define ATOMIC_LOADSTORE(TYPE) \ 557 ATOMIC_LOAD(TYPE); \ 558 ATOMIC_STORE(TYPE) 559 560ATOMIC_LOADSTORE(char); 561ATOMIC_LOADSTORE(short); 562ATOMIC_LOADSTORE(int); 563ATOMIC_LOADSTORE(long); 564 565#undef ATOMIC_ASM 566#undef ATOMIC_LOAD 567#undef ATOMIC_STORE 568#undef ATOMIC_LOADSTORE 569 570#ifndef WANT_FUNCTIONS 571 572static __inline int 573atomic_cmpset_long(volatile u_long *dst, u_long expect, u_long src) 574{ 575 576 return (atomic_cmpset_int((volatile u_int *)dst, (u_int)expect, 577 (u_int)src)); 578} 579 580static __inline u_long 581atomic_fetchadd_long(volatile u_long *p, u_long v) 582{ 583 584 return (atomic_fetchadd_int((volatile u_int *)p, (u_int)v)); 585} 586 587static __inline int 588atomic_testandset_long(volatile u_long *p, u_int v) 589{ 590 591 return (atomic_testandset_int((volatile u_int *)p, v)); 592} 593 594static __inline int 595atomic_testandclear_long(volatile u_long *p, u_int v) 596{ 597 598 return (atomic_testandclear_int((volatile u_int *)p, v)); 599} 600 601/* Read the current value and store a new value in the destination. */ 602#ifdef __GNUCLIKE_ASM 603 604static __inline u_int 605atomic_swap_int(volatile u_int *p, u_int v) 606{ 607 608 __asm __volatile( 609 " xchgl %1,%0 ; " 610 "# atomic_swap_int" 611 : "+r" (v), /* 0 */ 612 "+m" (*p)); /* 1 */ 613 return (v); 614} 615 616static __inline u_long 617atomic_swap_long(volatile u_long *p, u_long v) 618{ 619 620 return (atomic_swap_int((volatile u_int *)p, (u_int)v)); 621} 622 623#else /* !__GNUCLIKE_ASM */ 624 625u_int atomic_swap_int(volatile u_int *p, u_int v); 626u_long atomic_swap_long(volatile u_long *p, u_long v); 627 628#endif /* __GNUCLIKE_ASM */ 629 630#define atomic_set_acq_char atomic_set_barr_char 631#define atomic_set_rel_char atomic_set_barr_char 632#define atomic_clear_acq_char atomic_clear_barr_char 633#define atomic_clear_rel_char atomic_clear_barr_char 634#define atomic_add_acq_char atomic_add_barr_char 635#define atomic_add_rel_char atomic_add_barr_char 636#define atomic_subtract_acq_char atomic_subtract_barr_char 637#define atomic_subtract_rel_char atomic_subtract_barr_char 638 639#define atomic_set_acq_short atomic_set_barr_short 640#define atomic_set_rel_short atomic_set_barr_short 641#define atomic_clear_acq_short atomic_clear_barr_short 642#define atomic_clear_rel_short atomic_clear_barr_short 643#define atomic_add_acq_short atomic_add_barr_short 644#define atomic_add_rel_short atomic_add_barr_short 645#define atomic_subtract_acq_short atomic_subtract_barr_short 646#define atomic_subtract_rel_short atomic_subtract_barr_short 647 648#define atomic_set_acq_int atomic_set_barr_int 649#define atomic_set_rel_int atomic_set_barr_int 650#define atomic_clear_acq_int atomic_clear_barr_int 651#define atomic_clear_rel_int atomic_clear_barr_int 652#define atomic_add_acq_int atomic_add_barr_int 653#define atomic_add_rel_int atomic_add_barr_int 654#define atomic_subtract_acq_int atomic_subtract_barr_int 655#define atomic_subtract_rel_int atomic_subtract_barr_int 656#define atomic_cmpset_acq_int atomic_cmpset_int 657#define atomic_cmpset_rel_int atomic_cmpset_int 658 659#define atomic_set_acq_long atomic_set_barr_long 660#define atomic_set_rel_long atomic_set_barr_long 661#define atomic_clear_acq_long atomic_clear_barr_long 662#define atomic_clear_rel_long atomic_clear_barr_long 663#define atomic_add_acq_long atomic_add_barr_long 664#define atomic_add_rel_long atomic_add_barr_long 665#define atomic_subtract_acq_long atomic_subtract_barr_long 666#define atomic_subtract_rel_long atomic_subtract_barr_long 667#define atomic_cmpset_acq_long atomic_cmpset_long 668#define atomic_cmpset_rel_long atomic_cmpset_long 669 670#define atomic_readandclear_int(p) atomic_swap_int(p, 0) 671#define atomic_readandclear_long(p) atomic_swap_long(p, 0) 672 673/* Operations on 8-bit bytes. */ 674#define atomic_set_8 atomic_set_char 675#define atomic_set_acq_8 atomic_set_acq_char 676#define atomic_set_rel_8 atomic_set_rel_char 677#define atomic_clear_8 atomic_clear_char 678#define atomic_clear_acq_8 atomic_clear_acq_char 679#define atomic_clear_rel_8 atomic_clear_rel_char 680#define atomic_add_8 atomic_add_char 681#define atomic_add_acq_8 atomic_add_acq_char 682#define atomic_add_rel_8 atomic_add_rel_char 683#define atomic_subtract_8 atomic_subtract_char 684#define atomic_subtract_acq_8 atomic_subtract_acq_char 685#define atomic_subtract_rel_8 atomic_subtract_rel_char 686#define atomic_load_acq_8 atomic_load_acq_char 687#define atomic_store_rel_8 atomic_store_rel_char 688 689/* Operations on 16-bit words. */ 690#define atomic_set_16 atomic_set_short 691#define atomic_set_acq_16 atomic_set_acq_short 692#define atomic_set_rel_16 atomic_set_rel_short 693#define atomic_clear_16 atomic_clear_short 694#define atomic_clear_acq_16 atomic_clear_acq_short 695#define atomic_clear_rel_16 atomic_clear_rel_short 696#define atomic_add_16 atomic_add_short 697#define atomic_add_acq_16 atomic_add_acq_short 698#define atomic_add_rel_16 atomic_add_rel_short 699#define atomic_subtract_16 atomic_subtract_short 700#define atomic_subtract_acq_16 atomic_subtract_acq_short 701#define atomic_subtract_rel_16 atomic_subtract_rel_short 702#define atomic_load_acq_16 atomic_load_acq_short 703#define atomic_store_rel_16 atomic_store_rel_short 704 705/* Operations on 32-bit double words. */ 706#define atomic_set_32 atomic_set_int 707#define atomic_set_acq_32 atomic_set_acq_int 708#define atomic_set_rel_32 atomic_set_rel_int 709#define atomic_clear_32 atomic_clear_int 710#define atomic_clear_acq_32 atomic_clear_acq_int 711#define atomic_clear_rel_32 atomic_clear_rel_int 712#define atomic_add_32 atomic_add_int 713#define atomic_add_acq_32 atomic_add_acq_int 714#define atomic_add_rel_32 atomic_add_rel_int 715#define atomic_subtract_32 atomic_subtract_int 716#define atomic_subtract_acq_32 atomic_subtract_acq_int 717#define atomic_subtract_rel_32 atomic_subtract_rel_int 718#define atomic_load_acq_32 atomic_load_acq_int 719#define atomic_store_rel_32 atomic_store_rel_int 720#define atomic_cmpset_32 atomic_cmpset_int 721#define atomic_cmpset_acq_32 atomic_cmpset_acq_int 722#define atomic_cmpset_rel_32 atomic_cmpset_rel_int 723#define atomic_swap_32 atomic_swap_int 724#define atomic_readandclear_32 atomic_readandclear_int 725#define atomic_fetchadd_32 atomic_fetchadd_int 726#define atomic_testandset_32 atomic_testandset_int 727#define atomic_testandclear_32 atomic_testandclear_int 728 729/* Operations on pointers. */ 730#define atomic_set_ptr(p, v) \ 731 atomic_set_int((volatile u_int *)(p), (u_int)(v)) 732#define atomic_set_acq_ptr(p, v) \ 733 atomic_set_acq_int((volatile u_int *)(p), (u_int)(v)) 734#define atomic_set_rel_ptr(p, v) \ 735 atomic_set_rel_int((volatile u_int *)(p), (u_int)(v)) 736#define atomic_clear_ptr(p, v) \ 737 atomic_clear_int((volatile u_int *)(p), (u_int)(v)) 738#define atomic_clear_acq_ptr(p, v) \ 739 atomic_clear_acq_int((volatile u_int *)(p), (u_int)(v)) 740#define atomic_clear_rel_ptr(p, v) \ 741 atomic_clear_rel_int((volatile u_int *)(p), (u_int)(v)) 742#define atomic_add_ptr(p, v) \ 743 atomic_add_int((volatile u_int *)(p), (u_int)(v)) 744#define atomic_add_acq_ptr(p, v) \ 745 atomic_add_acq_int((volatile u_int *)(p), (u_int)(v)) 746#define atomic_add_rel_ptr(p, v) \ 747 atomic_add_rel_int((volatile u_int *)(p), (u_int)(v)) 748#define atomic_subtract_ptr(p, v) \ 749 atomic_subtract_int((volatile u_int *)(p), (u_int)(v)) 750#define atomic_subtract_acq_ptr(p, v) \ 751 atomic_subtract_acq_int((volatile u_int *)(p), (u_int)(v)) 752#define atomic_subtract_rel_ptr(p, v) \ 753 atomic_subtract_rel_int((volatile u_int *)(p), (u_int)(v)) 754#define atomic_load_acq_ptr(p) \ 755 atomic_load_acq_int((volatile u_int *)(p)) 756#define atomic_store_rel_ptr(p, v) \ 757 atomic_store_rel_int((volatile u_int *)(p), (v)) 758#define atomic_cmpset_ptr(dst, old, new) \ 759 atomic_cmpset_int((volatile u_int *)(dst), (u_int)(old), (u_int)(new)) 760#define atomic_cmpset_acq_ptr(dst, old, new) \ 761 atomic_cmpset_acq_int((volatile u_int *)(dst), (u_int)(old), \ 762 (u_int)(new)) 763#define atomic_cmpset_rel_ptr(dst, old, new) \ 764 atomic_cmpset_rel_int((volatile u_int *)(dst), (u_int)(old), \ 765 (u_int)(new)) 766#define atomic_swap_ptr(p, v) \ 767 atomic_swap_int((volatile u_int *)(p), (u_int)(v)) 768#define atomic_readandclear_ptr(p) \ 769 atomic_readandclear_int((volatile u_int *)(p)) 770 771#endif /* !WANT_FUNCTIONS */ 772 773#if defined(_KERNEL) 774#define mb() __mbk() 775#define wmb() __mbk() 776#define rmb() __mbk() 777#else 778#define mb() __mbu() 779#define wmb() __mbu() 780#define rmb() __mbu() 781#endif 782 783#endif /* !_MACHINE_ATOMIC_H_ */ 784